dtemirbulatov (Dinar Temirbulatov)
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Sep 17 2015, 10:06 AM (116 w, 5 d)

Recent Activity

Tue, Nov 28

dtemirbulatov added inline comments to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..
Tue, Nov 28, 10:53 PM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Fix all issues related to the last commit attempt.

Tue, Nov 28, 10:44 PM

Wed, Nov 22

dtemirbulatov updated the diff for D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Update description in LangRef.rst.

Wed, Nov 22, 4:10 PM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Update description in LangRef.rst.

Wed, Nov 22, 4:09 PM

Tue, Nov 21

dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Rebase and fix remarks.

Tue, Nov 21, 2:44 PM
dtemirbulatov updated the diff for D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Rebase and fix remarks.

Tue, Nov 21, 2:42 PM

Mon, Nov 13

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Update after NFC with add test/Transforms/SLPVectorizer/SystemZ/lit.local.cfg to the tree.

Mon, Nov 13, 10:39 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Fixed two issues associated with last build failures.

  1. llvm IR standard violation with second parameter always as integer 32-bit for Shl, LShr, AShr, but according to https://llvm.org/docs/LangRef.html#lshr-instruction both arguments of those instructions must be the same type. I have a testcase for the issue, but I think it is not required, please comment if you think otherwise.
  2. allow SystemZ SLP tests only when SystemZ is supported in a build.
Mon, Nov 13, 10:16 AM

Nov 7 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Formatted.

Nov 7 2017, 11:43 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Fixed typo.

Nov 7 2017, 11:32 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Update to the criteria to "(SameOrAlt <= VL.size() / 2) return;". I already tested that solution before.

Nov 7 2017, 11:28 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Updated this criteria for the same or alternative opcodes in the way suggested by Alexey and I tested the solution widely on different platforms and I was not able to encounter code where the same or alternative opcodes are more than 1 or 2 or the same or alternative opcode > than operations with different opcodes, except equal to one. But still the new criteria looks better to me.

Nov 7 2017, 10:43 AM

Oct 25 2017

dtemirbulatov updated the diff for D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Add LangRef.rst change. Small changes in SLPVectorizer.cpp.

Oct 25 2017, 3:38 PM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Add LangRef.rst change, update test to check metadata values.

Oct 25 2017, 3:35 PM
dtemirbulatov updated the diff for D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Update for solution, here it uses metadata "speculation.marker" with set of offsets instead of maximum offset as before, thread for discussion http://lists.llvm.org/pipermail/llvm-dev/2017-September/117782.html.

Oct 25 2017, 12:26 AM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Update for solution, here it uses metadata "speculation.marker" with set of offsets instead of maximum offset as before, thread for discussion http://lists.llvm.org/pipermail/llvm-dev/2017-September/117782.html.

Oct 25 2017, 12:25 AM

Oct 10 2017

dtemirbulatov added a comment to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Ping

Oct 10 2017, 5:44 AM

Oct 9 2017

dtemirbulatov added inline comments to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..
Oct 9 2017, 6:06 AM

Oct 5 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Found trash in the previous change, Update after fix ABataev remarks.

Oct 5 2017, 2:17 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Update after ABataev remarks

Oct 5 2017, 2:10 AM

Oct 3 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Update with solution for the last commit issues with that looks more appropriate to me with just avoiding any vectors like [ operand, operand, operation, operand] or [load, load, operation, load] in a scheduling bundle, with this solution I have not noticed any bitcode regressions(efficiency) with provided testcase pr34619.ll. I have checked all list of issues from the previous build with this change.

Oct 3 2017, 3:17 AM

Oct 1 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Resolved all issues associated with previous commit.

Oct 1 2017, 5:34 AM

Sep 26 2017

dtemirbulatov added a comment to D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

I think something might be missing here. You're forming a 4x wide load, but you've only proven dereferenceability for offsets 0, 1, 3. (i.e. not 2). How do we know it's safe to dereference between the two elements 1 & 3?

well, it is a maximum reference that was recorded there in InstCombine, that implies 0, 1, 2 and 3. And if you are saying that 0, 1, 3 dereferenceable and 2-nd is not at the same time then this solution is not correct.

Sep 26 2017, 3:48 PM
dtemirbulatov added a comment to D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

are you still looking at some other kind of metadata solution? Did you mean for "metadata" here to mean the intrinsic you're proposing?

No, I am happy with intrinsic solution.

Sep 26 2017, 3:30 PM

Sep 25 2017

dtemirbulatov updated the diff for D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Fix review remarks and add an aggregate pointer as intrinsic's second parameter, remove getNextNode() usage.

Sep 25 2017, 5:02 AM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Fix recordDeadLoad() parameter lining with clang-format.

Sep 25 2017, 5:02 AM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Fix review remarks and add an aggregate pointer intrinsic's second parameter.

Sep 25 2017, 5:02 AM
dtemirbulatov updated the diff for D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

add missed test in the last change.

Sep 25 2017, 5:02 AM
dtemirbulatov added a comment to D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Thanks for working on this. Please post an RFC on llvm-dev about the intrinsic and how you intend to use it. You can reference this review, but we should make sure that we have design consensus before proceeding here.

Sep 25 2017, 5:02 AM
dtemirbulatov added a comment to D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Why not leave the original load in place, and tag the load metadata like !speculation_marker ? In either case, this needs a LangRef entry.

Re-reading, I messed up the phrasing there. I meant to say two things:

  • You could consider leaving the original load in place, and tag it with something like !speculation_marker. This metadata would indicate to passes like DCE that said load should not be eliminated till the very end of the optimization pipeline (so that we keep the optimization information for as long as possible). This does block optimizations though (like you will not be able to sink stores across this now present load, something you may have been able to do with the intrinsic you're introducing, though not without figuring out a way to denote it as not reading memory), but it has the upside of not introducing a new intrinsic.
  • Irrespective of whether you decide to go with the intrinsic or the metadata approach, please also update the language reference with an entry describing the semantics of this new thing.
Sep 25 2017, 5:02 AM
dtemirbulatov added a comment to D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Some style comments as the poor bracing/indentation makes it difficult to grok - more thorough review needs to wait until you've addressed @hfinkel's comments on D37648 about phantom mem intrinsics

Sep 25 2017, 5:02 AM

Sep 14 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Update after RKSimon's remarks.

Sep 14 2017, 2:57 AM

Sep 11 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Found typo in previous change. Update.

Sep 11 2017, 3:45 AM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Rebase

Sep 11 2017, 2:31 AM

Sep 8 2017

dtemirbulatov created D37648: [SLPVectorizer] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.
Sep 8 2017, 4:08 PM

Sep 7 2017

dtemirbulatov created D37579: [InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.
Sep 7 2017, 11:29 AM

Sep 6 2017

dtemirbulatov updated the diff for D37212: [SLPVectorizer] Add struct InstructionsState, NFC.

reduce the change a bit further and rebase.

Sep 6 2017, 8:15 AM

Sep 4 2017

dtemirbulatov added a comment to D37212: [SLPVectorizer] Add struct InstructionsState, NFC.

ping

Sep 4 2017, 6:13 AM

Aug 31 2017

dtemirbulatov updated the diff for D37212: [SLPVectorizer] Add struct InstructionsState, NFC.

rebase

Aug 31 2017, 3:05 PM

Aug 28 2017

dtemirbulatov created D37212: [SLPVectorizer] Add struct InstructionsState, NFC.
Aug 28 2017, 6:23 AM

Aug 20 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Rebase

Aug 20 2017, 10:45 PM

Aug 18 2017

dtemirbulatov updated the diff for D36766: Reorder operands with provided Opcode.

Remove getDefaultConstantForOpcode function for now.

Aug 18 2017, 5:49 AM

Aug 17 2017

dtemirbulatov updated the diff for D36766: Reorder operands with provided Opcode.

test update to simpler

Aug 17 2017, 7:01 PM

Aug 16 2017

dtemirbulatov updated the diff for D36766: Reorder operands with provided Opcode.

remove extra flag -slp-vectorizer in test.

Aug 16 2017, 7:57 PM
dtemirbulatov updated the diff for D36766: Reorder operands with provided Opcode.

update testcase.

Aug 16 2017, 7:53 PM

Aug 15 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

update after RKSimon's remarks.

Aug 15 2017, 9:08 PM
dtemirbulatov created D36766: Reorder operands with provided Opcode.
Aug 15 2017, 1:51 PM

Aug 14 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Rebase

Aug 14 2017, 7:45 PM
dtemirbulatov updated the diff for D36518: [SLPVectorizer] Schedule bundle with different opcodes..

correct test filename spelling.

Aug 14 2017, 2:40 AM

Aug 13 2017

dtemirbulatov updated the diff for D36518: [SLPVectorizer] Schedule bundle with different opcodes..

update test.

Aug 13 2017, 9:53 PM
dtemirbulatov added inline comments to D36518: [SLPVectorizer] Schedule bundle with different opcodes..
Aug 13 2017, 9:40 PM

Aug 12 2017

dtemirbulatov updated the diff for D36518: [SLPVectorizer] Schedule bundle with different opcodes..

Update after RKSimon's remarks and replace testcase for more appropriate.

Aug 12 2017, 12:09 PM

Aug 10 2017

dtemirbulatov updated the diff for D36518: [SLPVectorizer] Schedule bundle with different opcodes..

update after RKSimon remarks and add test.

Aug 10 2017, 8:05 PM
dtemirbulatov updated the diff for D36518: [SLPVectorizer] Schedule bundle with different opcodes..

Test cases?

Well, I could add tests here, but it is a like a main flow of this algorithm and it should be tested already here.

Aug 10 2017, 4:55 AM
dtemirbulatov added inline comments to D36518: [SLPVectorizer] Schedule bundle with different opcodes..
Aug 10 2017, 4:52 AM

Aug 9 2017

dtemirbulatov created D36518: [SLPVectorizer] Schedule bundle with different opcodes..
Aug 9 2017, 6:45 AM

Aug 8 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Remove technical comments

Aug 8 2017, 12:03 PM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Fixed issue with horizontal-list.ll.

Aug 8 2017, 11:58 AM

Aug 7 2017

dtemirbulatov added a comment to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Oops, I just noticed that we have lost flag in horizontal-list.ll , I will look at the issue.

Aug 7 2017, 7:23 PM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

Rebase

Aug 7 2017, 7:20 PM

Aug 2 2017

dtemirbulatov updated the diff for D35965: [X86] SET0 to use XMM registers where possible PR26018 PR32862 2/2.

Rebase, remove all "End function" lines.

Aug 2 2017, 10:54 AM

Aug 1 2017

dtemirbulatov updated the diff for D35965: [X86] SET0 to use XMM registers where possible PR26018 PR32862 2/2.

Reversed back the last change.

Aug 1 2017, 12:28 AM

Jul 31 2017

dtemirbulatov updated the diff for D35965: [X86] SET0 to use XMM registers where possible PR26018 PR32862 2/2.

update after Craig's remark.

Jul 31 2017, 5:01 AM

Jul 30 2017

dtemirbulatov updated the diff for D35965: [X86] SET0 to use XMM registers where possible PR26018 PR32862 2/2.

Fix "change to a subregister" issue pointed by Craig.

Jul 30 2017, 2:18 AM

Jul 27 2017

dtemirbulatov created D35965: [X86] SET0 to use XMM registers where possible PR26018 PR32862 2/2.
Jul 27 2017, 4:27 PM
dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

Update to vector-shuffle-combining-avx.ll

Jul 27 2017, 7:27 AM
dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

update with X86::AVX512_256_SET0 included, please ignore my last comment

Jul 27 2017, 6:08 AM
dtemirbulatov added a comment to D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

we don't need to change X86::AVX512_256_SET0, it is already using X86::sub_ymm there, I have not seen any ZMM to YMM change in the diff.

Jul 27 2017, 5:27 AM
dtemirbulatov added a comment to D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

ok, thanks, I will redo the change.

Jul 27 2017, 3:01 AM

Jul 26 2017

dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

Update after RKSimon's remarks.

Jul 26 2017, 3:57 PM
dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

We decided to split this change into two AVX and AVX512 , this is part one AVX and AVX2.

Jul 26 2017, 12:21 PM
dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

updated manually vec_uint_to_fp-fastmath.ll, memset.ll

Jul 26 2017, 9:29 AM
dtemirbulatov added a comment to D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

and memset.ll, sorry.

Jul 26 2017, 8:56 AM
dtemirbulatov added a comment to D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

oh, I missed that vec_uint_to_fp-fastmath.ll should be updated manually. I will redo my change.

Jul 26 2017, 8:55 AM
dtemirbulatov updated the diff for D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

add X86::AVX512_256_SET0 handling, format, rebase

Jul 26 2017, 8:38 AM

Jul 25 2017

dtemirbulatov added a comment to D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .

oh, I missed "X86::AVX512_256_SET0:" case , I have to check some testcases, I think I saw there something incorrect. I will redo my change.

Jul 25 2017, 7:44 AM
dtemirbulatov created D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862 .
Jul 25 2017, 7:36 AM
dtemirbulatov added a comment to D35769: Allow setInsertPointAfterBundle to handle vectors with different opcodes.

Ping.

Jul 25 2017, 6:23 AM

Jul 22 2017

dtemirbulatov created D35769: Allow setInsertPointAfterBundle to handle vectors with different opcodes.
Jul 22 2017, 3:05 PM

Jul 21 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

rebase after recent changes.

Jul 21 2017, 9:15 AM

Jul 19 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

rebase

Jul 19 2017, 5:49 AM

Jul 14 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

rebase to the current tree.

Jul 14 2017, 3:48 AM
dtemirbulatov updated the diff for D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.

update after rksimon's remarks.

Jul 14 2017, 3:43 AM

Jul 13 2017

dtemirbulatov updated the diff for D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.

Fixed issue with test/Transforms/SLPVectorizer/X86/horizontal-list.ll, Merged two versions of propagateIRFlags into one.

Jul 13 2017, 12:57 PM
dtemirbulatov added inline comments to D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.
Jul 13 2017, 12:54 AM
dtemirbulatov added a comment to D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.

Resulting in to:
VL[0]: %r1 = add i32 %arg, undef
VL[1]: %r2 = add nsw i32 %r1, undef
VL[2]: %r3 = add nsw i32 %r2, undef
VL[3]: %r4 = add nsw i32 %r3, undef
VL[4]: %r5 = add nsw i32 %r4, undef

Jul 13 2017, 12:30 AM
dtemirbulatov added a comment to D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.

I'm not sure if Z having those flags is on purpose, though. And I don't see what we get from that.

Please tell me if I misunderstood something. I'm not the most familiar with the SLP vectorizer.

Usually it should have flags in common and it collects those flags see "Intersection->andIRFlags(V);" in the loop across all VL,
but I have one example from test/Transforms/SLPVectorizer/X86/horizontal-list.ll where NUW flag was canceled by NSW.
VL[0]: %r1 = add nuw i32 %arg, undef
VL[1]: %r2 = add nsw i32 %r1, undef
VL[2]: %r3 = add nsw i32 %r2, undef
VL[3]: %r4 = add nsw i32 %r3, undef
VL[4]: %r5 = add nsw i32 %r4, undef

Jul 13 2017, 12:18 AM

Jul 12 2017

dtemirbulatov added a comment to D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.

I don't get what you want to do here, sorry.
As I see it, in all the uses of propagateIRFlagsWithOp(X, Y, Z), we have Z == Y[0]. Which will end up being *almost* the same as the propagateIRFlags but with the side-effect that Z will also have those flags.

propagateIRFlagsWithOp only collects flags from Y if Y.Code == Z.Code while propagateIRFlags copies any flag from Y.

Jul 12 2017, 9:52 AM
dtemirbulatov added inline comments to D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.
Jul 12 2017, 8:33 AM

Jul 11 2017

dtemirbulatov updated subscribers of D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.
Jul 11 2017, 10:51 PM
dtemirbulatov created D35292: [SLPVectorizer] Add propagateIRFlagsWithOp() function to propagate IRFlags for specific Operation.
Jul 11 2017, 10:50 PM

Jul 9 2017

dtemirbulatov abandoned D35139: [SLPVectorizer][InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.

Abandoning review due to : there should separate reviews for one for InstCombine Pass and another one for SLP, and dereferenceable_or_null metadata can only be applied to loads of a pointer type.

Jul 9 2017, 10:03 PM
dtemirbulatov created D35139: [SLPVectorizer][InstCombine] Fix PR21780 Expansion of 256 bit vector loads fails to fold into shuffles.
Jul 9 2017, 6:13 AM

Jul 4 2017

dtemirbulatov added inline comments to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..
Jul 4 2017, 5:58 PM

Jun 30 2017

dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

update after D34756 commit.

Jun 30 2017, 4:04 PM

Jun 28 2017

dtemirbulatov created D34756: [SLPVectorizer] Introducing getTreeEntry() [NFC].
Jun 28 2017, 8:20 AM

Jun 19 2017

dtemirbulatov added inline comments to D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..
Jun 19 2017, 5:56 PM
dtemirbulatov updated the diff for D28907: [SLP] Fix for PR30787: Failure to beneficially vectorize 'copyable' elements in integer binary ops..

update after rksimon's remarks.

Jun 19 2017, 5:45 PM

Jun 15 2017

dtemirbulatov updated the diff for D33406: PR28129 expand vector oparation to an IR constant..

Update formatting, comments

Jun 15 2017, 1:34 PM
dtemirbulatov updated the diff for D33406: PR28129 expand vector oparation to an IR constant..

Update after http://lists.llvm.org/pipermail/llvm-dev/2017-June/114120.html. Added 0x1b(_CMP_FALSE_OS), 0x1f(_CMP_TRUE_US) handling.

Jun 15 2017, 9:00 AM