User Details
- User Since
- Sep 17 2015, 10:06 AM (393 w, 2 d)
Mon, Mar 27
Replaced zeroinitializer to poison in second operand for shufflevector.
Moved tests to <2 x > types.
Updated tests.
Changing tests.
Changed the second test case with suggestions from comment.
Wed, Mar 22
Rebased, Resolved comments.
Mon, Mar 20
Ping!
Thu, Mar 16
Removed double not in AArch64TargetLowering::preferScalarizeSplat() function.
Addressed remarks.
Wed, Mar 8
Feb 13 2023
Feb 12 2023
Adjust according to comments, fixed error with the same mask but different type size by forbid to delete the store.
Feb 10 2023
Rebasing.
Feb 9 2023
Gentle ping.
Feb 8 2023
Replaced to TypeSize::isKnownLE() usage for all constant true case. Added few tests.
Feb 7 2023
Restoring the previous revision.
Combined two ifs
Feb 6 2023
Fixed typo in test funtion name.
Addressed comments.
Feb 2 2023
I found an error in my implementation: we could not remove the store if the chained store is a fixed type and the store we consider to remove is a scalable type, since we don't know scalable type size in the runtime. fixed.
Resolved comments.
Feb 1 2023
Jan 31 2023
Use TypeSize::isKnownLE only if base pointers are equal.
Jan 30 2023
Addressed remakrs, using now TypeSize::isKnownLE.
Jan 25 2023
Dropped (STBitSize <= ChainBitSize) checks, it is not required as STBase.contains() ignores those to handle.
Jan 23 2023
Jan 19 2023
Fixed case where ST1 type size is bigger than in ST.
Missed to update sve-redundant-store.ll test after change, fixed.
Jan 11 2023
Renamed two functions in sve-splat-one-and-ptrue.ll
Addressed comments.
Jan 10 2023
Added combine for AArch64ISD::REINTERPRET_CAST nodes, addressed remarks.
Jan 9 2023
Addressed coments.
Jan 6 2023
Addressed comments.
Jan 5 2023
Changed proposed test in order to remove -O3 out of llc parameters.
Jan 3 2023
Removed unnecessary cast to CallInst.
Addressed comments.
Rebased, Addressed remarks.
Dec 20 2022
Dec 17 2022
Dec 16 2022
Fixed remarks.
Fixed remarks.
Dec 13 2022
Removed the Multiplier functionality. If a type is not representable on hardware then allow the legilizer to deduce the cost and in case a type is representable on hardware then assume basic SVE cost with 128-bit vector operation.
Missed two comments, addressed those as well.
Addressed suggestions.
Dec 12 2022
Added overflow check for the increment.
Dec 9 2022
Dec 8 2022
Added tests for signed/unsigned overflow.
Dec 7 2022
Dec 6 2022
Addressed remarks, avoided to check overflow while adding one to the range for equal or same conditions.
Addressed comments, added signed overflow handling while subtraction/addintion.
Dec 5 2022
Unified handling of WHILEop.
Dec 1 2022
Avoid to look at ConvertCostTableLookup table after switching to SVE registers, but call to AArch64TTIImpl::getCastInstrCost() recursively instead.
Nov 30 2022
Nov 25 2022
I found an error in the previous revision where we estimated cost for SVE based operation using NEON cost, added tests for target without NEON operations and SVE 128-bit size registers.
Nov 24 2022
Nov 23 2022
Fixed typo.
Nov 22 2022
Fixed error in converting from fixed to a scalable type by assuming to represent fixed vector type to SVE chunk 128-bit register.
Nov 18 2022
Nov 17 2022
Addressed remarks.
Corrected calculation for a number of elements in a vector for SVE type selection for cost approximation. No cost changes in test/Analysis/CostModel/AArch64/cast.ll with this revision against the previous.
Nov 16 2022
Add support for any range not just from 0.
Nov 15 2022
Rebased, addressed comments.
Nov 11 2022
Rebased, further improved cost estimation.
Nov 9 2022
Nov 7 2022
Fixed remarks.