• Avoid hoisting in following cases:
  • The cost of the const expr is 'free' for the target.
  • The expr can be folded into a legal addressing mode for the target.
  • The expr has only single use, and it's not inside a loop.
• Now there are no regressions.

LGTM. Thanks for the clarification.

Add extra test cases that have 'extract_subvector' in both operands.

Fix warning.

Enhance code readability.

Updating by main branch.

This patch indirectly causes the vectoriser to choose a lower VF due to the high cost of extending nxv16i8 -> nxv16i16, and that caused a regression.
Dave was investigating that issue and he has created a patch for fixing it.
So, right now this patch should work well.
I will rebase it and run checks to make sure everything is okay.

Hi @paulwalker-arm Are you okay with landing this patch ?

Fix format.

Check that extract node and mul node has one use.
That change triggered new changes in testing file of sve-fixed-length-int-rem.ll

Add check for fixed-length vectors.

Add a check to make sure that the mul has single use.

Remove line added by mistake.

Enhance code readability.

Remove line added by mistake.

Add additional checks to make sure of the expected pattern.

Fix Typo.

Improve code readability, Add comments.

@dmgreen Thanks for reviewing the patch. Do you have any further comments ?

Add test cases that use lshr.

Add comments explaining what LowerAvg() does.

Add test cases for logical shr.

Enhance code readability.

While checking isZeroExtending, only checking the signbit of known Zeros is enough.

Check if both operands of AVG are extended, not just single one.

Use ComputeNumSignBits instead of ComputeKnownBits for SIGN_EXTEND_INREG ops.

Use computeKnownBits for checking zeroExtedn/signExtend.

Remove sve-avgfloor testing file.
Add RUN line for sve to sve2-hadd
rename sve2-hadd to sve-hadd

Enhance code readability.

In case of CEIL, Put ADD operation for constant 1.

Change lshr to ashr for signed cases in the precursory patch.

Check if it's better to emit the original code or custom lower AVGFloor/Ceil

Optimize the generated code by checking if the extended nodes were previously truncated.

Optimize the generated code by checking if the extended node was previously truncated.

Add precursory patch.

Remove old code that is not used now.

Rerun testing files after updating the patch by main branch.

Update by main branch.

Remove neon-lshr.ll

Add AArch64 implementation for custom-lowering AVGFloor/AVGCeil

The affected testing files are related to custom-lowering ISD::VSELECT and ISD::BITREVERSE

Move combining trunc shift and extend shift to AArch64

Split out custom-lower select/fp_extend and related testing files into a new patch

Split out custom-lowering sign-extend-inreg and related testing files to another patch

This patch was split into smaller patches.

Recalculate the costs.

Update the calculated costs.
Use a cost of 1 for each SVE instruction.

In D142456#4079512, @sdesmalen wrote:

In D142456#4079499, @hassnaa-arm wrote:

In D142456#4079434, @dmgreen wrote:

where each operation has a cost of 2

Why does each instruction have a cost of 2?

Because that is mentioned here: https://developer.arm.com/documentation/pjdoc466751330-9685/latest/
in section 3.25 (SVE integer instructions)

Hi @hassnaa-arm, the cost-model shouldn't be hardcoding the number of cycles for one specific micro-architecture, because the cost-model should be accurate for other micro-architectures as well.
The cost requested here is the througput cost, not the latency. The throughput is closer to the number of instructions that is required for the operation.

In D142456#4079434, @dmgreen wrote:

where each operation has a cost of 2

Why does each instruction have a cost of 2?

Remove changes included by mistake.

Recalculate costs. In the code generation testing file, use real variable instead of undef to get accurate costs.

Add more accurte costs.

fix comment typo

Add testing file for the cost of zero/sign extend