[AMDGPU][True16] Support disassembling .h registers.

[kosarev]

The encoding is a bit different from what we use downstream, because I don't like the idea of assigning the is-high flag to the LSB. This makes encodings that we get from getEncodingValue() for the non-16bit registers effectively incorrect and thus requiring additional treatment. Placing the flag in one of the MSBs feels like it extends the existing encoding conventions more naturally.

[Joe_Nash]

The hi/lo bit was specifically chosen to be the LSB in the Register encoding so that subtracting registers creates a logical register range. This is used for True16 codegen support SIInsertWaitcnts, and likely elsewhere.
I do not think it is a good idea to introduce changes while upstreaming the feature because they cannot be tested against the codegen implementation downstream. There is not enough context for code inspection or test coverage upstream to support whether that bit layout change is a good idea.

[kosarev]

The hi/lo bit was specifically chosen to be the LSB in the Register encoding so that subtracting registers creates a logical register range. This is used for True16 codegen support SIInsertWaitcnts, and likely elsewhere.

Why do SIInsertWaitcnts intervals need to represent individual 16-bit registers?

[kosarev]

@Joe_Nash Joe, do you still request changes for this?

[Joe_Nash]

After seeing the changes to SIInsertWaitcnts and testing this downstream, I think it will work fine.
LGTM

[rampitec]

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

508–509

Why not to call TRI->getHWRegIndex(AMDGPU::getMCReg(Op.getReg(), *ST)) here and remove any dependency on the encoding?

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt

70

Does it just break fake16 and these can be removed completely at this point?

[kosarev]

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

508–509

For these initial patches I would like to keep changes minimal and avoid any immediate reworks and refinements. We can always do that later (it's in my TODO list).

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt

70

Well, it just exposes the current level of support for these instructions, and gives them some coverage. I believe we didn't break anything here.

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

if (!TRI->isInAllocatableClass(Op.getReg()))
     return {-1, -1};
 
   // A use via a PW operand does not need a waitcnt.
   // A partial write is not a WAW.
   assert(!Op.getSubReg() || !Op.isUndef());
 
   RegInterval Result;
 
-  unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST));
+  unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)) &
+                 AMDGPU::EncValues::REG_IDX_MASK;
 
   if (TRI->isVectorRegister(*MRI, Op.getReg())) {
     assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL);
     Result.first = Reg - Encoding.VGPR0;
     if (TRI->isAGPR(*MRI, Op.getReg()))
       Result.first += AGPR_OFFSET;
     assert(Result.first >= 0 && Result.first < SQ_MAX_PGM_VGPRS);
   } else if (TRI->isSGPRReg(*MRI, Op.getReg())) {
bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
   Limits.VscntMax = ST->hasVscnt() ? 63 : 0;
 
   unsigned NumVGPRsMax = ST->getAddressableNumVGPRs();
   unsigned NumSGPRsMax = ST->getAddressableNumSGPRs();
   assert(NumVGPRsMax <= SQ_MAX_PGM_VGPRS);
   assert(NumSGPRsMax <= SQ_MAX_PGM_SGPRS);
 
   RegisterEncoding Encoding = {};
-  Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0);
+  Encoding.VGPR0 =
+      TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
   Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1;
-  Encoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0);
+  Encoding.SGPR0 =
+      TRI->getEncodingValue(AMDGPU::SGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
   Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax - 1;
 
   TrackedWaitcntSet.clear();
   BlockInfos.clear();
   bool Modified = false;
 
   if (!MFI->isEntryFunction()) {
     // Wait for any outstanding memory operations that the input registers may

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
                        int last_reg, int stride, int size, string prefix> :
   RegisterTuples<Indices,
                  RegSeqDags<RC, last_reg, stride, size>.ret,
                  RegSeqNames<last_reg, stride, size, prefix>.ret>;
 
 //===----------------------------------------------------------------------===//
 //  Declarations that describe the SI registers
 //===----------------------------------------------------------------------===//
-class SIReg <string n, bits<16> regIdx = 0> :
-  Register<n> {
+class SIReg <string n, bits<8> regIdx = 0, bit isAGPROrVGPR = 0,
+             bit isHi = 0> : Register<n> {
   let Namespace = "AMDGPU";
-  let HWEncoding = regIdx;
+  let HWEncoding{7-0} = regIdx;
+  let HWEncoding{8} = isAGPROrVGPR;
+  let HWEncoding{9} = isHi;
 }
 
 // For register classes that use TSFlags.
 class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
   : RegisterClass <n, rTypes, Align, rList> {
   // For vector register classes.
   field bit HasVGPR = 0;
   field bit HasAGPR = 0;
 
   // For scalar register classes.
   field bit HasSGPR = 0;
 
   // Alignment of the first register in tuple (in 32-bit units).
   field int RegTupleAlignUnits = 1;
 
   // These need to be kept in sync with the enum SIRCFlags.
   let TSFlags{1-0} = RegTupleAlignUnits;
   let TSFlags{2} = HasVGPR;
   let TSFlags{3} = HasAGPR;
   let TSFlags{4} = HasSGPR;
 }
 
-multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
-                        bit HWEncodingHigh = 0> {
-  // There is no special encoding for 16 bit subregs, these are not real
-  // registers but rather operands for instructions preserving other 16 bits
-  // of the result or reading just 16 bits of a 32 bit VGPR.
-  // It is encoded as a corresponding 32 bit register.
-  // Non-VGPR register classes use it as we need to have matching subregisters
-  // to move instructions and data between ALUs.
-  def _LO16 : SIReg<n#".l", regIdx> {
-    let HWEncoding{8} = HWEncodingHigh;
-  }
-  def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> {
+multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1,
+                        bit isAGPROrVGPR = 0> {
+  def _LO16 : SIReg<n#".l", regIdx, isAGPROrVGPR>;
+  def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isAGPROrVGPR,
+                    /* isHi */ 1> {
     let isArtificial = ArtificialHigh;
-    let HWEncoding{8} = HWEncodingHigh;
   }
   def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
                                    !cast<Register>(NAME#"_HI16")]> {
     let Namespace = "AMDGPU";
     let SubRegIndices = [lo16, hi16];
     let CoveredBySubRegs = !not(ArtificialHigh);
-    let HWEncoding = regIdx;
-    let HWEncoding{8} = HWEncodingHigh;
+    let HWEncoding{7-0} = regIdx;
+    let HWEncoding{8} = isAGPROrVGPR;
   }
 }
 
 // Special Registers
 defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
 defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
 
 // Pseudo-registers: Used as placeholders during isel and immediately

 // HI 32 bit cannot be used, and LO 32 is used by instructions
 // with 32 bit sources.
 //
 // Note that the low 32 bits are essentially useless as they
 // don't contain the lower 32 bits of the address - they are in
 // the high 32 bits. The lower 32 bits are always zero (for base) or
 // -1 (for limit). Since we cannot access the high 32 bits, when we
 // need them, we need to do a 64 bit load and extract the bits manually.
-multiclass ApertureRegister<string name, bits<16> regIdx> {
+multiclass ApertureRegister<string name, bits<8> regIdx> {
   let isConstant = true in {
     // FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit
     //  register classes), but if we don't it seems to confuse the TableGen
     //  backend and we end up with a lot of weird register pressure sets and classes.
     defm _LO : SIRegLoHi16 <name, regIdx>;
     defm _HI : SIRegLoHi16 <"", regIdx>;
 
     def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO), !cast<Register>(NAME#_HI)]> {

 }
 
 foreach Index = 0...15 in {
   defm TTMP#Index#_vi       : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>;
   defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>;
   defm TTMP#Index           : SIRegLoHi16<"ttmp"#Index, 0>;
 }
 
-multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
+multiclass FLAT_SCR_LOHI_m <string n, bits<8> ci_e, bits<8> vi_e> {
   defm _ci : SIRegLoHi16<n, ci_e>;
   defm _vi : SIRegLoHi16<n, vi_e>;
   defm "" : SIRegLoHi16<n, 0>;
 }
 
 class FlatReg <Register lo, Register hi, bits<16> encoding> :
     RegisterWithSubRegs<"flat_scratch", [lo, hi]> {
   let Namespace = "AMDGPU";

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt

 # W32: v_add_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
 # W64: v_add_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_add_f16_e32 v5.l, v1.l, v2.l   ; encoding: [0x01,0x05,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x64]
 0x01,0x05,0x0a,0x64
 
+# GFX11-REAL16: v_add_f16_e32 v5.l, v1.h, v2.l   ; encoding: [0x81,0x05,0x0a,0x64]
+# GFX11-FAKE16: v_add_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x64]
+0x81,0x05,0x0a,0x64
+
 # GFX11-REAL16: v_add_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, v127, v2       ; encoding: [0x7f,0x05,0x0a,0x64]
 0x7f,0x05,0x0a,0x64
 
+# GFX11-REAL16: v_add_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x64]
+# GFX11-FAKE16: v_add_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x64]
+0xff,0x05,0x0a,0x64
+
 # GFX11-REAL16: v_add_f16_e32 v5.l, s1, v2.l     ; encoding: [0x01,0x04,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x64]
 0x01,0x04,0x0a,0x64
 
 # GFX11-REAL16: v_add_f16_e32 v5.l, s105, v2.l   ; encoding: [0x69,0x04,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x64]
 0x69,0x04,0x0a,0x64
 

 # GFX11-REAL16: v_add_f16_e32 v5.l, 0.5, v2.l    ; encoding: [0xf0,0x04,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x64]
 0xf0,0x04,0x0a,0x64
 
 # GFX11-REAL16: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64]
 # GFX11-FAKE16: v_add_f16_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x64]
 0xfd,0x04,0x0a,0x64
 
+# GFX11-REAL16: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x65
+0xfd,0x04,0x0b,0x65
+
 # GFX11-REAL16: v_add_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_add_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_add_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x06]
 0x01,0x05,0x0a,0x06
 
 # GFX11: v_add_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x06]
 0xff,0x05,0x0a,0x06
 
 # GFX11: v_add_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x06]
 0x01,0x04,0x0a,0x06

 
 # GFX11: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_max_f16_e32 v5.l, v1.l, v2.l   ; encoding: [0x01,0x05,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x72]
 0x01,0x05,0x0a,0x72
 
+# GFX11-REAL16: v_max_f16_e32 v5.l, v1.h, v2.l   ; encoding: [0x81,0x05,0x0a,0x72]
+# GFX11-FAKE16: v_max_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x72]
+0x81,0x05,0x0a,0x72
+
 # GFX11-REAL16: v_max_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, v127, v2       ; encoding: [0x7f,0x05,0x0a,0x72]
 0x7f,0x05,0x0a,0x72
 
+# GFX11-REAL16: v_max_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x72]
+# GFX11-FAKE16: v_max_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x72]
+0xff,0x05,0x0a,0x72
+
 # GFX11-REAL16: v_max_f16_e32 v5.l, s1, v2.l     ; encoding: [0x01,0x04,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x72]
 0x01,0x04,0x0a,0x72
 
 # GFX11-REAL16: v_max_f16_e32 v5.l, s105, v2.l   ; encoding: [0x69,0x04,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x72]
 0x69,0x04,0x0a,0x72
 

 # GFX11-REAL16: v_max_f16_e32 v5.l, 0.5, v2.l    ; encoding: [0xf0,0x04,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x72]
 0xf0,0x04,0x0a,0x72
 
 # GFX11-REAL16: v_max_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x72]
 # GFX11-FAKE16: v_max_f16_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x72]
 0xfd,0x04,0x0a,0x72
 
+# GFX11-REAL16: v_max_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x73]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x73
+0xfd,0x04,0x0b,0x73
+
 # GFX11-REAL16: v_max_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_max_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_max_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_max_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x20]
 0x01,0x05,0x0a,0x20
 
 # GFX11: v_max_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x20]
 0xff,0x05,0x0a,0x20
 
 # GFX11: v_max_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x20]
 0x01,0x04,0x0a,0x20

 
 # GFX11: v_max_u32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_min_f16_e32 v5.l, v1.l, v2.l   ; encoding: [0x01,0x05,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x74]
 0x01,0x05,0x0a,0x74
 
+# GFX11-REAL16: v_min_f16_e32 v5.l, v1.h, v2.l   ; encoding: [0x81,0x05,0x0a,0x74]
+# GFX11-FAKE16: v_min_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x74]
+0x81,0x05,0x0a,0x74
+
 # GFX11-REAL16: v_min_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, v127, v2       ; encoding: [0x7f,0x05,0x0a,0x74]
 0x7f,0x05,0x0a,0x74
 
+# GFX11-REAL16: v_min_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x74]
+# GFX11-FAKE16: v_min_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x74]
+0xff,0x05,0x0a,0x74
+
 # GFX11-REAL16: v_min_f16_e32 v5.l, s1, v2.l     ; encoding: [0x01,0x04,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x74]
 0x01,0x04,0x0a,0x74
 
 # GFX11-REAL16: v_min_f16_e32 v5.l, s105, v2.l   ; encoding: [0x69,0x04,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x74]
 0x69,0x04,0x0a,0x74
 

 # GFX11-REAL16: v_min_f16_e32 v5.l, 0.5, v2.l    ; encoding: [0xf0,0x04,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x74]
 0xf0,0x04,0x0a,0x74
 
 # GFX11-REAL16: v_min_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x74]
 # GFX11-FAKE16: v_min_f16_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x74]
 0xfd,0x04,0x0a,0x74
 
+# GFX11-REAL16: v_min_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x75]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x75
+0xfd,0x04,0x0b,0x75
+
 # GFX11-REAL16: v_min_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_min_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_min_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_min_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x1e]
 0x01,0x05,0x0a,0x1e
 
 # GFX11: v_min_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x1e]
 0xff,0x05,0x0a,0x1e
 
 # GFX11: v_min_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x1e]
 0x01,0x04,0x0a,0x1e

 
 # GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_mul_f16_e32 v5.l, v1.l, v2.l   ; encoding: [0x01,0x05,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x6a]
 0x01,0x05,0x0a,0x6a
 
+# GFX11-REAL16: v_mul_f16_e32 v5.l, v1.h, v2.l   ; encoding: [0x81,0x05,0x0a,0x6a]
+# GFX11-FAKE16: v_mul_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x6a
+0x81,0x05,0x0a,0x6a
+
 # GFX11-REAL16: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, v127, v2       ; encoding: [0x7f,0x05,0x0a,0x6a]
 0x7f,0x05,0x0a,0x6a
 
+# GFX11-REAL16: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a]
+# GFX11-FAKE16: v_mul_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x6a]
+0xff,0x05,0x0a,0x6a
+
 # GFX11-REAL16: v_mul_f16_e32 v5.l, s1, v2.l     ; encoding: [0x01,0x04,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x6a]
 0x01,0x04,0x0a,0x6a
 
 # GFX11-REAL16: v_mul_f16_e32 v5.l, s105, v2.l   ; encoding: [0x69,0x04,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x6a]
 0x69,0x04,0x0a,0x6a
 

 # GFX11-REAL16: v_mul_f16_e32 v5.l, 0.5, v2.l    ; encoding: [0xf0,0x04,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x6a]
 0xf0,0x04,0x0a,0x6a
 
 # GFX11-REAL16: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a]
 # GFX11-FAKE16: v_mul_f16_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x6a]
 0xfd,0x04,0x0a,0x6a
 
+# GFX11-REAL16: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x6b
+0xfd,0x04,0x0b,0x6b
+
 # GFX11-REAL16: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_mul_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x10]
 0x01,0x05,0x0a,0x10
 
 # GFX11: v_mul_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x10]
 0xff,0x05,0x0a,0x10
 
 # GFX11: v_mul_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x10]
 0x01,0x04,0x0a,0x10

 # W32: v_sub_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
 # W64: v_sub_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_sub_f16_e32 v5.l, v1.l, v2.l   ; encoding: [0x01,0x05,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x66]
 0x01,0x05,0x0a,0x66
 
+# GFX11-REAL16: v_sub_f16_e32 v5.l, v1.h, v2.l   ; encoding: [0x81,0x05,0x0a,0x66]
+# GFX11-FAKE16: v_sub_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x66]
+0x81,0x05,0x0a,0x66
+
 # GFX11-REAL16: v_sub_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, v127, v2       ; encoding: [0x7f,0x05,0x0a,0x66]
 0x7f,0x05,0x0a,0x66
 
+# GFX11-REAL16: v_sub_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x66]
+# GFX11-FAKE16: v_sub_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x66]
+0xff,0x05,0x0a,0x66
+
 # GFX11-REAL16: v_sub_f16_e32 v5.l, s1, v2.l     ; encoding: [0x01,0x04,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x66]
 0x01,0x04,0x0a,0x66
 
 # GFX11-REAL16: v_sub_f16_e32 v5.l, s105, v2.l   ; encoding: [0x69,0x04,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x66]
 0x69,0x04,0x0a,0x66
 

 # GFX11-REAL16: v_sub_f16_e32 v5.l, 0.5, v2.l    ; encoding: [0xf0,0x04,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x66]
 0xf0,0x04,0x0a,0x66
 
 # GFX11-REAL16: v_sub_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x66]
 # GFX11-FAKE16: v_sub_f16_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x66]
 0xfd,0x04,0x0a,0x66
 
+# GFX11-REAL16: v_sub_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x67]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x67
+0xfd,0x04,0x0b,0x67
+
 # GFX11-REAL16: v_sub_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_sub_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_sub_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x08]
 0x01,0x05,0x0a,0x08
 
 # GFX11: v_sub_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x08]
 0xff,0x05,0x0a,0x08
 
 # GFX11: v_sub_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x08]
 0x01,0x04,0x0a,0x08

 # W32: v_subrev_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
 # W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
 0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf
 
 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, v1, v2      ; encoding: [0x01,0x05,0x0a,0x68]
 0x01,0x05,0x0a,0x68
 
+# GFX11-REAL16: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
+# GFX11-FAKE16: v_subrev_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x68]
+0x81,0x05,0x0a,0x68
+
 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, v127, v2    ; encoding: [0x7f,0x05,0x0a,0x68]
 0x7f,0x05,0x0a,0x68
 
+# GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
+# GFX11-FAKE16: v_subrev_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x68]
+0xff,0x05,0x0a,0x68
+
 # GFX11-REAL16: v_subrev_f16_e32 v5.l, s1, v2.l  ; encoding: [0x01,0x04,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, s1, v2      ; encoding: [0x01,0x04,0x0a,0x68]
 0x01,0x04,0x0a,0x68
 
 # GFX11-REAL16: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, s105, v2    ; encoding: [0x69,0x04,0x0a,0x68]
 0x69,0x04,0x0a,0x68
 

 # GFX11-REAL16: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, 0.5, v2     ; encoding: [0xf0,0x04,0x0a,0x68]
 0xf0,0x04,0x0a,0x68
 
 # GFX11-REAL16: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68]
 # GFX11-FAKE16: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
 0xfd,0x04,0x0a,0x68
 
+# GFX11-REAL16: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x69
+0xfd,0x04,0x0b,0x69
+
 # GFX11-REAL16: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
 # GFX11-FAKE16: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
 0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00
 
+# GFX11-REAL16: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
+# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00
+0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_subrev_f32_e32 v5, v1, v2             ; encoding: [0x01,0x05,0x0a,0x0a]
 0x01,0x05,0x0a,0x0a
 
 # GFX11: v_subrev_f32_e32 v5, v255, v2           ; encoding: [0xff,0x05,0x0a,0x0a]
 0xff,0x05,0x0a,0x0a
 
 # GFX11: v_subrev_f32_e32 v5, s1, v2             ; encoding: [0x01,0x04,0x0a,0x0a]
 0x01,0x04,0x0a,0x0a