[llvm][RISCV][IR] Zext flag in IR for RISC-V

[karouzakisp]

Summary

Added zext flag in IR named was_sext for the target
RISC-V that converts back sext instructions from zext instructions
that were originated as a sext instruction. This conversion
happens in the backend of RISC-V in RISCVCodeGenPrepare.

[nikic]

Missing LangRef change.

was_sext is the wrong name for this flag, because it's not meaningful in terms of operational semantics of the IR. You'll want to call this something like nneg or nonneg, with the semantics that if the argument is negative, the return value is poison. This allows refining zext nneg %x to sext %x.

Generally I'm on board with adding such a flag.

[craig.topper]

Patch needs a real title

[craig.topper]

Please upload patches with full context using -U99999 per the directions here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

llvm/lib/AsmParser/LLParser.cpp

3747

if (Opc == Instruction::ZExt && EatIfPresent(lltok::kw_was_sext))
  WasSext = true;

6355

Unrelated change?

6382

Can this be moved into parseCast?

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

1472

This TODO needs to removed, or needs to say what needs to be done

4874

Is this reformatting existing code that you aren't changing?

4893

TODO has no description

4921

Join conditions with && to reduce nesting

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

105

This TODO is in the middle of a sentence

llvm/lib/IR/Instructions.cpp

3761

This is adding curly braces to code you didn't otherwise change. Please remove

[karouzakisp]

Added -U999999 in
git show
to make the reviewing possible via the web interface

[craig.topper]

Missing changes to Operator::hasPoisonGeneratingFlags and Instruction::copyIRFlags

[karouzakisp]

Changed flag's name from `was_sext to nneg`. Updated the LangRef and all the required changes such as Instruction.h Operator.h.

[craig.topper]

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

3228

Extra blank line

4925

Extra blank line

6420

Not sure what this is?

[nikic]

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

llvm/lib/Bitcode/flags.ll

31

This test should not be in the lib/ directory.

llvm/lib/IR/Instructions.cpp

3771

Spurious white space changes.

[karouzakisp]

Removed redudant whitespaces.

[karouzakisp]

Removed more redudant white spaces.

[karouzakisp]

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

llvm/lib/AsmParser/LLParser.cpp

6355

Yes, I reverted it back as it was.

6382

It can be moved but I wrote this, as all the other flags was written in a similar way. Also if we move it to parseCast we must refactor parseCast with one additional optional argument.

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

4874

Probably
git clang-format
reformatted it.
Should I reformat it back?

[craig.topper]

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

[karouzakisp]

In D156444#4632536, @craig.topper wrote:

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

[karouzakisp]

In D156444#4633397, @karouzakisp wrote:

In D156444#4632536, @craig.topper wrote:

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

In D156444#4633397, @karouzakisp wrote:

In D156444#4632536, @craig.topper wrote:

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

Ping.

[craig.topper]

I don't see tests for constantexpr.

llvm/include/llvm/IR/Instruction.h

372

"sext flag" -> "nneg flag"

382

"Determine whether the nneg flag is set."

llvm/lib/AsmParser/LLLexer.cpp

567

I think this list should try to be the same order as LLVMToken.h where you have this after inbounds

llvm/lib/AsmParser/LLParser.cpp

6383

We can just do return parseCast I think?

7185

Space after if

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

3216

Don't change the formatting of this line

3224

Extra space after &&

4892–4893

Don't change the formatting of this line

llvm/lib/IR/Instruction.cpp

385

Space after if

410

space after if

llvm/test/Bitcode/constantsTest.3.2.ll

124

The only change to this file seems to be adding a new line. I don't think we should touch this file in this patch.

[karouzakisp]

Updated clang-format and fixed minor errors.

[karouzakisp]

In D156444#4649111, @craig.topper wrote:

I don't see tests for constantexpr.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

ConstantExpr tests::

define i64 @zext_plain_ce() {
; CHECK: ret zext nneg i32 (i32 ptrtoint (ptr @addr to i32), i32 130) to i64

ret zext nneg i32 (i32 ptrtoint (ptr @addr to i32), i32 130) to i64

}

[nikic]

The semantics need to be a change to llvm/docs/LangRef.rst in this patch, not a comment.

As I said before, I don't think it makes sense to add nneg support to zext constant expressions, which are slated for removal.

llvm/include/llvm/IR/Operator.h

349

Missing comment text?

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

105

Not done?

[karouzakisp]

In D156444#4650274, @nikic wrote:

The semantics need to be a change to llvm/docs/LangRef.rst in this patch, not a comment.

As I said before, I don't think it makes sense to add nneg support to zext constant expressions, which are slated for removal.

Refactoring NonNeg Operator and removing all zext constant expressions leads to 3 test failing due to the inheritance graph:
NonNeg Operator is Operator and Operator is User and ConstantExpr is a Constant and Constant is User too.
So the User class must be refactored too to not support ConstantExpr in general.

[nikic]

In D156444#4652044, @karouzakisp wrote:

In D156444#4650274, @nikic wrote:

The semantics need to be a change to llvm/docs/LangRef.rst in this patch, not a comment.

As I said before, I don't think it makes sense to add nneg support to zext constant expressions, which are slated for removal.

Refactoring NonNeg Operator and removing all zext constant expressions leads to 3 test failing due to the inheritance graph:
NonNeg Operator is Operator and Operator is User and ConstantExpr is a Constant and Constant is User too.
So the User class must be refactored too to not support ConstantExpr in general.

Yes, Operator is for cases that support Instruction and ConstantExpr. You would change NonNegOperator -> NonNegInstruction/NonNegInst (if you need it at all, it would only have the classof check for zext and nothing else).

[karouzakisp]

In D156444#4652045, @nikic wrote:

In D156444#4652044, @karouzakisp wrote:

In D156444#4650274, @nikic wrote:

The semantics need to be a change to llvm/docs/LangRef.rst in this patch, not a comment.

As I said before, I don't think it makes sense to add nneg support to zext constant expressions, which are slated for removal.

Refactoring NonNeg Operator and removing all zext constant expressions leads to 3 test failing due to the inheritance graph:
NonNeg Operator is Operator and Operator is User and ConstantExpr is a Constant and Constant is User too.
So the User class must be refactored too to not support ConstantExpr in general.

Yes, Operator is for cases that support Instruction and ConstantExpr. You would change NonNegOperator -> NonNegInstruction/NonNegInst (if you need it at all, it would only have the classof check for zext and nothing else).

Yes I have done that and still the 3 tests fail, inheriting from User directly, instead of Operator.
and I get --> " decltype(auto) llvm::cast(From*) [with To = llvm::NonNegOperator; From = const llvm::Operator]: Assertion `isa<To>(Val) && "cast<Ty>() argument of incompatible type!"' failed. "

Basically I used operator to set/get the flag similarly to all the other flags but now those support ConstantExpr.
and I think that's the problem.

[craig.topper]

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

4874

This should be reformatted back the way it was.

[nikic]

I've put up https://github.com/llvm/llvm-project/pull/67982 based on this code, without the constant expression support and some cleanup.

llvm/include/llvm/AsmParser/LLToken.h

enum Kind {
   kw_contract,
   kw_reassoc,
   kw_afn,
   kw_fast,
   kw_nuw,
   kw_nsw,
   kw_exact,
   kw_inbounds,
+  kw_was_sext,
   kw_inrange,
   kw_addrspace,
   kw_section,
   kw_partition,
   kw_alias,
   kw_ifunc,
   kw_module,
   kw_asm,

llvm/include/llvm/Bitcode/LLVMBitCodes.h

enum FastMathMap {
   NoInfs          = (1 << 2),
   NoSignedZeros   = (1 << 3),
   AllowReciprocal = (1 << 4),
   AllowContract   = (1 << 5),
   ApproxFunc      = (1 << 6),
   AllowReassoc    = (1 << 7)
 };
 
+/// WSXTOperatorOptionalFlags - Flags for serializing
+/// WSXTOperator's SubclassOptionalData contents.
+enum WSXTOperatorOptionalFlags { WSXTO_WAS_SEXT = 0 };
+
 /// PossiblyExactOperatorOptionalFlags - Flags for serializing
 /// PossiblyExactOperator's SubclassOptionalData contents.
 enum PossiblyExactOperatorOptionalFlags { PEO_EXACT = 0 };
 
 /// Encoded AtomicOrdering values.
 enum AtomicOrderingCodes {
   ORDERING_NOTATOMIC = 0,
   ORDERING_UNORDERED = 1,

llvm/include/llvm/IR/Constants.h

public:
   static Constant *getXor(Constant *C1, Constant *C2);
   static Constant *getUMin(Constant *C1, Constant *C2);
   static Constant *getShl(Constant *C1, Constant *C2, bool HasNUW = false,
                           bool HasNSW = false);
   static Constant *getLShr(Constant *C1, Constant *C2, bool isExact = false);
   static Constant *getAShr(Constant *C1, Constant *C2, bool isExact = false);
   static Constant *getTrunc(Constant *C, Type *Ty, bool OnlyIfReduced = false);
   static Constant *getSExt(Constant *C, Type *Ty, bool OnlyIfReduced = false);
-  static Constant *getZExt(Constant *C, Type *Ty, bool OnlyIfReduced = false);
+  static Constant *getZExt(Constant *C, Type *Ty, bool OnlyIfReduced = false,
+                           bool WasSext = false);
   static Constant *getFPTrunc(Constant *C, Type *Ty,
                               bool OnlyIfReduced = false);
   static Constant *getFPExtend(Constant *C, Type *Ty,
                                bool OnlyIfReduced = false);
   static Constant *getUIToFP(Constant *C, Type *Ty, bool OnlyIfReduced = false);
   static Constant *getSIToFP(Constant *C, Type *Ty, bool OnlyIfReduced = false);
   static Constant *getFPToUI(Constant *C, Type *Ty, bool OnlyIfReduced = false);
   static Constant *getFPToSI(Constant *C, Type *Ty, bool OnlyIfReduced = false);

llvm/include/llvm/IR/Instruction.h

public:
   /// Set or clear the nsw flag on this instruction, which must be an operator
   /// which supports this flag. See LangRef.html for the meaning of this flag.
   void setHasNoSignedWrap(bool b = true);
 
   /// Set or clear the exact flag on this instruction, which must be an operator
   /// which supports this flag. See LangRef.html for the meaning of this flag.
   void setIsExact(bool b = true);
 
+  /// Set or clear the sext flag on this instruction, which must be an operator
+  /// which supports this flag. In our case WSXTOperator defined in Operator.h.
+  void setWasSext(bool b = true);
+
   /// Determine whether the no unsigned wrap flag is set.
   bool hasNoUnsignedWrap() const LLVM_READONLY;
 
   /// Determine whether the no signed wrap flag is set.
   bool hasNoSignedWrap() const LLVM_READONLY;
 
+  /// Determine whether the sext flag is set.
+  bool wasSext() const LLVM_READONLY;
+
   /// Return true if this operator has flags which may cause this instruction
   /// to evaluate to poison despite having non-poison inputs.
   bool hasPoisonGeneratingFlags() const LLVM_READONLY;
 
   /// Drops flags that may cause this instruction to evaluate to poison despite
   /// having non-poison inputs.
   void dropPoisonGeneratingFlags();
 

llvm/include/llvm/IR/Operator.h

case Instruction::Call: {
       return Ty->isFPOrFPVectorTy();
     }
     default:
       return false;
     }
   }
 };
 
+/// An utility class for the zext instructions that were
+/// created by a conversion from sext instructions.
+class WSXTOperator : public Operator {
+public:
+  enum { WasSext = (1 << 0) };
+
+private:
+  friend class Instruction;
+  friend class ConstantExpr;
+
+  void setWasSext(bool B) {
+    SubclassOptionalData = (SubclassOptionalData & ~WasSext) | (B * WasSext);
+  }
+
+public:
+  ///
+  bool wasSext() const { return (SubclassOptionalData & WasSext) != 0; }
+
+  static bool classof(const Instruction *I) {
+    return I->getOpcode() == Instruction::ZExt;
+  }
+  static bool classof(const ConstantExpr *CE) {
+    return CE->getOpcode() == Instruction::ZExt;
+  }
+  static bool classof(const Value *V) {
+    return (isa<Instruction>(V) && classof(cast<Instruction>(V))) ||
+           (isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
+  }
+};
+
 /// A helper template for defining operators for individual opcodes.
 template<typename SuperClass, unsigned Opc>
 class ConcreteOperator : public SuperClass {
 public:
   static bool classof(const Instruction *I) {
     return I->getOpcode() == Opc;
   }
   static bool classof(const ConstantExpr *CE) {

 };
 class AShrOperator
   : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
 };
 class LShrOperator
   : public ConcreteOperator<PossiblyExactOperator, Instruction::LShr> {
 };
 
-class ZExtOperator : public ConcreteOperator<Operator, Instruction::ZExt> {};
+class ZExtOperator : public ConcreteOperator<WSXTOperator, Instruction::ZExt> {
+};
 
 class GEPOperator
   : public ConcreteOperator<Operator, Instruction::GetElementPtr> {
   friend class GetElementPtrInst;
   friend class ConstantExpr;
 
   enum {
     IsInBounds = (1 << 0),

llvm/lib/AsmParser/LLLexer.cpp

#define KEYWORD(STR)                                                           \
   KEYWORD(nsz);
   KEYWORD(arcp);
   KEYWORD(contract);
   KEYWORD(reassoc);
   KEYWORD(afn);
   KEYWORD(fast);
   KEYWORD(nuw);
   KEYWORD(nsw);
+  KEYWORD(was_sext);
   KEYWORD(exact);
   KEYWORD(inbounds);
   KEYWORD(inrange);
   KEYWORD(addrspace);
   KEYWORD(section);
   KEYWORD(partition);
   KEYWORD(alias);
   KEYWORD(ifunc);

llvm/lib/AsmParser/LLParser.cpp

bool LLParser::parseValID(ValID &ID, PerFunctionState *PFS, Type *ExpectedTy) {
   case lltok::kw_addrspacecast:
   case lltok::kw_uitofp:
   case lltok::kw_sitofp:
   case lltok::kw_fptoui:
   case lltok::kw_fptosi:
   case lltok::kw_inttoptr:
   case lltok::kw_ptrtoint: {
     unsigned Opc = Lex.getUIntVal();
+    bool WasSext = false;
     Type *DestTy = nullptr;
     Constant *SrcVal;
     Lex.Lex();
+    if (Opc == Instruction::ZExt) {
+      if (EatIfPresent(lltok::kw_was_sext))
+        WasSext = true;
+    }
     if (parseToken(lltok::lparen, "expected '(' after constantexpr cast") ||
         parseGlobalTypeAndValue(SrcVal) ||
         parseToken(lltok::kw_to, "expected 'to' in constantexpr cast") ||
         parseType(DestTy) ||
         parseToken(lltok::rparen, "expected ')' at end of constantexpr cast"))
       return true;
     if (!CastInst::castIsValid((Instruction::CastOps)Opc, SrcVal, DestTy))
       return error(ID.Loc, "invalid cast opcode for cast from '" +
                                getTypeString(SrcVal->getType()) + "' to '" +
                                getTypeString(DestTy) + "'");
-    ID.ConstantVal = ConstantExpr::getCast((Instruction::CastOps)Opc,
-                                                 SrcVal, DestTy);
+
     ID.Kind = ValID::t_Constant;
+    if (WasSext) {
+      ID.ConstantVal =
+          ConstantExpr::getZExt(SrcVal, DestTy,
+                                /* OnlyIfReduced */ false, /* WasSext */ true);
+
+    } else {
+      ID.ConstantVal =
+          ConstantExpr::getCast((Instruction::CastOps)Opc, SrcVal, DestTy);
+    }
     return false;
   }
   case lltok::kw_extractvalue:
     return error(ID.Loc, "extractvalue constexprs are no longer supported");
   case lltok::kw_insertvalue:
     return error(ID.Loc, "insertvalue constexprs are no longer supported");
   case lltok::kw_udiv:
     return error(ID.Loc, "udiv constexprs are no longer supported");
int LLParser::parseInstruction(Instruction *&Inst, BasicBlock *BB,
   case lltok::kw_sdiv:
   case lltok::kw_udiv:
   case lltok::kw_lshr:
   case lltok::kw_ashr: {
     bool Exact = EatIfPresent(lltok::kw_exact);
 
     if (parseArithmetic(Inst, PFS, KeywordVal, /*IsFP*/ false))
       return true;
+
     if (Exact) cast<BinaryOperator>(Inst)->setIsExact(true);
     return false;
   }
 
   case lltok::kw_urem:
   case lltok::kw_srem:
     return parseArithmetic(Inst, PFS, KeywordVal,
                            /*IsFP*/ false);
case lltok::kw_fcmp: {
     if (Res != 0)
       return Res;
     if (FMF.any())
       Inst->setFastMathFlags(FMF);
     return 0;
   }
 
   // Casts.
+  case lltok::kw_zext: {
+    bool WasSext = EatIfPresent(lltok::kw_was_sext);
+    bool Res = parseCast(Inst, PFS, KeywordVal);
+    if (Res != 0) {
+      return Res;
+    }
+    if (WasSext == true)
+      Inst->setWasSext(true);
+    return 0;
+  }
   case lltok::kw_trunc:
-  case lltok::kw_zext:
   case lltok::kw_sext:
   case lltok::kw_fptrunc:
   case lltok::kw_fpext:
   case lltok::kw_bitcast:
   case lltok::kw_addrspacecast:
   case lltok::kw_uitofp:
   case lltok::kw_sitofp:
   case lltok::kw_fptoui:
bool LLParser::parseCast(Instruction *&Inst, PerFunctionState &PFS,
 
   if (!CastInst::castIsValid((Instruction::CastOps)Opc, Op, DestTy)) {
     CastInst::castIsValid((Instruction::CastOps)Opc, Op, DestTy);
     return error(Loc, "invalid cast opcode for cast from '" +
                           getTypeString(Op->getType()) + "' to '" +
                           getTypeString(DestTy) + "'");
   }
   Inst = CastInst::Create((Instruction::CastOps)Opc, Op, DestTy);
   return false;
 }
 
 /// parseSelect
 ///   ::= 'select' TypeAndValue ',' TypeAndValue ',' TypeAndValue
 bool LLParser::parseSelect(Instruction *&Inst, PerFunctionState &PFS) {
   LocTy Loc;
   Value *Op0, *Op1, *Op2;
   if (parseTypeAndValue(Op0, Loc, PFS) ||

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

while (!Worklist.empty()) {
     SmallVector<Constant *> ConstOps;
     for (Value *Op : Ops)
       if (auto *C = dyn_cast<Constant>(Op))
         ConstOps.push_back(C);
 
     // Materialize as constant expression if possible.
     if (isConstExprSupported(BC->Opcode) && ConstOps.size() == Ops.size()) {
       Constant *C;
-      if (Instruction::isCast(BC->Opcode)) {
+      if (Instruction::isCast(BC->Opcode)) { // TODO
         C = UpgradeBitCastExpr(BC->Opcode, ConstOps[0], BC->getType());
         if (!C)
           C = ConstantExpr::getCast(BC->Opcode, ConstOps[0], BC->getType());
       } else if (Instruction::isBinaryOp(BC->Opcode)) {
         C = ConstantExpr::get(BC->Opcode, ConstOps[0], ConstOps[1], BC->Flags);
       } else {
         switch (BC->Opcode) {
         case BitcodeConstant::NoCFIOpcode: {
if (!InsertBB)
                          "constant expression of type ") +
                    BC->getOpcodeName());
 
     // Materialize as instructions if necessary.
     Instruction *I;
     if (Instruction::isCast(BC->Opcode)) {
       I = CastInst::Create((Instruction::CastOps)BC->Opcode, Ops[0],
                            BC->getType(), "constexpr", InsertBB);
+      if (isa<WSXTOperator>(I) && (BC->Flags & WSXTOperator::WasSext))
+        I->setWasSext(true);
+
     } else if (Instruction::isUnaryOp(BC->Opcode)) {
       I = UnaryOperator::Create((Instruction::UnaryOps)BC->Opcode, Ops[0],
                                 "constexpr", InsertBB);
     } else if (Instruction::isBinaryOp(BC->Opcode)) {
       I = BinaryOperator::Create((Instruction::BinaryOps)BC->Opcode, Ops[0],
                                  Ops[1], "constexpr", InsertBB);
       if (isa<OverflowingBinaryOperator>(I)) {
         if (BC->Flags & OverflowingBinaryOperator::NoSignedWrap)
case bitc::CST_CODE_CE_BINOP: {  // CE_BINOP: [opcode, opval, opval]
               Flags |= SDivOperator::IsExact;
           }
         }
         V = BitcodeConstant::create(Alloc, CurTy, {(uint8_t)Opc, Flags},
                                     {(unsigned)Record[1], (unsigned)Record[2]});
       }
       break;
     }
-    case bitc::CST_CODE_CE_CAST: {  // CE_CAST: [opcode, opty, opval]
+    case bitc::CST_CODE_CE_CAST: { // CE_CAST: [opcode, opty, opval] #TODO
       if (Record.size() < 3)
         return error("Invalid cast constexpr record");
       int Opc = getDecodedCastOpcode(Record[0]);
       if (Opc < 0) {
         V = UndefValue::get(CurTy);  // Unknown cast.
       } else {
+        uint8_t Flags = 0;
+        if (Record.size() >= 4) {
+          if (Record[3] & (1 << bitc::WSXTO_WAS_SEXT)) {
+            Flags |= WSXTOperator::WasSext;
+          }
+        }
         unsigned OpTyID = Record[1];
         Type *OpTy = getTypeByID(OpTyID);
         if (!OpTy)
           return error("Invalid cast constexpr record");
-        V = BitcodeConstant::create(Alloc, CurTy, Opc, (unsigned)Record[2]);
+        V = BitcodeConstant::create(Alloc, CurTy, {(uint8_t)Opc, Flags},
+                                    (unsigned)Record[2]);
       }
       break;
     }
     case bitc::CST_CODE_CE_INBOUNDS_GEP: // [ty, n x operands]
     case bitc::CST_CODE_CE_GEP: // [ty, n x operands]
     case bitc::CST_CODE_CE_GEP_WITH_INRANGE_INDEX: { // [ty, flags, n x
                                                      // operands]
       if (Record.size() < 2)
case bitc::FUNC_CODE_INST_BINOP: {    // BINOP: [opval, ty, opval, opcode]
 
       int Opc = getDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
       if (Opc == -1)
         return error("Invalid record");
       I = BinaryOperator::Create((Instruction::BinaryOps)Opc, LHS, RHS);
       ResTypeID = TypeID;
       InstructionList.push_back(I);
       if (OpNum < Record.size()) {
-        if (Opc == Instruction::Add ||
-            Opc == Instruction::Sub ||
-            Opc == Instruction::Mul ||
-            Opc == Instruction::Shl) {
-          if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
-            cast<BinaryOperator>(I)->setHasNoSignedWrap(true);
+        if (Opc == Instruction::Add || Opc == Instruction::Sub ||
+            Opc == Instruction::Mul || Opc == Instruction::Shl) {
           if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
             cast<BinaryOperator>(I)->setHasNoUnsignedWrap(true);
-        } else if (Opc == Instruction::SDiv ||
-                   Opc == Instruction::UDiv ||
-                   Opc == Instruction::LShr ||
-                   Opc == Instruction::AShr) {
+          if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
+            cast<BinaryOperator>(I)->setHasNoSignedWrap(true);
+        } else if (Opc == Instruction::SDiv || Opc == Instruction::UDiv ||
+                   Opc == Instruction::LShr || Opc == Instruction::AShr) {
           if (Record[OpNum] & (1 << bitc::PEO_EXACT))
             cast<BinaryOperator>(I)->setIsExact(true);
         } else if (isa<FPMathOperator>(I)) {
           FastMathFlags FMF = getDecodedFastMathFlags(Record[OpNum]);
           if (FMF.any())
             I->setFastMathFlags(FMF);
         }
-
       }
       break;
     }
-    case bitc::FUNC_CODE_INST_CAST: {    // CAST: [opval, opty, destty, castopc]
+    case bitc::FUNC_CODE_INST_CAST: { // CAST: [opval, opty, destty, castopc]
+                                      // #TODO
       unsigned OpNum = 0;
       Value *Op;
       unsigned OpTypeID;
       if (getValueTypePair(Record, OpNum, NextValueNo, Op, OpTypeID, CurBB) ||
-          OpNum+2 != Record.size())
+          OpNum + 1 > Record.size())
         return error("Invalid record");
 
-      ResTypeID = Record[OpNum];
+      ResTypeID = Record[OpNum++];
       Type *ResTy = getTypeByID(ResTypeID);
-      int Opc = getDecodedCastOpcode(Record[OpNum + 1]);
+      int Opc = getDecodedCastOpcode(Record[OpNum++]);
+
       if (Opc == -1 || !ResTy)
         return error("Invalid record");
       Instruction *Temp = nullptr;
       if ((I = UpgradeBitCastInst(Opc, Op, ResTy, Temp))) {
         if (Temp) {
           InstructionList.push_back(Temp);
           assert(CurBB && "No current BB?");
           Temp->insertInto(CurBB, CurBB->end());
         }
       } else {
         auto CastOp = (Instruction::CastOps)Opc;
+
         if (!CastInst::castIsValid(CastOp, Op, ResTy))
           return error("Invalid cast");
         I = CastInst::Create(CastOp, Op, ResTy);
       }
+      if (OpNum < Record.size()) {
+        if (isa<WSXTOperator>(I)) {
+          if ((Record[OpNum] & (1 << bitc::WSXTO_WAS_SEXT))) {
+            cast<CastInst>(I)->setWasSext(true);
+          }
+        }
+      }
+
       InstructionList.push_back(I);
       break;
     }
     case bitc::FUNC_CODE_INST_INBOUNDS_GEP_OLD:
     case bitc::FUNC_CODE_INST_GEP_OLD:
     case bitc::FUNC_CODE_INST_GEP: { // GEP: type, [n x operands]
       unsigned OpNum = 0;
 
case bitc::FUNC_CODE_INST_CALL: {
         TCK = CallInst::TCK_MustTail;
       if (CCInfo & (1 << bitc::CALL_NOTAIL))
         TCK = CallInst::TCK_NoTail;
       cast<CallInst>(I)->setTailCallKind(TCK);
       cast<CallInst>(I)->setAttributes(PAL);
       if (Error Err = propagateAttributeTypes(cast<CallBase>(I), ArgTyIDs)) {
         I->deleteValue();
         return Err;
-      }
+      } // CHECK FOR ZEXT FLAG possible on call?
       if (FMF.any()) {
         if (!isa<FPMathOperator>(I))
           return error("Fast-math-flags specified for call without "
                        "floating-point scalar or vector return type");
         I->setFastMathFlags(FMF);
       }
       break;
     }

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

 
 namespace llvm {
 extern FunctionSummary::ForceSummaryHotnessType ForceSummaryEdgesCold;
 }
 
 namespace {
 
 /// These are manifest constants used by the bitcode writer. They do not need to
-/// be kept in sync with the reader, but need to be consistent within this file.
+/// // TODO add zext be kept in sync with the reader, but need to be consistent
+/// within this file.
 enum {
   // VALUE_SYMTAB_BLOCK abbrev id's.
   VST_ENTRY_8_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
   VST_ENTRY_7_ABBREV,
   VST_ENTRY_6_ABBREV,
   VST_BBENTRY_6_ABBREV,
 
   // CONSTANTS_BLOCK abbrev id's.
   CONSTANTS_SETTYPE_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
   CONSTANTS_INTEGER_ABBREV,
   CONSTANTS_CE_CAST_Abbrev,
+  CONSTANTS_CE_CAST_FLAGS_ABBREV,
   CONSTANTS_NULL_Abbrev,
 
   // FUNCTION_BLOCK abbrev id's.
   FUNCTION_INST_LOAD_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
   FUNCTION_INST_UNOP_ABBREV,
   FUNCTION_INST_UNOP_FLAGS_ABBREV,
   FUNCTION_INST_BINOP_ABBREV,
   FUNCTION_INST_BINOP_FLAGS_ABBREV,
   FUNCTION_INST_CAST_ABBREV,
+  FUNCTION_INST_CAST_FLAGS_ABBREV,
   FUNCTION_INST_RET_VOID_ABBREV,
   FUNCTION_INST_RET_VAL_ABBREV,
   FUNCTION_INST_UNREACHABLE_ABBREV,
   FUNCTION_INST_GEP_ABBREV,
 };
 
 /// Abstract class to manage the bitcode writing, subclassed for each bitcode
 /// file type.
if (const auto *OBO = dyn_cast<OverflowingBinaryOperator>(V)) {
     if (FPMO->hasNoSignedZeros())
       Flags |= bitc::NoSignedZeros;
     if (FPMO->hasAllowReciprocal())
       Flags |= bitc::AllowReciprocal;
     if (FPMO->hasAllowContract())
       Flags |= bitc::AllowContract;
     if (FPMO->hasApproxFunc())
       Flags |= bitc::ApproxFunc;
+  } else if (const auto *WSXTO = dyn_cast<WSXTOperator>(V)) {
+    if (WSXTO->wasSext()) {
+      Flags |= 1 << bitc::WSXTO_WAS_SEXT;
+    }
   }
-
   return Flags;
 }
 
 void ModuleBitcodeWriter::writeValueAsMetadata(
     const ValueAsMetadata *MD, SmallVectorImpl<uint64_t> &Record) {
   // Mimic an MDNode with a value as one operand.
   Value *V = MD->getValue();
   Record.push_back(VE.getTypeID(V->getType()));
if (C->isNullValue()) {
       switch (CE->getOpcode()) {
       default:
         if (Instruction::isCast(CE->getOpcode())) {
           Code = bitc::CST_CODE_CE_CAST;
           Record.push_back(getEncodedCastOpcode(CE->getOpcode()));
           Record.push_back(VE.getTypeID(C->getOperand(0)->getType()));
           Record.push_back(VE.getValueID(C->getOperand(0)));
           AbbrevToUse = CONSTANTS_CE_CAST_Abbrev;
+          uint64_t Flags = getOptimizationFlags(CE);
+          if (Flags != 0) {
+            AbbrevToUse = CONSTANTS_CE_CAST_FLAGS_ABBREV;
+            Record.push_back(Flags);
+          }
         } else {
           assert(CE->getNumOperands() == 2 && "Unknown constant expr!");
           Code = bitc::CST_CODE_CE_BINOP;
           Record.push_back(getEncodedBinaryOpcode(CE->getOpcode()));
           Record.push_back(VE.getValueID(C->getOperand(0)));
           Record.push_back(VE.getValueID(C->getOperand(1)));
           uint64_t Flags = getOptimizationFlags(CE);
           if (Flags != 0)
void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
   switch (I.getOpcode()) {
   default:
     if (Instruction::isCast(I.getOpcode())) {
       Code = bitc::FUNC_CODE_INST_CAST;
       if (!pushValueAndType(I.getOperand(0), InstID, Vals))
         AbbrevToUse = FUNCTION_INST_CAST_ABBREV;
       Vals.push_back(VE.getTypeID(I.getType()));
       Vals.push_back(getEncodedCastOpcode(I.getOpcode()));
+      uint64_t Flags = getOptimizationFlags(&I);
+      if (Flags != 0) {
+        if (AbbrevToUse == FUNCTION_INST_CAST_ABBREV)
+          AbbrevToUse = FUNCTION_INST_CAST_FLAGS_ABBREV;
+        Vals.push_back(Flags);
+      }
     } else {
       assert(isa<BinaryOperator>(I) && "Unknown instruction!");
       Code = bitc::FUNC_CODE_INST_BINOP;
       if (!pushValueAndType(I.getOperand(0), InstID, Vals))
         AbbrevToUse = FUNCTION_INST_BINOP_ABBREV;
       pushValue(I.getOperand(1), InstID, Vals);
       Vals.push_back(getEncodedBinaryOpcode(I.getOpcode()));
       uint64_t Flags = getOptimizationFlags(&I);
void ModuleBitcodeWriter::writeBlockInfo() {
   { // INTEGER abbrev for CONSTANTS_BLOCK.
     auto Abbv = std::make_shared<BitCodeAbbrev>();
     Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_INTEGER));
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));
     if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) !=
         CONSTANTS_INTEGER_ABBREV)
       llvm_unreachable("Unexpected abbrev ordering!");
   }
+  { // CE_CAST abbrev for CONSTANTS_BLOCK.
+    auto Abbv = std::make_shared<BitCodeAbbrev>();
+    Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_CE_CAST));
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // cast opc
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,      // typeid
+                              VE.computeBitsRequiredForTypeIndicies()));
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // value id
+    if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) !=
+        CONSTANTS_CE_CAST_Abbrev)
+      llvm_unreachable("Unexpected abbrev ordering!");
+  }
 
   { // CE_CAST abbrev for CONSTANTS_BLOCK.
     auto Abbv = std::make_shared<BitCodeAbbrev>();
     Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_CE_CAST));
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4));  // cast opc
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,       // typeid
                               VE.computeBitsRequiredForTypeIndicies()));
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));    // value id
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8));  // flags
 
     if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) !=
-        CONSTANTS_CE_CAST_Abbrev)
+        CONSTANTS_CE_CAST_FLAGS_ABBREV)
       llvm_unreachable("Unexpected abbrev ordering!");
   }
   { // NULL abbrev for CONSTANTS_BLOCK.
     auto Abbv = std::make_shared<BitCodeAbbrev>();
     Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_NULL));
     if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID, Abbv) !=
         CONSTANTS_NULL_Abbrev)
       llvm_unreachable("Unexpected abbrev ordering!");
// FIXME: This should only use space for first class types!
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // LHS
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // RHS
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8)); // flags
     if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
         FUNCTION_INST_BINOP_FLAGS_ABBREV)
       llvm_unreachable("Unexpected abbrev ordering!");
   }
-  { // INST_CAST abbrev for FUNCTION_BLOCK.
+  { // INST_CAST abbrev for FUNCTION_BLOCK. TODO possible zext flag
     auto Abbv = std::make_shared<BitCodeAbbrev>();
     Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_CAST));
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));    // OpVal
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,       // dest ty
                               VE.computeBitsRequiredForTypeIndicies()));
     Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4));  // opc
     if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
         FUNCTION_INST_CAST_ABBREV)
       llvm_unreachable("Unexpected abbrev ordering!");
   }
+  { // INST_CAST FLAGS abbrev for FUNCTION_BLOCK. TODO possible zext flag
+    auto Abbv = std::make_shared<BitCodeAbbrev>();
+    Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_CAST));
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // OpVal
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,    // dest ty
+                              VE.computeBitsRequiredForTypeIndicies()));
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
+    Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8)); // flags
+    if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
+        FUNCTION_INST_CAST_FLAGS_ABBREV)
+      llvm_unreachable("Unexpected abbrev ordering!");
+  }
 
   { // INST_RET abbrev for FUNCTION_BLOCK.
     auto Abbv = std::make_shared<BitCodeAbbrev>();
     Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET));
     if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
         FUNCTION_INST_RET_VOID_ABBREV)
       llvm_unreachable("Unexpected abbrev ordering!");
   }

llvm/lib/Bitcode/flags.ll

+; RUN: llvm-as < %s | llvm-dis > %t0
+; RUN: opt -S < %s > %t1
+; RUN: diff %t0 %t1
+; RUN: verify-uselistorder < %s
+; PR6140
+
+; Make sure the flags are serialized/deserialized properly for both
+; forward and backward references.
+
+define void @foo() nounwind {
+entry:
+  br label %first
+
+second:                                           ; preds = %first
+  %u = add nuw i32 %a, 0                          ; <i32> [#uses=0]
+  %s = add nsw i32 %a, 0                          ; <i32> [#uses=0]
+  %us = add nuw nsw i32 %a, 0                     ; <i32> [#uses=0]
+  %z = add i32 %a, 0                              ; <i32> [#uses=0]
+  %hh = zext i32 %a to i64                        ; <i64> [#uses=0]
+  unreachable
+
+first:                                            ; preds = %entry
+  %a = bitcast i32 0 to i32                       ; <i32> [#uses=8]
+  %uu = add nuw i32 %a, 0                         ; <i32> [#uses=0]
+  %ss = add nsw i32 %a, 0                         ; <i32> [#uses=0]
+  %uuss = add nuw nsw i32 %a, 0                   ; <i32> [#uses=0]
+  %zz = add i32 %a, 0                             ; <i32> [#uses=0]
+  %kk = zext was_sext i32 %a to i64               ; <i64> [#uses=0]
+  br label %second
+}

llvm/lib/IR/AsmWriter.cpp

if (OBO->hasNoSignedWrap())
       Out << " nsw";
   } else if (const PossiblyExactOperator *Div =
                dyn_cast<PossiblyExactOperator>(U)) {
     if (Div->isExact())
       Out << " exact";
   } else if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
     if (GEP->isInBounds())
       Out << " inbounds";
+  } else if (const WSXTOperator *WSXTO = dyn_cast<WSXTOperator>(U)) {
+    if (WSXTO->wasSext())
+      Out << " was_sext";
   }
 }
 
 static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
                                   AsmWriterContext &WriterCtx) {
   if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
     if (CI->getType()->isIntegerTy(1)) {
       Out << (CI->getZExtValue() ? "true" : "false");

llvm/lib/IR/Constants.cpp

 }
 
 //---- ConstantExpr::get() implementations.
 //
 
 /// This is a utility function to handle folding of casts and lookup of the
 /// cast in the ExprConstants map. It is used by the various get* methods below.
 static Constant *getFoldedCast(Instruction::CastOps opc, Constant *C, Type *Ty,
-                               bool OnlyIfReduced = false) {
+                               bool OnlyIfReduced = false,
+                               bool WasSext = false) {
   assert(Ty->isFirstClassType() && "Cannot cast to an aggregate type!");
   // Fold a few common cases
   if (Constant *FC = ConstantFoldCastInstruction(opc, C, Ty))
     return FC;
 
   if (OnlyIfReduced)
     return nullptr;
 
   LLVMContextImpl *pImpl = Ty->getContext().pImpl;
 
   // Look up the constant in the table first to ensure uniqueness.
-  ConstantExprKeyType Key(opc, C);
+  ConstantExprKeyType Key(opc, C, 0, WasSext);
 
   return pImpl->ExprConstants.getOrCreate(Ty, Key);
 }
 
 Constant *ConstantExpr::getCast(unsigned oc, Constant *C, Type *Ty,
                                 bool OnlyIfReduced) {
   Instruction::CastOps opc = Instruction::CastOps(oc);
   assert(Instruction::isCast(opc) && "opcode out of range");
#endif
   assert(C->getType()->isIntOrIntVectorTy() && "SExt operand must be integral");
   assert(Ty->isIntOrIntVectorTy() && "SExt produces only integer");
   assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&&
          "SrcTy must be smaller than DestTy for SExt!");
 
   return getFoldedCast(Instruction::SExt, C, Ty, OnlyIfReduced);
 }
 
-Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced) {
+Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced,
+                                bool WasSext) {
 #ifndef NDEBUG
   bool fromVec = isa<VectorType>(C->getType());
   bool toVec = isa<VectorType>(Ty);
 #endif
   assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");
   assert(C->getType()->isIntOrIntVectorTy() && "ZEXt operand must be integral");
   assert(Ty->isIntOrIntVectorTy() && "ZExt produces only integer");
   assert(C->getType()->getScalarSizeInBits() < Ty->getScalarSizeInBits()&&
          "SrcTy must be smaller than DestTy for ZExt!");
 
-  return getFoldedCast(Instruction::ZExt, C, Ty, OnlyIfReduced);
+  return getFoldedCast(Instruction::ZExt, C, Ty, OnlyIfReduced, WasSext);
 }
 
 Constant *ConstantExpr::getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) {
 #ifndef NDEBUG
   bool fromVec = isa<VectorType>(C->getType());
   bool toVec = isa<VectorType>(Ty);
 #endif
   assert((fromVec == toVec) && "Cannot convert from scalar to/from vector");

llvm/lib/IR/Instruction.cpp

 void Instruction::setHasNoSignedWrap(bool b) {
   cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(b);
 }
 
 void Instruction::setIsExact(bool b) {
   cast<PossiblyExactOperator>(this)->setIsExact(b);
 }
 
+void Instruction::setWasSext(bool b) {
+  cast<WSXTOperator>(this)->setWasSext(b);
+}
+
 bool Instruction::hasNoUnsignedWrap() const {
   return cast<OverflowingBinaryOperator>(this)->hasNoUnsignedWrap();
 }
 
 bool Instruction::hasNoSignedWrap() const {
   return cast<OverflowingBinaryOperator>(this)->hasNoSignedWrap();
 }
 
+bool Instruction::wasSext() const {
+  return cast<WSXTOperator>(this)->wasSext();
+}
+
 bool Instruction::hasPoisonGeneratingFlags() const {
   return cast<Operator>(this)->hasPoisonGeneratingFlags();
 }
 
 void Instruction::dropPoisonGeneratingFlags() {
   switch (getOpcode()) {
   case Instruction::Add:
   case Instruction::Sub:
   case Instruction::Mul:
   case Instruction::Shl:
     cast<OverflowingBinaryOperator>(this)->setHasNoUnsignedWrap(false);
     cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(false);
     break;
 
   case Instruction::UDiv:
   case Instruction::SDiv:
   case Instruction::AShr:
   case Instruction::LShr:
     cast<PossiblyExactOperator>(this)->setIsExact(false);
     break;
 
   case Instruction::GetElementPtr:
     cast<GetElementPtrInst>(this)->setIsInBounds(false);
     break;
+
+  case Instruction::ZExt:
+    cast<WSXTOperator>(this)->setWasSext(false);
+    break;
   }
+
   if (isa<FPMathOperator>(this)) {
     setHasNoNaNs(false);
     setHasNoInfs(false);
   }
 
   assert(!hasPoisonGeneratingFlags() && "must be kept in sync");
 }
 
if (auto *FP = dyn_cast<FPMathOperator>(V))
     if (isa<FPMathOperator>(this))
       copyFastMathFlags(FP->getFastMathFlags());
 
   if (auto *SrcGEP = dyn_cast<GetElementPtrInst>(V))
     if (auto *DestGEP = dyn_cast<GetElementPtrInst>(this))
       DestGEP->setIsInBounds(SrcGEP->isInBounds() || DestGEP->isInBounds());
 }
 
 void Instruction::andIRFlags(const Value *V) {
   if (auto *OB = dyn_cast<OverflowingBinaryOperator>(V)) {
     if (isa<OverflowingBinaryOperator>(this)) {
       setHasNoSignedWrap(hasNoSignedWrap() && OB->hasNoSignedWrap());
       setHasNoUnsignedWrap(hasNoUnsignedWrap() && OB->hasNoUnsignedWrap());
     }
   }
 
   if (auto *PE = dyn_cast<PossiblyExactOperator>(V))
     if (isa<PossiblyExactOperator>(this))
       setIsExact(isExact() && PE->isExact());
 
   if (auto *FP = dyn_cast<FPMathOperator>(V)) {
     if (isa<FPMathOperator>(this)) {
       FastMathFlags FM = getFastMathFlags();
       FM &= FP->getFastMathFlags();
       copyFastMathFlags(FM);
     }
   }
 
   if (auto *SrcGEP = dyn_cast<GetElementPtrInst>(V))
     if (auto *DestGEP = dyn_cast<GetElementPtrInst>(this))
       DestGEP->setIsInBounds(SrcGEP->isInBounds() && DestGEP->isInBounds());
 }
 
 const char *Instruction::getOpcodeName(unsigned OpCode) {
   switch (OpCode) {
   // Terminators
   case Ret:    return "ret";
   case Br:     return "br";
   case Switch: return "switch";
   case IndirectBr: return "indirectbr";
   case Invoke: return "invoke";
   case Resume: return "resume";

llvm/lib/IR/Instructions.cpp

CastInst::castIsValid(Instruction::CastOps op, Type *SrcTy, Type *DstTy) {
   // scalars are not being converted to vectors or vectors to scalars).
   ElementCount SrcEC = SrcIsVec ? cast<VectorType>(SrcTy)->getElementCount()
                                 : ElementCount::getFixed(0);
   ElementCount DstEC = DstIsVec ? cast<VectorType>(DstTy)->getElementCount()
                                 : ElementCount::getFixed(0);
 
   // Switch on the opcode provided
   switch (op) {
-  default: return false; // This is an input error
+  default: {
+    return false; // This is an input error
+  }
   case Instruction::Trunc:
     return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() &&
            SrcEC == DstEC && SrcScalarBitSize > DstScalarBitSize;
-  case Instruction::ZExt:
+  case Instruction::ZExt: {
     return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() &&
            SrcEC == DstEC && SrcScalarBitSize < DstScalarBitSize;
-  case Instruction::SExt:
+  }
+  case Instruction::SExt: {
     return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() &&
            SrcEC == DstEC && SrcScalarBitSize < DstScalarBitSize;
+  }
   case Instruction::FPTrunc:
     return SrcTy->isFPOrFPVectorTy() && DstTy->isFPOrFPVectorTy() &&
            SrcEC == DstEC && SrcScalarBitSize > DstScalarBitSize;
   case Instruction::FPExt:
     return SrcTy->isFPOrFPVectorTy() && DstTy->isFPOrFPVectorTy() &&
            SrcEC == DstEC && SrcScalarBitSize < DstScalarBitSize;
   case Instruction::UIToFP:
   case Instruction::SIToFP:

llvm/test/Assembler/flags.ll

 ; CHECK: ret i64 sub nuw (i64 ptrtoint (ptr @addr to i64), i64 91)
   ret i64 sub nuw (i64 ptrtoint (ptr @addr to i64), i64 91)
 }
 
 define i64 @mul_unsigned_ce() {
 ; CHECK: ret i64 mul nuw (i64 ptrtoint (ptr @addr to i64), i64 91)
   ret i64 mul nuw (i64 ptrtoint (ptr @addr to i64), i64 91)
 }
+define i64 @zext_after_add_signed(i32 %a, i32 %b) {
+; CHECK: %res = zext was_sext i32 %a to i64
+  %res = zext was_sext i32 %a to i64
+    ret i64 %res
+}
+
+define i64 @zext_after_mul_signed(i32 %a, i32 %b) {
+; CHECK: %res = zext was_sext i32 %a to i64
+  %res = zext was_sext i32 %a to i64
+    ret i64 %res
+}
 

llvm/test/Bitcode/constantsTest.3.2.ll

entry:
   ; CHECK-NEXT: shufflevector <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
   shufflevector <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
   ; CHECK-NEXT: extractvalue { i32, float } { i32 1, float 2.000000e+00 }, 0
   extractvalue { i32, float } { i32 1, float 2.0 }, 0
   ; CHECK-NEXT: insertvalue { i32, float } { i32 1, float 2.000000e+00 }, i32 0, 0
   insertvalue { i32, float } { i32 1, float 2.0 }, i32 0, 0
   
   ret void
-}
+}
 

llvm/test/Bitcode/flags.ll

 entry:
   br label %first
 
 second:                                           ; preds = %first
   %u = add nuw i32 %a, 0                          ; <i32> [#uses=0]
   %s = add nsw i32 %a, 0                          ; <i32> [#uses=0]
   %us = add nuw nsw i32 %a, 0                     ; <i32> [#uses=0]
   %z = add i32 %a, 0                              ; <i32> [#uses=0]
+  %hh = zext was_sext i32 %a to i64               ; <i64> [#uses=0]
+  %ll = zext i32 %s to i64                        ; <i64> [#uses=0]
   unreachable
 
 first:                                            ; preds = %entry
   %a = bitcast i32 0 to i32                       ; <i32> [#uses=8]
   %uu = add nuw i32 %a, 0                         ; <i32> [#uses=0]
   %ss = add nsw i32 %a, 0                         ; <i32> [#uses=0]
   %uuss = add nuw nsw i32 %a, 0                   ; <i32> [#uses=0]
   %zz = add i32 %a, 0                             ; <i32> [#uses=0]
+  %kk = zext was_sext i32 %a to i64               ; <i64> [#uses=0]
+  %rr = zext i32 %ss to i64                        ; <i64> [#uses=0]
   br label %second
 }