[RISCV][Backend] Zext flag conversion in RISC-V Backend

[karouzakisp]

Summary

Added zext flag named was_sext in IR
RISCVCodeGenPrepare does a conversion that converts all the
zext instructions with the flag back to sext.

[craig.topper]

Need tests and real patch title.

llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp

89

"an non" -> "a non"

[jrtc27]

Also upload patches with context per https://llvm.org/docs/DeveloperPolicy.html#making-and-submitting-a-patch

[craig.topper]

Should still keep [RISCV] at the beginning of the title. Those tags are helpful for filtering emails from llvm-commits.

[karouzakisp]

Added -U999999 in
git show
to make possible the reviewing via the web interface.

[karouzakisp]

Added simple tests.

[karouzakisp]

Fixed the test that failed to convert the zext(value) to sext(value) whenever the value was assumed to be non negative by llvm.assume

[craig.topper]

llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp

88

Could we have InstCombine call isKnownNonNegative during visitZExt and set the flag if the input is non negative? Then we only need the code here that checks the flag.

[karouzakisp]

Removed IsKnownNonNegative from RISCVCodeGen and added in InstCombine::visitZExt

llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp

 #include "llvm/Pass.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-codegenprepare"
 #define PASS_NAME "RISCV CodeGenPrepare"
 
 STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt");
+STATISTIC(NumZExtToSExtNonNeg,
+          "Number of SExt non negative value instructions converted to ZExt");
 
 namespace {
 
 class RISCVCodeGenPrepare : public FunctionPass,
                             public InstVisitor<RISCVCodeGenPrepare, bool> {
   const DataLayout *DL;
   const RISCVSubtarget *ST;
-
 public:
   static char ID;
 
   RISCVCodeGenPrepare() : FunctionPass(ID) {}
 
   bool runOnFunction(Function &F) override;
 
   StringRef getPassName() const override { return PASS_NAME; }
if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, Src,
     SExt->setDebugLoc(ZExt.getDebugLoc());
 
     ZExt.replaceAllUsesWith(SExt);
     ZExt.eraseFromParent();
     ++NumZExtToSExt;
     return true;
   }
 
+  // Look for zext instructions that have the nneg flag.
+  if (ZExt.hasNonNeg()){
+    auto SExt = new SExtInst(Src, ZExt.getType(), "", &ZExt);
+    SExt->takeName(&ZExt);
+    SExt->setDebugLoc(ZExt.getDebugLoc());
+
+    ZExt.replaceAllUsesWith(SExt);
+    ZExt.eraseFromParent();
+    ++NumZExtToSExtNonNeg;
+    return true; 
+  }
   // Convert (zext (abs(i32 X, i1 1))) -> (sext (abs(i32 X, i1 1))). If abs of
   // INT_MIN is poison, the sign bit is zero.
   using namespace PatternMatch;
   if (match(Src, m_Intrinsic<Intrinsic::abs>(m_Value(), m_One()))) {
     auto *SExt = new SExtInst(Src, ZExt.getType(), "", &ZExt);
     SExt->takeName(&ZExt);
     SExt->setDebugLoc(ZExt.getDebugLoc());
 
bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
   if (skipFunction(F))
     return false;
 
   auto &TPC = getAnalysis<TargetPassConfig>();
   auto &TM = TPC.getTM<RISCVTargetMachine>();
   ST = &TM.getSubtarget<RISCVSubtarget>(F);
 
   DL = &F.getParent()->getDataLayout();
-
   bool MadeChange = false;
   for (auto &BB : F)
     for (Instruction &I : llvm::make_early_inc_range(BB))
       MadeChange |= visit(I);
 
   return MadeChange;
 }
 

llvm/test/CodeGen/RISCV/O3-pipeline.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
 ; RUN:   grep -v "Verify generated machine code" | \
 ; RUN:   FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
 ; RUN:   grep -v "Verify generated machine code" | \
 ; RUN:   FileCheck %s --check-prefixes=CHECK,RV64
 
 ; REQUIRES: asserts

llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll

for.body:                                         ; preds = %for.body, %for.body.preheader.new
   %3 = load i32, ptr %arrayidx.1, align 4
   %add.1 = add nsw i32 %3, 4
   store i32 %add.1, ptr %arrayidx.1, align 4
   %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
   %niter.next.1 = add i64 %niter, 2
   %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
   br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
 }
+
+define i64 @test3(i32 noundef %a){
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sext.w a0, a0
+; CHECK-NEXT:    addi a0, a0, 5
+; CHECK-NEXT:    ret
+
+  %ext = zext nneg i32 %a to i64
+  %added = add i64 %ext, 5
+  ret i64 %added
+}

llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

for.body:                                         ; preds = %for.body, %for.body.preheader.new
   %3 = load i32, ptr %arrayidx.1, align 4
   %add.1 = add nsw i32 %3, 4
   store i32 %add.1, ptr %arrayidx.1, align 4
   %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
   %niter.next.1 = add i64 %niter, 2
   %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
   br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
 }
+
+declare void @llvm.assume(i1 %assume);
+define i64 @test3(i32 noundef signext %a){
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[ASSUME:%.*]] = icmp sge i32 [[A:%.*]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[ASSUME]])
+; CHECK-NEXT:    [[EXT:%.*]] = zext i32 [[A]] to i64
+; CHECK-NEXT:    ret i64 [[EXT]]
+;
+  %assume = icmp sge i32 %a, 0;
+  call void @llvm.assume(i1 %assume)
+  %ext = zext i32 %a to i64
+  ret i64 %ext
+}
+
+
+define i64 @test4(i32 noundef signext %a){
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[EXT:%.*]] = sext i32 [[A:%.*]] to i64
+; CHECK-NEXT:    ret i64 [[EXT]]
+;
+  %ext = zext nneg i32 %a to i64;
+  ret i64 %ext;
+}
+
+