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Differential D156314

[RISCV] Make Zcf and Zcd imply the F and D extensions respectively
ClosedPublic

Authored by asb on Jul 26 2023, 4:42 AM.

Details

Reviewers
craig.topper
reames
kito-cheng
Commits
rG8acb8a143f50: [RISCV] Make Zcf and Zcd imply the F and D extensions respectively
Summary

This was an omission in the spec that has now been addressed https://github.com/riscv/riscv-code-size-reduction/pull/224.

Diff Detail

Event Timeline

asb created this revision.Jul 26 2023, 4:42 AM
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Herald added subscribers: jobnoorman, luke, wingo and 29 others. · View Herald Transcript
asb requested review of this revision.Jul 26 2023, 4:42 AM
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Harbormaster completed remote builds in B248214: Diff 544304.Jul 26 2023, 9:09 AM
craig.topper accepted this revision.Jul 26 2023, 9:20 AM

LGTM

This revision is now accepted and ready to land.Jul 26 2023, 9:20 AM
This revision was landed with ongoing or failed builds.Aug 2 2023, 2:41 AM
Closed by commit rG8acb8a143f50: [RISCV] Make Zcf and Zcd imply the F and D extensions respectively (authored by asb). · Explain Why
This revision was automatically updated to reflect the committed changes.
asb added a commit: rG8acb8a143f50: [RISCV] Make Zcf and Zcd imply the F and D extensions respectively.

Revision Contents

PathSize
llvm/
lib/
Support/
4 lines
test/
CodeGen/
RISCV/
6 lines
MC/
RISCV/
4 lines

Diff 546368

llvm/lib/Support/RISCVISAInfo.cpp

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static const char *ImpliedExtsD[] = {"f"}; static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"}; static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"};
static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
static const char *ImpliedExtsZacas[] = {"a"}; static const char *ImpliedExtsZacas[] = {"a"};
static const char *ImpliedExtsZcb[] = {"zca"}; static const char *ImpliedExtsZcb[] = {"zca"};
static const char *ImpliedExtsZcd[] = {"zca"}; static const char *ImpliedExtsZcd[] = {"d", "zca"};
static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"}; static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
static const char *ImpliedExtsZcf[] = {"zca"}; static const char *ImpliedExtsZcf[] = {"f", "zca"};
static const char *ImpliedExtsZcmp[] = {"zca"}; static const char *ImpliedExtsZcmp[] = {"zca"};
static const char *ImpliedExtsZcmt[] = {"zca"}; static const char *ImpliedExtsZcmt[] = {"zca"};
static const char *ImpliedExtsZdinx[] = {"zfinx"}; static const char *ImpliedExtsZdinx[] = {"zfinx"};
static const char *ImpliedExtsZfa[] = {"f"}; static const char *ImpliedExtsZfa[] = {"f"};
static const char *ImpliedExtsZfbfmin[] = {"f"}; static const char *ImpliedExtsZfbfmin[] = {"f"};
static const char *ImpliedExtsZfh[] = {"f"}; static const char *ImpliedExtsZfh[] = {"f"};
static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfhmin[] = {"f"};
static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZfinx[] = {"zicsr"};
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llvm/test/CodeGen/RISCV/attributes.ll

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; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0" ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0" ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0" ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0" ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0" ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0" ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0" ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
; RV32ZCD: .attribute 5, "rv32i2p1_zca1p0_zcd1p0" ; RV32ZCD: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0" ; RV32ZCF: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"
; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0" ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0" ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0" ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0" ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
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; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0" ; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0"
; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0" ; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0"
; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0" ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0"
; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0" ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1" ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0" ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0" ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0" ; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0" ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0" ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0" ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0" ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
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llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" # CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32izca1p0" .attribute arch, "rv32izca1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0" # CHECK: attribute 5, "rv32i2p1_zca1p0"
.attribute arch, "rv32izcd1p0" .attribute arch, "rv32izcd1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcd1p0" # CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
.attribute arch, "rv32izcf1p0" .attribute arch, "rv32izcf1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcf1p0" # CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"
.attribute arch, "rv32izcb1p0" .attribute arch, "rv32izcb1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0" # CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0"
.attribute arch, "rv32izcmp1p0" .attribute arch, "rv32izcmp1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmp1p0" # CHECK: attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
.attribute arch, "rv32izcmt1p0" .attribute arch, "rv32izcmt1p0"
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