[RISCV] Add support for custom CSRs for Sifive S76.

[garvitgupta08]

Summary

Support for below CSRs is addeed -

1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs

spec:https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This patch removes AltName field from SysReg class because we are now using
separate class for custom vendor CSRs. Also, all use of AltName have been changed
to DeprecatedName because both were interchangeably used for old names which are
not in use in latest RISCV spec.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1804

Space after if

1804

Line exceeds 80 characters

[garvitgupta08]

Addressed the comments

[craig.topper]

llvm/lib/Target/RISCV/RISCVFeatures.td

757

Drop "for S76"

llvm/test/MC/RISCV/xsfcie-invalid.s

6

Are we able to tell the user which option?

[garvitgupta08]

llvm/test/MC/RISCV/xsfcie-invalid.s

6

The existing implementation will need change to tell precisely which options need to be enabled. For now, this patch is using the same implementation of erroring out as earlier if subtarget does not have required features.

[garvitgupta08]

Hi @craig.topper, since custom instruction patch is merged now, can we also go ahead and merge this patch? Thanks

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1792

"a alternate" -> "an alternate"

llvm/lib/Target/RISCV/RISCVSystemOperands.td

23

Do we only allow one vendor to implement an alternate name?

310

Remove S76.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

43

I wonder if maybe we should have a separate table for alternate registers?

[craig.topper]

Will this prevent supporting the Smrnmi which uses these same CSR names. See most recent development copy of the privilege specificvation https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1239329-2023-05-23/riscv-privileged.pdf

[garvitgupta08]

In D153499#4451214, @craig.topper wrote:

Will this prevent supporting the Smrnmi which uses these same CSR names. See most recent development copy of the privilege specificvation https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1239329-2023-05-23/riscv-privileged.pdf

To add support for these CSRs, only one line change is needed in RISCVAsmParser. I have included that change in the latest patchset so that if we have to add those CSRs, we can easily do so without modifying the Parsing logic.

[garvitgupta08]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

23

Currently yes.

43

Can you elaborate on this?

[jrtc27]

Should vendor-specific CSRs not have vendor-prefixed names just as vendor-specific instructions do? Having their names collide with standard ones sounds like a terrible idea.

[jrtc27]

That is, sf.mnstatus etc.

[craig.topper]

I think SiFive core IPs once used the old addresses. Newer versions of cores from SiFive use the standard addresses.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

43

SysReg and SysRegsList together generate a "searchable table". This patch adds extra fields to every CSR in that table just for a couple CSRs. That makes the table larger.

May we should have AltSysReg and AltSysRegsList create a separate second search table for these 2 registers. Or SiFiveSysReg and SiFiveRegsList if we wanted a table per vendor.

[garvitgupta08]

Addressing the comments

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1809

space after if

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

360

Wasn't this field added by a previous version of this patch? Did you upload with the wrong base?

[garvitgupta08]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

360

No, In previous version I added AltFeaturesRequired field. AltName field already existed in the SysReg for aliasing but was apparently being used for deprecated names. As mentioned in the commit message that we now have separate class for custom vendor CSRs therefore there is no need for AltName field anymore.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1808

No need for else after return

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

296

Does this now print the warning "is a deprecated alias for"? Should we have a test for that?

338

Same here

[garvitgupta08]

Added test case for diagnostic message.

[garvitgupta08]

Fixing Premerge checks

[craig.topper]

LGTM

[garvitgupta08]

In D153499#4499870, @craig.topper wrote:

LGTM

Can you commit this on my behalf?
Name - Garvit Gupta
Username - garvitgupta08
Mail id - [e-mail]

[zixuan-wu]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1821

Could this move forward more? Constructing more abstract infra to support all vendor reg instead of just SiFive.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

case AsmToken::String: {
     generateImmOutOfRangeError(S, 0, (1 << 12) - 1);
     return MatchOperand_ParseFail;
   }
   case AsmToken::Identifier: {
     StringRef Identifier;
     if (getParser().parseIdentifier(Identifier))
       return MatchOperand_ParseFail;
 
-    auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
-    if (!SysReg)
-      SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
+    auto SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
+
+    // Accept a alternate named Sys Reg if the alternate required features are
+    // present.
+    if (SysReg) {
+      if (!SysReg->haveAltRequiredFeatures(getSTI().getFeatureBits())) {
+        Error(S, "system register use requires an option to be enabled");
+        return MatchOperand_ParseFail;
+      }
+      Operands.push_back(
+          RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
+      return MatchOperand_Success;
+    }
+
+    SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
+    if (SysReg && SysReg->AltName &&
+        SysReg->haveAltRequiredFeatures(getSTI().getFeatureBits())) {
+      Warning(S,
+              "'" + Identifier +
+                  "' CSR is not available on the current subtarget. Instead '" +
+                  SysReg->AltName + "' CSR will be used.");
+    }
     if (!SysReg)
       if ((SysReg = RISCVSysReg::lookupSysRegByDeprecatedName(Identifier)))
         Warning(S, "'" + Identifier + "' is a deprecated alias for '" +
                        SysReg->Name + "'");
 
     // Accept a named Sys Reg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {
         Error(S, "system register use requires an option to be enabled");
         return MatchOperand_ParseFail;
       }
       Operands.push_back(
           RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
       return MatchOperand_Success;
     }
 
     generateImmOutOfRangeError(S, 0, (1 << 12) - 1,
                                "operand must be a valid system register name "

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 /// immediate value. If the value cannot be represented as a 5-bit binary
 /// encoding, then return -1.
 int getLoadFPImm(APFloat FPImm);
 } // namespace RISCVLoadFPImm
 
 namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
   const char *AltName;
   const char *DeprecatedName;
   unsigned Encoding;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;
   // Privilege Mode: User, System or Machine.
   // unsigned Mode;
   // Check field name.
   // unsigned Extra;
   // Register number without the privilege bits.
   // unsigned Number;
   FeatureBitset FeaturesRequired;
+  FeatureBitset AltFeaturesRequired;
   bool isRV32Only;
 
   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
     // Not in 32-bit mode.
     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
       return false;
     // No required feature associated with the system register.
     if (FeaturesRequired.none())
       return true;
     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
   }
+
+  bool haveAltRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
+    // Not in 32-bit mode.
+    if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
+      return false;
+    // No alternate required feature associated with the system register.
+    if (AltFeaturesRequired.none())
+      return false;
+    return (AltFeaturesRequired & ActiveFeatures) == AltFeaturesRequired;
+  }
 };
 
 #define GET_SysRegsList_DECL
 #include "RISCVGenSearchableTables.inc"
 } // end namespace RISCVSysReg
 
 namespace RISCVInsnOpcode {
 struct RISCVOpcode {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
   }
 }
 
 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
                                               const MCSubtargetInfo &STI,
                                               raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
-  if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
+  if (SysReg) {
+    if (SysReg->AltName &&
+        SysReg->haveAltRequiredFeatures(STI.getFeatureBits()))
+      O << SysReg->AltName;
+    else if (SysReg->haveRequiredFeatures(STI.getFeatureBits()))
       O << SysReg->Name;
     else
       O << Imm;
+   return;
+  }
+  O << Imm;
 }
 
 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   unsigned FenceArg = MI->getOperand(OpNo).getImm();
   assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
 

llvm/lib/Target/RISCV/RISCVFeatures.td

 def FeatureVendorXSfvcp
     : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
                        "XSfvcp (SiFive Custom Vector Coprocessor Interface Instructions)",
                        [FeatureStdExtZve32x]>;
 def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
                                 AssemblerPredicate<(all_of FeatureVendorXSfvcp),
                                 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
 
+def FeatureVendorXSfcie
+    : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
+                       "'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)">;
+def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
+                        AssemblerPredicate<(all_of FeatureVendorXSfcie),
+                        "'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)">;
 
 def FeatureVendorXCVbitmanip
     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
                        "'XCVbitmanip' (Bit Manipulation)">;
 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
                                 "'XCVbitmanip' (Bit Manipulation)">;
 

llvm/lib/Target/RISCV/RISCVProcessors.td

 def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
                                      SiFive7Model,
                                      [Feature64Bit,
                                       FeatureStdExtZifencei,
                                       FeatureStdExtM,
                                       FeatureStdExtA,
                                       FeatureStdExtF,
                                       FeatureStdExtD,
-                                      FeatureStdExtC],
+                                      FeatureStdExtC,
+                                      FeatureVendorXSfcie],
                                      [TuneSiFive7]>;
 
 def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
                                      RocketModel,
                                      [Feature64Bit,
                                       FeatureStdExtZifencei,
                                       FeatureStdExtM,
                                       FeatureStdExtA,

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
 // CSR (control and status register read/write) instruction options.
 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<12> op> {
   string Name = name;
-  // A maximum of one alias is supported right now.
-  string AltName = name;
+  // AltName to be used by Vendors for Custom Vendor Extension.
+  string AltName = "";
   // A maximum of one deprecated name is supported right now.  Unlike the
   // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is
   // used to encourage software to migrate away from the name.
   string DeprecatedName = "";
   bits<12> Encoding = op;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
   // Privilege Mode: User = 0, System = 1 or Machine = 3.
   // bits<2> ReadWrite = op{11 - 10};
   // bits<2> XMode = op{9 - 8};
   // Check Extra field name and what bits 7-6 correspond to.
   // bits<2> Extra = op{7 - 6};
   // Register number without the privilege bits.
   // bits<6> Number = op{5 - 0};
   code FeaturesRequired = [{ {} }];
+  code AltFeaturesRequired = [{ {} }];
   bit isRV32Only = 0;
 }
 
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
   let Fields = [
     "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired",
-    "isRV32Only",
+    "AltFeaturesRequired", "isRV32Only",
   ];
 
   let PrimaryKey = [ "Encoding" ];
   let PrimaryKeyName = "lookupSysRegByEncoding";
 }
 
 def lookupSysRegByName : SearchIndex {
   let Table = SysRegsList;

 // mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
 foreach i = 3...31 in
   def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
 }
 
 //===----------------------------------------------------------------------===//
 // Machine Counter Setup
 //===----------------------------------------------------------------------===//
-let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
+let DeprecatedName  = "mucounteren" in // Privileged spec v1.9.1 Name
 def : SysReg<"mcountinhibit", 0x320>;
 
 // mhpmevent3-mhpmevent31 at 0x323-0x33F.
 foreach i = 3...31 in
   def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
 
 // mhpmevent3h-mhpmevent31h at 0x723-0x73F
 foreach i = 3...31 in {
   let isRV32Only = 1 in
   def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
 }
 
 //===----------------------------------------------------------------------===//
+// Sifive S76 Custom Machine Mode Registers
+//===----------------------------------------------------------------------===//
+
+let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in {
+def : SysReg<"mncause", 0x352>;
+def : SysReg<"mnstatus", 0x353>;
+def : SysReg<"mbpm", 0x7C0>;
+def : SysReg<"mfd", 0x7C1>;
+def : SysReg<"mpd", 0x7C8>;
+}
+
+//===----------------------------------------------------------------------===//
 // Debug/ Trace Registers (shared with Debug Mode)
 //===----------------------------------------------------------------------===//
 def : SysReg<"tselect", 0x7A0>;
 def : SysReg<"tdata1", 0x7A1>;
 def : SysReg<"tdata2", 0x7A2>;
 def : SysReg<"tdata3", 0x7A3>;
 def : SysReg<"mcontext", 0x7A8>;
 
 //===----------------------------------------------------------------------===//
 // Debug Mode Registers
 //===----------------------------------------------------------------------===//
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
 
 // "dscratch" is an alternative name for "dscratch0" which appeared in earlier
 // drafts of the RISC-V debug spec
-let AltName = "dscratch" in
+let DeprecatedName  = "dscratch" in
 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
 
 //===----------------------------------------------------------------------===//
 // User Vector CSRs
 //===----------------------------------------------------------------------===//
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;

 
 def SEED : SysReg<"seed", 0x015>;
 
 //===-----------------------------------------------
 // Advanced Interrupt Architecture
 //===-----------------------------------------------
 
 // Machine-level CSRs
-def : SysReg<"miselect", 0x350>;
-def : SysReg<"mireg", 0x351>;
+def : SysReg<"miselect", 0x350> {
+  let AltName = "mnscratch";
+  let AltFeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }];
+}
+def : SysReg<"mireg", 0x351> {
+  let AltName = "mnepc";
+  let AltFeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }];
+}
 def : SysReg<"mtopei", 0x35C>;
 def : SysReg<"mtopi", 0xFB0>;
 def : SysReg<"mvien", 0x308>;
 def : SysReg<"mvip", 0x309>;
 let isRV32Only = 1 in {
 def : SysReg<"midelegh", 0x313>;
 def : SysReg<"mieh", 0x314>;
 def : SysReg<"mvienh", 0x318>;

llvm/test/MC/RISCV/xsfcie-invalid.s

+# SCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+csrr t1, mbpm # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mfd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mpd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnscratch # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnepc # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mncause # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnstatus # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, miselect # CHECK-ERROR: :[[@LINE]]:11: warning: 'miselect' CSR is not available on the current subtarget. Instead 'mnscratch' CSR will be used.
+
+csrr t1, mireg # CHECK-ERROR: :[[@LINE]]:11: warning: 'mireg' CSR is not available on the current subtarget. Instead 'mnepc' CSR will be used.

llvm/test/MC/RISCV/xsfcie-valid.s

+# SCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
+# RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN:     | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# mbpm
+# name
+# CHECK-INST: csrrs t2, mbpm, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mbpm, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+# name
+csrrs t2, mbpm, zero
+# uimm12
+csrrs t2, 0x7C0, zero
+
+# mfd
+# name
+# CHECK-INST: csrrs t2, mfd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mfd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+# name
+csrrs t2, mfd, zero
+# uimm12
+csrrs t2, 0x7C1, zero
+
+# mpd
+# name
+# CHECK-INST: csrrs t2, mpd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mpd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+# name
+csrrs t2, mpd, zero
+# uimm12
+csrrs t2, 0x7C8, zero
+
+# mnscratch
+# name
+# CHECK-INST: csrrs t1, mnscratch, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mnscratch, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
+# name
+csrrs t1, mnscratch, zero
+csrrs t1, miselect, zero
+# uimm12
+csrrs t2, 0x350, zero
+
+# mnepc
+# name
+# CHECK-INST: csrrs t1, mnepc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mnepc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
+# name
+csrrs t1, mnepc, zero
+csrrs t1, mireg, zero
+# uimm12
+csrrs t2, 0x351, zero
+
+# mncause
+# name
+# CHECK-INST: csrrs t1, mncause, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mncause, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x35]
+# name
+csrrs t1, mncause, zero
+# uimm12
+csrrs t2, 0x352, zero
+
+# mnstatus
+# name
+# CHECK-INST: csrrs t1, mnstatus, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mnstatus, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x35]
+# name
+csrrs t1, mnstatus, zero
+# uimm12
+csrrs t2, 0x353, zero