[RISCV] Add support for custom CSRs for Sifive S76.

[garvitgupta08]

Summary

Support for below CSRs is addeed -

1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs

spec:https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This patch removes AltName field from SysReg class because we are now using
separate class for custom vendor CSRs. Also, all use of AltName have been changed
to DeprecatedName because both were interchangeably used for old names which are
not in use in latest RISCV spec.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1843

Space after if

1843

Line exceeds 80 characters

[garvitgupta08]

Addressed the comments

[craig.topper]

llvm/lib/Target/RISCV/RISCVFeatures.td

757 ↗

(On Diff #533867)

Drop "for S76"

llvm/test/MC/RISCV/xsfcie-invalid.s

5

Are we able to tell the user which option?

[garvitgupta08]

llvm/test/MC/RISCV/xsfcie-invalid.s

5

The existing implementation will need change to tell precisely which options need to be enabled. For now, this patch is using the same implementation of erroring out as earlier if subtarget does not have required features.

[garvitgupta08]

Hi @craig.topper, since custom instruction patch is merged now, can we also go ahead and merge this patch? Thanks

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1831

"a alternate" -> "an alternate"

llvm/lib/Target/RISCV/RISCVSystemOperands.td

22

Do we only allow one vendor to implement an alternate name?

326

Remove S76.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

40

I wonder if maybe we should have a separate table for alternate registers?

[craig.topper]

Will this prevent supporting the Smrnmi which uses these same CSR names. See most recent development copy of the privilege specificvation https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1239329-2023-05-23/riscv-privileged.pdf

[garvitgupta08]

In D153499#4451214, @craig.topper wrote:

Will this prevent supporting the Smrnmi which uses these same CSR names. See most recent development copy of the privilege specificvation https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-1239329-2023-05-23/riscv-privileged.pdf

To add support for these CSRs, only one line change is needed in RISCVAsmParser. I have included that change in the latest patchset so that if we have to add those CSRs, we can easily do so without modifying the Parsing logic.

[garvitgupta08]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

22

Currently yes.

40

Can you elaborate on this?

[jrtc27]

Should vendor-specific CSRs not have vendor-prefixed names just as vendor-specific instructions do? Having their names collide with standard ones sounds like a terrible idea.

[jrtc27]

That is, sf.mnstatus etc.

[craig.topper]

I think SiFive core IPs once used the old addresses. Newer versions of cores from SiFive use the standard addresses.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

40

SysReg and SysRegsList together generate a "searchable table". This patch adds extra fields to every CSR in that table just for a couple CSRs. That makes the table larger.

May we should have AltSysReg and AltSysRegsList create a separate second search table for these 2 registers. Or SiFiveSysReg and SiFiveRegsList if we wanted a table per vendor.

[garvitgupta08]

Addressing the comments

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1825

space after if

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

366

Wasn't this field added by a previous version of this patch? Did you upload with the wrong base?

[garvitgupta08]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

366

No, In previous version I added AltFeaturesRequired field. AltName field already existed in the SysReg for aliasing but was apparently being used for deprecated names. As mentioned in the commit message that we now have separate class for custom vendor CSRs therefore there is no need for AltName field anymore.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1824

No need for else after return

[craig.topper]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

312

Does this now print the warning "is a deprecated alias for"? Should we have a test for that?

356

Same here

[garvitgupta08]

Added test case for diagnostic message.

[garvitgupta08]

Fixing Premerge checks

[craig.topper]

LGTM

[garvitgupta08]

In D153499#4499870, @craig.topper wrote:

LGTM

Can you commit this on my behalf?
Name - Garvit Gupta
Username - garvitgupta08
Mail id - [e-mail]

[zixuan-wu]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1839

Could this move forward more? Constructing more abstract infra to support all vendor reg instead of just SiFive.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

case AsmToken::String: {
 
     return generateImmOutOfRangeError(S, 0, (1 << 12) - 1);
   }
   case AsmToken::Identifier: {
     StringRef Identifier;
     if (getParser().parseIdentifier(Identifier))
       return ParseStatus::Failure;
 
+    // Check for CSR names conflicts.
+    // Custom CSR names might conflict with CSR names in privileged spec.
+    // E.g. - SiFive mnscratch(0x350) and privileged spec mnscratch(0x740).
+    auto CheckCSRNameConflict = [&]() {
+      if (!(RISCVSysReg::lookupSysRegByName(Identifier))) {
+        Error(S, "system register use requires an option to be enabled");
+        return true;
+      }
+      return false;
+    };
+
+    // First check for vendor specific CSRs.
+    auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByName(Identifier);
+    if (SiFiveReg) {
+      if (SiFiveReg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) {
+        Operands.push_back(
+            RISCVOperand::createSysReg(Identifier, S, SiFiveReg->Encoding));
+        return ParseStatus::Success;
+      }
+      if (CheckCSRNameConflict())
+        return ParseStatus::Failure;
+    }
+
     auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
     if (!SysReg)
-      SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
-    if (!SysReg)
       if ((SysReg = RISCVSysReg::lookupSysRegByDeprecatedName(Identifier)))
         Warning(S, "'" + Identifier + "' is a deprecated alias for '" +
                        SysReg->Name + "'");
 
-    // Accept a named Sys Reg if the required features are present.
+    // Check for CSR encoding conflicts.
+    // Custom CSR encoding might conflict with CSR encoding in privileged spec.
+    // E.g. - SiFive mnscratch(0x350) and privileged spec miselect(0x350).
+    auto CheckCSREncodingConflict = [&]() {
+      auto Reg = RISCVSysReg::lookupSiFiveRegByEncoding(SysReg->Encoding);
+      if (Reg && Reg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) {
+        Warning(S, "'" + Identifier + "' CSR is not available on the current " +
+                       "subtarget. Instead '" + Reg->Name +
+                       "' CSR will be used.");
+        Operands.push_back(
+            RISCVOperand::createSysReg(Reg->Name, S, Reg->Encoding));
+        return true;
+      }
+      return false;
+    };
+
+    // Accept a named SysReg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits()))
         return Error(S, "system register use requires an option to be enabled");
+      if (CheckCSREncodingConflict())
+        return ParseStatus::Success;
       Operands.push_back(
           RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
       return ParseStatus::Success;
     }
 
     return generateImmOutOfRangeError(S, 0, (1 << 12) - 1,
                                       "operand must be a valid system register "
                                       "name or an integer in the range");

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 /// immediate value. If the value cannot be represented as a 5-bit binary
 /// encoding, then return -1.
 int getLoadFPImm(APFloat FPImm);
 } // namespace RISCVLoadFPImm
 
 namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
-  const char *AltName;
   const char *DeprecatedName;
   unsigned Encoding;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;
   // Privilege Mode: User, System or Machine.
   // unsigned Mode;
   // Check field name.
   // unsigned Extra;
   // Register number without the privilege bits.
   // unsigned Number;
   FeatureBitset FeaturesRequired;
   bool isRV32Only;
 
   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
     // Not in 32-bit mode.
     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
       return false;
     // No required feature associated with the system register.
     if (FeaturesRequired.none())
       return true;
     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
   }
+
+  bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
+    // Not in 32-bit mode.
+    if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
+      return false;
+    // No required feature associated with the system register.
+    if (FeaturesRequired.none())
+      return false;
+    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
+  }
 };
 
+struct SiFiveReg : SysReg {};
+
 #define GET_SysRegsList_DECL
+#define GET_SiFiveRegsList_DECL
 #include "RISCVGenSearchableTables.inc"
 } // end namespace RISCVSysReg
 
 namespace RISCVInsnOpcode {
 struct RISCVOpcode {
   const char *Name;
   unsigned Value;
 };

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

 #include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 
 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
 
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL
+#define GET_SiFiveRegsList_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCVSysReg
 
 namespace RISCVInsnOpcode {
 #define GET_RISCVOpcodesList_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCVInsnOpcode
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

if (PrintBranchImmAsAddress) {
     O << MO.getImm();
   }
 }
 
 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
                                               const MCSubtargetInfo &STI,
                                               raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
+  auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
   auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
-  if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
+  if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits()))
+    O << SiFiveReg->Name;
+  else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
     O << SysReg->Name;
   else
     O << Imm;
 }
 
 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
 // CSR (control and status register read/write) instruction options.
 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<12> op> {
   string Name = name;
-  // A maximum of one alias is supported right now.
-  string AltName = name;
-  // A maximum of one deprecated name is supported right now.  Unlike the
-  // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is
-  // used to encourage software to migrate away from the name.
+  // A maximum of one deprecated name is supported right now. It generates a
+  // diagnostic when the name is used to encourage software to migrate away from
+  // the name.
   string DeprecatedName = "";
   bits<12> Encoding = op;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
   // Privilege Mode: User = 0, System = 1 or Machine = 3.
   // bits<2> ReadWrite = op{11 - 10};
   // bits<2> XMode = op{9 - 8};
   // Check Extra field name and what bits 7-6 correspond to.
   // bits<2> Extra = op{7 - 6};
   // Register number without the privilege bits.
   // bits<6> Number = op{5 - 0};
   code FeaturesRequired = [{ {} }];
   bit isRV32Only = 0;
 }
 
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
   let Fields = [
-    "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired",
+    "Name", "DeprecatedName", "Encoding", "FeaturesRequired",
     "isRV32Only",
   ];
 
   let PrimaryKey = [ "Encoding" ];
   let PrimaryKeyName = "lookupSysRegByEncoding";
 }
 
 def lookupSysRegByName : SearchIndex {
   let Table = SysRegsList;
   let Key = [ "Name" ];
 }
 
-def lookupSysRegByAltName : SearchIndex {
+def lookupSysRegByDeprecatedName : SearchIndex {
   let Table = SysRegsList;
-  let Key = [ "AltName" ];
+  let Key = [ "DeprecatedName" ];
 }
 
-def lookupSysRegByDeprecatedName : SearchIndex {
-  let Table = SysRegsList;
+class SiFiveReg<string name, bits<12> op> : SysReg<name, op>;
+
+def SiFiveRegsList : GenericTable {
+  let FilterClass = "SiFiveReg";
+  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
+  let Fields = [
+    "Name", "DeprecatedName", "Encoding", "FeaturesRequired",
+    "isRV32Only",
+  ];
+
+  let PrimaryKey = [ "Encoding" ];
+  let PrimaryKeyName = "lookupSiFiveRegByEncoding";
+}
+
+def lookupSiFiveRegByName : SearchIndex {
+  let Table = SiFiveRegsList;
+  let Key = [ "Name" ];
+}
+
+def lookupSiFiveRegByDeprecatedName : SearchIndex {
+  let Table = SiFiveRegsList;
   let Key = [ "DeprecatedName" ];
 }
 
 // The following CSR encodings match those given in Tables 2.2,
 // 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
 
 //===----------------------------------------------------------------------===//

 // mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
 foreach i = 3...31 in
   def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
 }
 
 //===----------------------------------------------------------------------===//
 // Machine Counter Setup
 //===----------------------------------------------------------------------===//
-let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
+let DeprecatedName = "mucounteren" in // Privileged spec v1.9.1 Name
 def : SysReg<"mcountinhibit", 0x320>;
 
 // mhpmevent3-mhpmevent31 at 0x323-0x33F.
 foreach i = 3...31 in
   def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
 
 // mhpmevent3h-mhpmevent31h at 0x723-0x73F
 foreach i = 3...31 in {
   let isRV32Only = 1 in
   def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
 }
 
 //===----------------------------------------------------------------------===//
+// SiFive Custom Machine Mode Registers
+//===----------------------------------------------------------------------===//
+
+let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in {
+def : SiFiveReg<"mnscratch", 0x350>;
+def : SiFiveReg<"mnepc", 0x351>;
+def : SiFiveReg<"mncause", 0x352>;
+def : SiFiveReg<"mnstatus", 0x353>;
+def : SiFiveReg<"mbpm", 0x7C0>;
+def : SiFiveReg<"mfd", 0x7C1>;
+def : SiFiveReg<"mpd", 0x7C8>;
+}
+
+//===----------------------------------------------------------------------===//
 // Debug/ Trace Registers (shared with Debug Mode)
 //===----------------------------------------------------------------------===//
 def : SysReg<"tselect", 0x7A0>;
 def : SysReg<"tdata1", 0x7A1>;
 def : SysReg<"tdata2", 0x7A2>;
 def : SysReg<"tdata3", 0x7A3>;
 def : SysReg<"mcontext", 0x7A8>;
 
 //===----------------------------------------------------------------------===//
 // Debug Mode Registers
 //===----------------------------------------------------------------------===//
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
 
 // "dscratch" is an alternative name for "dscratch0" which appeared in earlier
 // drafts of the RISC-V debug spec
-let AltName = "dscratch" in
+let DeprecatedName = "dscratch" in
 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
 
 //===----------------------------------------------------------------------===//
 // User Vector CSRs
 //===----------------------------------------------------------------------===//
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;

llvm/test/MC/RISCV/machine-csr-names.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
+# RUN: llvm-mc -triple riscv64 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
 
 ##################################
 # Machine Information Registers
 ##################################
 
 # mvendorid
 # name
 # CHECK-INST: csrrs t1, mvendorid, zero

 # CHECK-INST: csrrs t2, dscratch0, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
 # CHECK-INST-ALIAS: csrr t2, dscratch0
 # name
 csrrs t1, dscratch, zero
 # uimm12
 csrrs t2, 0x7B2, zero
 
+# CHECK-WARN: warning: 'dscratch' is a deprecated alias for 'dscratch0'
+
 # dscratch1
 # name
 # CHECK-INST: csrrs t1, dscratch1, zero
 # CHECK-ENC: encoding: [0x73,0x23,0x30,0x7b]
 # CHECK-INST-ALIAS: csrr t1, dscratch1
 # uimm12
 # CHECK-INST: csrrs t2, dscratch1, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7b]

 # CHECK-INST: csrrs t2, mcountinhibit, zero
 # CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
 # CHECK-INST-ALIAS: csrr t2, mcountinhibit
 # name
 csrrs t1, mucounteren, zero
 # uimm12
 csrrs t2, 0x320, zero
 
+# CHECK-WARN: warning: 'mucounteren' is a deprecated alias for 'mcountinhibit'
+
 # mhpmevent3
 # name
 # CHECK-INST: csrrs t1, mhpmevent3, zero
 # CHECK-ENC:  encoding: [0x73,0x23,0x30,0x32]
 # CHECK-INST-ALIAS: csrr t1, mhpmevent3
 # uimm12
 # CHECK-INST: csrrs t2, mhpmevent3, zero
 # CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x32]

llvm/test/MC/RISCV/xsfcie-invalid.s

 # SCIE - SiFive Custom Instructions Extension.
 # RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
 # RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
 
 cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 
 cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
 
 cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
 
 cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
 
 cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
 
 cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+csrr t1, mbpm # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mfd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mpd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnscratch # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnepc # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mncause # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled
+
+csrr t1, mnstatus # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled

llvm/test/MC/RISCV/xsfcie-valid.s

 # SCIE - SiFive Custom Instructions Extension.
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
 # RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
 # RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
 # RUN:     | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: cflush.d.l1     zero
 # CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
 # CHECK-INST: cflush.d.l1     zero
 # CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]

 
 # CHECK-INST: cdiscard.d.l1   t2
 # CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
 cdiscard.d.l1 x7
 
 # CHECK-INST: cease
 # CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
 cease
+
+# mbpm
+# name
+# CHECK-INST: csrrs t2, mbpm, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mbpm, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+# name
+csrrs t2, mbpm, zero
+# uimm12
+csrrs t2, 0x7C0, zero
+
+# mfd
+# name
+# CHECK-INST: csrrs t2, mfd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mfd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+# name
+csrrs t2, mfd, zero
+# uimm12
+csrrs t2, 0x7C1, zero
+
+# mpd
+# name
+# CHECK-INST: csrrs t2, mpd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+# uimm12
+# CHECK-INST: csrrs t2, mpd, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+# name
+csrrs t2, mpd, zero
+# uimm12
+csrrs t2, 0x7C8, zero
+
+# mnscratch
+# name
+# CHECK-INST: csrrs t1, mnscratch, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
+# CHECK-WARN: warning: 'miselect' CSR is not available on the current subtarget. Instead 'mnscratch' CSR will be used.
+# uimm12
+# CHECK-INST: csrrs t2, mnscratch, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
+# name
+csrrs t1, mnscratch, zero
+csrrs t1, miselect, zero
+# uimm12
+csrrs t2, 0x350, zero
+
+# mnepc
+# name
+# CHECK-INST: csrrs t1, mnepc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
+# CHECK-WARN: warning: 'mireg' CSR is not available on the current subtarget. Instead 'mnepc' CSR will be used.
+# uimm12
+# CHECK-INST: csrrs t2, mnepc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
+# name
+csrrs t1, mnepc, zero
+csrrs t1, mireg, zero
+# uimm12
+csrrs t2, 0x351, zero
+
+# mncause
+# name
+# CHECK-INST: csrrs t1, mncause, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mncause, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x35]
+# name
+csrrs t1, mncause, zero
+# uimm12
+csrrs t2, 0x352, zero
+
+# mnstatus
+# name
+# CHECK-INST: csrrs t1, mnstatus, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x35]
+# uimm12
+# CHECK-INST: csrrs t2, mnstatus, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x35]
+# name
+csrrs t1, mnstatus, zero
+# uimm12
+csrrs t2, 0x353, zero