[ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[stuij]

Summary

This patch adds the LLVM-side plumbing for the following relocations:

• R_ARM_THM_ALU_ABS_G0_NC
• R_ARM_THM_ALU_ABS_G1_NC
• R_ARM_THM_ALU_ABS_G2_NC
• R_ARM_THM_ALU_ABS_G3

(see section 5.6.1.5, Static Thumb16 relocations, of the AArch32 ELF Arm ABI:
https://github.com/ARM-software/abi-aa/blob/844a79fd4c77252a11342709e3b27b2c9f590cf1/aaelf32/aaelf32.rst#5615static-thumb16-relocations)

Which can respectivly be generated by prefixing assembly symbols with:

• :lower0_7:
• :lower8_15:
• :upper0_7:
• :upper8_15:

LLD support for these relocations will be added in a follow-up patch

[simonwallis2]

llvm/lib/Target/ARM/ARMInstrThumb.td

998–1000

{ let DecoderMethod = "DecodeI8RelocInstruction"; }
applies to tADDi8, not tADDrr,
so it should be moved 10 lines earlier.

[stuij]

Still WIP, but fixed failing tests, and removed decoder method from add for now (do we actually need it?) so this patch is friendlier for other work that depends on it.

[simonwallis2]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

1247

llvm_unreachable(":upper_8_15: not supported in ARM state");

1252

Following the architectural definitions,
the term "state" describes an instruction set state (ARM state or Thumb state);
and the term "mode" or "processor mode" relates to execution privilege level.

1257

ARM state

1262

ARM state

[stuij]

added testing, addressed review comment

[stuij]

add GNU syntax

[john.brawn]

A few comments:

• Please run clang-format on the patch (pre-merge is showing as failed due to this)
• We should have a test to check that we're emitting the right relocation (probably something similar to test/MC/ARM/thumb-movwt-reloc.s)
• There should be something in ARMAsmParser::validateInstruction to check that the expression is valid, like we do for movw/movt, as currently you can do movs r0, :lower16:some_symbol and it's accepted and results in a 16-bit mov with a movw relocation.
• Something weird is happening when I try to use these expressions in movs on v7m. If I try to assemble movs r0, :upper8_15:some_symbol I get "error: expected relocatable expression", and looking at the llvm-mc --show-encoding --show-inst-operands it's selected movs.w instead of 16-bit mov for some reason.

[john.brawn]

llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def

141

According to the ABI document this is R_ARM_THM_ALU_ABS_G3, i.e. without the _NC.

[stuij]

addressed review comment

[stuij]

llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def

141

Yes, I noticed that as well, but must have forgotten to update it. Done!

[john.brawn]

This is still missing a test that the correct relocations are emitted, and checking in ARMAsmParser::validateInstruction that expression is valid.

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

498–505

The calculation here isn't correct when IsResolved is false. In that case we're calculating the addend for a relocation, and the value of that will be Value&0xff for all four of these fixups (movw/movt has similar behaviour).

[stuij]

In D149443#4418136, @john.brawn wrote:

This is still missing a test that the correct relocations are emitted, and checking in ARMAsmParser::validateInstruction that expression is valid.

Yes, I just wanted to possibly unblock you for the LLD work. Still need to address the rest of the comments.

[stuij]

addressed review comments

[stuij]

In D149443#4403186, @john.brawn wrote:

A few comments:

• Please run clang-format on the patch (pre-merge is showing as failed due to this)
• We should have a test to check that we're emitting the right relocation (probably something similar to test/MC/ARM/thumb-movwt-reloc.s)
• There should be something in ARMAsmParser::validateInstruction to check that the expression is valid, like we do for movw/movt, as currently you can do movs r0, :lower16:some_symbol and it's accepted and results in a 16-bit mov with a movw relocation.
• Something weird is happening when I try to use these expressions in movs on v7m. If I try to assemble movs r0, :upper8_15:some_symbol I get "error: expected relocatable expression", and looking at the llvm-mc --show-encoding --show-inst-operands it's selected movs.w instead of 16-bit mov for some reason.

the recent changes should have addressed all of these

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

498–505

done

[john.brawn]

LGTM

[MaskRay]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

6422

Use parseOptionalToken.

[MaskRay]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1244

isUInt<8>(Value).

Can the limit be tested?

llvm/test/MC/ARM/thumb-8-bit-relocs.s

2

-filetype asm can be omitted.

32

Add -NEXT whenever applicable to test that there is no other relocation.

[stuij]

addressed review comments

[MaskRay]

llvm/test/MC/ARM/thumb-fixups.s

2

We normally just pipe the output to FileCheck, e.g. | FileCheck %s

10

[stuij]

address review comments

llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def

 ELF_RELOC(R_ARM_PRIVATE_11,             0x7b)
 ELF_RELOC(R_ARM_PRIVATE_12,             0x7c)
 ELF_RELOC(R_ARM_PRIVATE_13,             0x7d)
 ELF_RELOC(R_ARM_PRIVATE_14,             0x7e)
 ELF_RELOC(R_ARM_PRIVATE_15,             0x7f)
 ELF_RELOC(R_ARM_ME_TOO,                 0x80)
 ELF_RELOC(R_ARM_THM_TLS_DESCSEQ16,      0x81)
 ELF_RELOC(R_ARM_THM_TLS_DESCSEQ32,      0x82)
+ELF_RELOC(R_ARM_THM_ALU_ABS_G0_NC,      0x84)
+ELF_RELOC(R_ARM_THM_ALU_ABS_G1_NC,      0x85)
+ELF_RELOC(R_ARM_THM_ALU_ABS_G2_NC,      0x86)
+ELF_RELOC(R_ARM_THM_ALU_ABS_G3,         0x87)
 ELF_RELOC(R_ARM_THM_BF16,               0x88)
 ELF_RELOC(R_ARM_THM_BF12,               0x89)
 ELF_RELOC(R_ARM_THM_BF18,               0x8a)
 ELF_RELOC(R_ARM_IRELATIVE,              0xa0)

llvm/lib/Target/ARM/ARMInstrInfo.td

 }
 
 /// imm0_255 predicate - Immediate in the range [0,255].
 def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; }
 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
   let ParserMatchClass = Imm0_255AsmOperand;
 }
 
+// imm0_255_expr - For Thumb1 movs/adds - 8-bit immediate that can also reference
+// a relocatable expression.
+def Imm0_255ExprAsmOperand: AsmOperandClass {
+  let Name = "Imm0_255Expr";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticString = "operand must be an immediate in the range [0,255] or a relocatable expression";
+}
+
+def imm0_255_expr : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
+  let EncoderMethod = "getHiLoImmOpValue";
+  let ParserMatchClass = Imm0_255ExprAsmOperand;
+}
+
 /// imm0_65535 - An immediate is in the range [0,65535].
 def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; }
 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 65536;
 }]> {
   let ParserMatchClass = Imm0_65535AsmOperand;
 }
 

 // While the range is the same, and can thus use the same match class,
 // the encoding is different so it should have a different encoder method.
 def Imm0_65535ExprAsmOperand: AsmOperandClass {
   let Name = "Imm0_65535Expr";
   let RenderMethod = "addImmOperands";
   let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
 }
 
-def imm0_65535_expr : Operand<i32> {
-  let EncoderMethod = "getHiLo16ImmOpValue";
+def imm0_65535_expr : Operand<i32>, ImmLeaf<i32, [{
+  return Imm >= 0 && Imm < 65536;
+}]> {
+  let EncoderMethod = "getHiLoImmOpValue";
   let ParserMatchClass = Imm0_65535ExprAsmOperand;
 }
 
 def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; }
 def imm256_65535_expr : Operand<i32> {
   let ParserMatchClass = Imm256_65535ExprAsmOperand;
 }
 

llvm/lib/Target/ARM/ARMInstrThumb.td

T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                      [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
                      Sched<[WriteALU]> {
     bits<3> imm3;
     let Inst{8-6} = imm3;
   }
 
   def tADDi8 :                    // A8.6.4 T2
     T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
-                      (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
+                      (ins tGPR:$Rn, imm0_255_expr:$imm8), IIC_iALUi,
                       "add", "\t$Rdn, $imm8",
-                      [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
+                      [(set tGPR:$Rdn, (add tGPR:$Rn, imm0_255_expr:$imm8))]>,
                       Sched<[WriteALU]>;
 
   // Add register
   let isCommutable = 1 in
   def tADDrr :                    // A8.6.6 T1
     T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
                   IIC_iALUr,
                   "add", "\t$Rd, $Rn, $Rm",
-                  [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                  [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
+                  Sched<[WriteALU]>;
 
   /// Similar to the above except these set the 's' bit so the
   /// instruction modifies the CPSR register.
   ///
   /// These opcodes will be converted to the real non-S opcodes by
   /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
   let hasPostISelHook = 1, Defs = [CPSR] in {
     let isCommutable = 1, Uses = [CPSR] in
     def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                             2, IIC_iALUr,
                             [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
                                                             CPSR))]>,
                 Requires<[IsThumb1Only]>,
                 Sched<[WriteALU]>;
 
     def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                               2, IIC_iALUi,
                               [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
                                                              imm0_7:$imm3))]>,
                   Requires<[IsThumb1Only]>,
                   Sched<[WriteALU]>;
 
-    def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
+    def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255_expr:$imm8),
                               2, IIC_iALUi,
                               [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,
-                                                      imm8_255:$imm8))]>,
+                                                      imm0_255_expr:$imm8))]>,
                   Requires<[IsThumb1Only]>,
                   Sched<[WriteALU]>;
 
     let isCommutable = 1 in
     def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
                               2, IIC_iALUr,
                               [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
                                                              tGPR:$Rm))]>,

 def tLSRrr :                    // A8.6.91
   T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iMOVsr,
                 "lsr", "\t$Rdn, $Rm",
                 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
 
 // Move register
 let isMoveImm = 1 in
-def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
+def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255_expr:$imm8), IIC_iMOVi,
                   "mov", "\t$Rd, $imm8",
-                  [(set tGPR:$Rd, imm0_255:$imm8)]>,
+                  [(set tGPR:$Rd, imm0_255_expr:$imm8)]>,
              T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
   // A8.6.96
   bits<3> Rd;
   bits<8> imm8;
   let Inst{10-8} = Rd;
   let Inst{7-0}  = imm8;
 }
 // Because we have an explicit tMOVSr below, we need an alias to handle
 // the immediate "movs" form here. Blech.
-def : tInstAlias <"movs $Rdn, $imm",
-                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
+def : tInstAlias <"movs $Rdn, $imm8",
+                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255_expr:$imm8, 14, 0)>;
 
 // A7-73: MOV(2) - mov setting flag.
 
 let hasSideEffects = 0, isMoveReg = 1 in {
 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
                       2, IIC_iMOVr,
                       "mov", "\t$Rd, $Rm", "", []>,
                   T1Special<{1,0,?,?}>, Sched<[WriteALU]> {

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

public:
   bool isImm1_32() const {
     return isImmediate<1, 32>();
   }
 
   bool isImm8_255() const {
     return isImmediate<8, 255>();
   }
 
+  bool isImm0_255Expr() const {
+    if (!isImm())
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    // If it's not a constant expression, it'll generate a fixup and be
+    // handled later.
+    if (!CE)
+      return true;
+    int64_t Value = CE->getValue();
+    return isUInt<8>(Value);
+  }
+
   bool isImm256_65535Expr() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // If it's not a constant expression, it'll generate a fixup and be
     // handled later.
     if (!CE) return true;
     int64_t Value = CE->getValue();
     return Value >= 256 && Value < 65536;
if (Parser.getTok().isNot(AsmToken::Colon)) {
       }
       return false;
     }
     // w/ a ':' after the '#', it's just like a plain ':'.
     [[fallthrough]];
   }
   case AsmToken::Colon: {
     S = Parser.getTok().getLoc();
-    // ":lower16:" and ":upper16:" expression prefixes
+    // ":lower16:", ":upper16:", ":lower0_7:", ":lower8_15:", ":upper0_7:" and
+    // ":upper8_15:", expression prefixes
     // FIXME: Check it's an expression prefix,
     // e.g. (FOO - :lower16:BAR) isn't legal.
     ARMMCExpr::VariantKind RefKind;
     if (parsePrefix(RefKind))
       return true;
 
     const MCExpr *SubExprVal;
     if (getParser().parseExpression(SubExprVal))
if (check(getParser().parseExpression(Expr), L, "expected expression"))
     return true;
   const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
   if (check(!Value, L, "expected constant expression"))
     return true;
   Out = Value->getValue();
   return false;
 }
 
-// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
-//  :lower16: and :upper16:.
+// parsePrefix - Parse ARM 16-bit relocations expression prefixes, i.e.
+// :lower16: and :upper16: and Thumb 8-bit relocation expression prefixes, i.e.
+// :upper8_15:, :upper0_7:, :lower8_15: and :lower0_7:
 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
   MCAsmParser &Parser = getParser();
   RefKind = ARMMCExpr::VK_ARM_None;
 
   // consume an optional '#' (GNU compatibility)
   if (getLexer().is(AsmToken::Hash))
     Parser.Lex();
 
-  // :lower16: and :upper16: modifiers
   assert(getLexer().is(AsmToken::Colon) && "expected a :");
   Parser.Lex(); // Eat ':'
 
   if (getLexer().isNot(AsmToken::Identifier)) {
     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
     return true;
   }
 
   enum {
     COFF = (1 << MCContext::IsCOFF),
     ELF = (1 << MCContext::IsELF),
     MACHO = (1 << MCContext::IsMachO),
     WASM = (1 << MCContext::IsWasm),
   };
   static const struct PrefixEntry {
     const char *Spelling;
     ARMMCExpr::VariantKind VariantKind;
     uint8_t SupportedFormats;
   } PrefixEntries[] = {
-    { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
-    { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
+      {"upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO},
+      {"lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO},
+      {"upper8_15", ARMMCExpr::VK_ARM_HI_8_15, ELF},
+      {"upper0_7", ARMMCExpr::VK_ARM_HI_0_7, ELF},
+      {"lower8_15", ARMMCExpr::VK_ARM_LO_8_15, ELF},
+      {"lower0_7", ARMMCExpr::VK_ARM_LO_0_7, ELF},
   };
 
   StringRef IDVal = Parser.getTok().getIdentifier();
 
   const auto &Prefix =
       llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) {
         return PE.Spelling == IDVal;
       });
bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
   Parser.Lex();
 
   if (getLexer().isNot(AsmToken::Colon)) {
     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
     return true;
   }
   Parser.Lex(); // Eat the last ':'
 
+  // consume an optional trailing '#' (GNU compatibility) bla
+  parseOptionalToken(AsmToken::Hash);
+
   return false;
 }
 
 /// Given a mnemonic, split out possible predication code and carry
 /// setting letters to form a canonical mnemonic and flags.
 //
 // FIXME: Would be nice to autogen this.
 // FIXME: This is a bit of a maze of special cases.
void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
 
   if (Transform) {
     if (Swap)
       std::swap(Op4, Op5);
     Operands.erase(Operands.begin() + 3);
   }
 }
 
+// this function returns true if the operand is one of the following
+// relocations: :upper8_15:, :upper0_7:, :lower8_15: or :lower0_7:
+static bool isThumbI8Relocation(MCParsedAsmOperand &MCOp) {
+  ARMOperand &Op = static_cast<ARMOperand &>(MCOp);
+  if (!Op.isImm())
+    return false;
+  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
+  if (CE)
+    return false;
+  const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
+  if (!E)
+    return false;
+  const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
+  if (ARM16Expr && (ARM16Expr->getKind() == ARMMCExpr::VK_ARM_HI_8_15 ||
+                    ARM16Expr->getKind() == ARMMCExpr::VK_ARM_HI_0_7 ||
+                    ARM16Expr->getKind() == ARMMCExpr::VK_ARM_LO_8_15 ||
+                    ARM16Expr->getKind() == ARMMCExpr::VK_ARM_LO_0_7))
+    return true;
+  return false;
+}
+
 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
                                           OperandVector &Operands) {
   // FIXME: This is all horribly hacky. We really need a better way to deal
   // with optional operands like this in the matcher table.
 
   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
   // another does not. Specifically, the MOVW instruction does not. So we
   // special case it here and remove the defaulted (non-setting) cc_out
   // operand if that's the instruction we're trying to match.
   //
   // We do this as post-processing of the explicit operands rather than just
   // conditionally adding the cc_out in the first place because we need
   // to check the type of the parsed immediate operand.
   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
     return true;
 
+  if (Mnemonic == "movs" && Operands.size() > 3 && isThumb() &&
+      isThumbI8Relocation(*Operands[3]))
+    return true;
+
   // Register-register 'add' for thumb does not have a cc_out operand
   // when there are only two register operands.
   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
     return true;
   // Register-register 'add' for thumb does not have a cc_out operand
static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
   }
   return -1;
 }
 
 static bool isVectorPredicable(const MCInstrDesc &MCID) {
   return findFirstVectorPredOperandIdx(MCID) != -1;
 }
 
+static bool isARMMCExpr(MCParsedAsmOperand &MCOp) {
+  ARMOperand &Op = static_cast<ARMOperand &>(MCOp);
+  if (!Op.isImm())
+    return false;
+  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
+  if (CE)
+    return false;
+  const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
+  if (!E)
+    return false;
+  return true;
+}
+
 // FIXME: We would really like to be able to tablegen'erate this.
 bool ARMAsmParser::validateInstruction(MCInst &Inst,
                                        const OperandVector &Operands) {
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   SMLoc Loc = Operands[0]->getStartLoc();
 
   // Check the IT block state first.
   // NOTE: BKPT and HLT instructions have the interesting property of being
case ARM::t2MOVTi16:
     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
       return Error(
           Op.getStartLoc(),
           "immediate expression for mov requires :lower16: or :upper16");
     break;
   }
+  case ARM::tADDi8: {
+    MCParsedAsmOperand &Op = *Operands[4];
+    if (isARMMCExpr(Op) && !isThumbI8Relocation(Op))
+      return Error(Op.getStartLoc(),
+                   "Immediate expression for Thumb adds requires :lower0_7:,"
+                   " :lower8_15:, :upper0_7: or :upper8_15:");
+    break;
+  }
+  case ARM::tMOVi8: {
+    MCParsedAsmOperand &Op = *Operands[2];
+    if (isARMMCExpr(Op) && !isThumbI8Relocation(Op))
+      return Error(Op.getStartLoc(),
+                   "Immediate expression for Thumb movs requires :lower0_7:,"
+                   " :lower8_15:, :upper0_7: or :upper8_15:");
+    break;
+  }
   case ARM::HINT:
   case ARM::t2HINT: {
     unsigned Imm8 = Inst.getOperand(0).getImm();
     unsigned Pred = Inst.getOperand(1).getImm();
     // ESB is not predicable (pred must be AL). Without the RAS extension, this
     // behaves as any other unallocated hint.
     if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
       return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
case ARM::t2SUBspImm12: {
     Inst.addOperand(MCOperand::createReg(0)); // cc_out
     return true;
   }
   case ARM::tADDi8:
     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
     // to encoding T1 if <Rd> is omitted."
-    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
+    if (Inst.getOperand(3).isImm() &&
+        (unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
       Inst.setOpcode(ARM::tADDi3);
       return true;
     }
     break;
   case ARM::tSUBi8:
     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
       // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
       // - 19.
       {"fixup_arm_movt_hi16", 0, 20, 0},
       {"fixup_arm_movw_lo16", 0, 20, 0},
       {"fixup_t2_movt_hi16", 0, 20, 0},
       {"fixup_t2_movw_lo16", 0, 20, 0},
+      {"fixup_arm_thumb_upper_8_15", 0, 8, 0},
+      {"fixup_arm_thumb_upper_0_7", 0, 8, 0},
+      {"fixup_arm_thumb_lower_8_15", 0, 8, 0},
+      {"fixup_arm_thumb_lower_0_7", 0, 8, 0},
       {"fixup_arm_mod_imm", 0, 12, 0},
       {"fixup_t2_so_imm", 0, 26, 0},
       {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfcsel_else_target", 0, 32, 0},
       {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
       // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
       // - 19.
       {"fixup_arm_movt_hi16", 12, 20, 0},
       {"fixup_arm_movw_lo16", 12, 20, 0},
       {"fixup_t2_movt_hi16", 12, 20, 0},
       {"fixup_t2_movw_lo16", 12, 20, 0},
+      {"fixup_arm_thumb_upper_8_15", 24, 8, 0},
+      {"fixup_arm_thumb_upper_0_7", 24, 8, 0},
+      {"fixup_arm_thumb_lower_8_15", 24, 8, 0},
+      {"fixup_arm_thumb_lower_0_7", 24, 8, 0},
       {"fixup_arm_mod_imm", 20, 12, 0},
       {"fixup_t2_so_imm", 26, 6, 0},
       {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_bfcsel_else_target", 0, 32, 0},
       {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
case ARM::fixup_t2_movw_lo16: {
     unsigned Lo8 = Value & 0x0FF;
     // inst{19-16} = Hi4;
     // inst{26} = i;
     // inst{14-12} = Mid3;
     // inst{7-0} = Lo8;
     Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
     return swapHalfWords(Value, Endian == support::little);
   }
+  case ARM::fixup_arm_thumb_upper_8_15:
+    if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
+      return (Value & 0xff000000) >> 24;
+    return Value & 0xff;
+  case ARM::fixup_arm_thumb_upper_0_7:
+    if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
+      return (Value & 0x00ff0000) >> 16;
+    return Value & 0xff;
+  case ARM::fixup_arm_thumb_lower_8_15:
+    if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
+      return (Value & 0x0000ff00) >> 8;
+    return Value & 0xff;
+  case ARM::fixup_arm_thumb_lower_0_7:
+    return Value & 0x000000ff;
   case ARM::fixup_arm_ldst_pcrel_12:
     // ARM PC-relative values are offset by 8.
     Value -= 4;
     [[fallthrough]];
   case ARM::fixup_t2_ldst_pcrel_12:
     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     Value -= 4;
     [[fallthrough]];
static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
 
   case FK_Data_1:
   case ARM::fixup_arm_thumb_bcc:
   case ARM::fixup_arm_thumb_cp:
   case ARM::fixup_thumb_adr_pcrel_10:
+  case ARM::fixup_arm_thumb_upper_8_15:
+  case ARM::fixup_arm_thumb_upper_0_7:
+  case ARM::fixup_arm_thumb_lower_8_15:
+  case ARM::fixup_arm_thumb_lower_0_7:
     return 1;
 
   case FK_Data_2:
   case ARM::fixup_arm_thumb_br:
   case ARM::fixup_arm_thumb_cb:
   case ARM::fixup_arm_mod_imm:
     return 2;
 
static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
   case FK_Data_4:
     return 4;
 
   case ARM::fixup_arm_thumb_bcc:
   case ARM::fixup_arm_thumb_cp:
   case ARM::fixup_thumb_adr_pcrel_10:
   case ARM::fixup_arm_thumb_br:
   case ARM::fixup_arm_thumb_cb:
+  case ARM::fixup_arm_thumb_upper_8_15:
+  case ARM::fixup_arm_thumb_upper_0_7:
+  case ARM::fixup_arm_thumb_lower_8_15:
+  case ARM::fixup_arm_thumb_lower_0_7:
     // Instruction size is 2 bytes.
     return 2;
 
   case ARM::fixup_arm_pcrel_10_unscaled:
   case ARM::fixup_arm_ldst_pcrel_12:
   case ARM::fixup_arm_pcrel_10:
   case ARM::fixup_arm_pcrel_9:
   case ARM::fixup_arm_adr_pcrel_12:

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

if (IsPCRel) {
     case ARM::fixup_arm_movt_hi16:
       return ELF::R_ARM_MOVT_PREL;
     case ARM::fixup_arm_movw_lo16:
       return ELF::R_ARM_MOVW_PREL_NC;
     case ARM::fixup_t2_movt_hi16:
       return ELF::R_ARM_THM_MOVT_PREL;
     case ARM::fixup_t2_movw_lo16:
       return ELF::R_ARM_THM_MOVW_PREL_NC;
+    case ARM::fixup_arm_thumb_upper_8_15:
+      return ELF::R_ARM_THM_ALU_ABS_G3;
+    case ARM::fixup_arm_thumb_upper_0_7:
+      return ELF::R_ARM_THM_ALU_ABS_G2_NC;
+    case ARM::fixup_arm_thumb_lower_8_15:
+      return ELF::R_ARM_THM_ALU_ABS_G1_NC;
+    case ARM::fixup_arm_thumb_lower_0_7:
+      return ELF::R_ARM_THM_ALU_ABS_G0_NC;
     case ARM::fixup_arm_thumb_br:
       return ELF::R_ARM_THM_JUMP11;
     case ARM::fixup_arm_thumb_bcc:
       return ELF::R_ARM_THM_JUMP8;
     case ARM::fixup_arm_thumb_bl:
     case ARM::fixup_arm_thumb_blx:
       switch (Modifier) {
       case MCSymbolRefExpr::VK_TLSCALL:
default:
       Ctx.reportError(Fixup.getLoc(),
                       "invalid fixup for Thumb MOVW instruction");
       return ELF::R_ARM_NONE;
     case MCSymbolRefExpr::VK_None:
       return ELF::R_ARM_THM_MOVW_ABS_NC;
     case MCSymbolRefExpr::VK_ARM_SBREL:
       return ELF::R_ARM_THM_MOVW_BREL_NC;
     }
+
+  case ARM::fixup_arm_thumb_upper_8_15:
+    return ELF::R_ARM_THM_ALU_ABS_G3;
+  case ARM::fixup_arm_thumb_upper_0_7:
+    return ELF::R_ARM_THM_ALU_ABS_G2_NC;
+  case ARM::fixup_arm_thumb_lower_8_15:
+    return ELF::R_ARM_THM_ALU_ABS_G1_NC;
+  case ARM::fixup_arm_thumb_lower_0_7:
+    return ELF::R_ARM_THM_ALU_ABS_G0_NC;
   }
 }
 
 void ARMELFObjectWriter::addTargetSectionFlags(MCContext &Ctx,
                                                MCSectionELF &Sec) {
   // The mix of execute-only and non-execute-only at link time is
   // non-execute-only. To avoid the empty implicitly created .text
   // section from making the whole .text section non-execute-only, we

llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h

enum Fixups {
 
   // The next two are for the movt/movw pair
   // the 16bit imm field are split into imm{15-12} and imm{11-0}
   fixup_arm_movt_hi16, // :upper16:
   fixup_arm_movw_lo16, // :lower16:
   fixup_t2_movt_hi16,  // :upper16:
   fixup_t2_movw_lo16,  // :lower16:
 
+  // Fixup for Thumb movs (enc T1) and adds (enc T2) 8-bit immediate field (7-0)
+  fixup_arm_thumb_upper_8_15, // :upper8_15:
+  fixup_arm_thumb_upper_0_7,  // :upper0_7:
+  fixup_arm_thumb_lower_8_15, // :lower8_15:
+  fixup_arm_thumb_lower_0_7,  // :lower0_7:
+
   // Fixup for mod_imm
   fixup_arm_mod_imm,
 
   // Fixup for Thumb2 8-bit rotated operand
   fixup_t2_so_imm,
 
   // Fixups for Branch Future.
   fixup_bf_branch,

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  const MCSubtargetInfo &STI) const;
 
   /// getMachineOpValue - Return binary encoding of operand. If the machine
   /// operand requires relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
-  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
-  /// the specified operand. This is used for operands with :lower16: and
-  /// :upper16: prefixes.
-  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
-                               SmallVectorImpl<MCFixup> &Fixups,
-                               const MCSubtargetInfo &STI) const;
+  /// getHiLoImmOpValue - Return the encoding for either the hi / low 16-bit, or
+  /// high/middle-high/middle-low/low 8 bits of the specified operand. This is
+  /// used for operands with :lower16:, :upper16: :lower0_7:, :lower8_15:,
+  /// :higher0_7:, and :higher8_15: prefixes.
+  uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
 
   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
                               unsigned &Reg, unsigned &Imm,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
   /// BL branch target.
getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
   // {7-0}  = imm8
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
   unsigned Imm8 = MO1.getImm();
   return (Reg << 8) | Imm8;
 }
 
-uint32_t
-ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
+uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
   // {20-16} = imm{15-12}
   // {11-0}  = imm{11-0}
   const MCOperand &MO = MI.getOperand(OpIdx);
   if (MO.isImm())
-    // Hi / lo 16 bits already extracted during earlier passes.
+    // Hi / lo bits already extracted during earlier passes.
     return static_cast<unsigned>(MO.getImm());
 
-  // Handle :upper16: and :lower16: assembly prefixes.
+  // Handle :upper16:, :lower16:, :upper8_15:, :upper0_7:, :lower8_15:
+  // :lower0_7: assembly prefixes.
   const MCExpr *E = MO.getExpr();
   MCFixupKind Kind;
   if (E->getKind() == MCExpr::Target) {
     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
     E = ARM16Expr->getSubExpr();
 
     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
       const int64_t Value = MCE->getValue();
       if (Value > UINT32_MAX)
         report_fatal_error("constant value truncated (limited to 32-bit)");
 
       switch (ARM16Expr->getKind()) {
       case ARMMCExpr::VK_ARM_HI16:
         return (int32_t(Value) & 0xffff0000) >> 16;
       case ARMMCExpr::VK_ARM_LO16:
         return (int32_t(Value) & 0x0000ffff);
+
+      case ARMMCExpr::VK_ARM_HI_8_15:
+        return (int32_t(Value) & 0xff000000) >> 24;
+      case ARMMCExpr::VK_ARM_HI_0_7:
+        return (int32_t(Value) & 0x00ff0000) >> 16;
+      case ARMMCExpr::VK_ARM_LO_8_15:
+        return (int32_t(Value) & 0x0000ff00) >> 8;
+      case ARMMCExpr::VK_ARM_LO_0_7:
+        return (int32_t(Value) & 0x000000ff);
+
       default: llvm_unreachable("Unsupported ARMFixup");
       }
     }
 
     switch (ARM16Expr->getKind()) {
     default: llvm_unreachable("Unsupported ARMFixup");
     case ARMMCExpr::VK_ARM_HI16:
       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
                                       : ARM::fixup_arm_movt_hi16);
       break;
     case ARMMCExpr::VK_ARM_LO16:
       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
                                       : ARM::fixup_arm_movw_lo16);
       break;
+    case ARMMCExpr::VK_ARM_HI_8_15:
+      if (!isThumb(STI))
+        llvm_unreachable(":upper_8_15: not supported in Arm state");
+      Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_8_15);
+      break;
+    case ARMMCExpr::VK_ARM_HI_0_7:
+      if (!isThumb(STI))
+        llvm_unreachable(":upper_0_7: not supported in Arm state");
+      Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_0_7);
+      break;
+    case ARMMCExpr::VK_ARM_LO_8_15:
+      if (!isThumb(STI))
+        llvm_unreachable(":lower_8_15: not supported in Arm state");
+      Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_8_15);
+      break;
+    case ARMMCExpr::VK_ARM_LO_0_7:
+      if (!isThumb(STI))
+        llvm_unreachable(":lower_0_7: not supported in Arm state");
+      Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_0_7);
+      break;
     }
 
     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
     return 0;
   }
-  // If the expression doesn't have :upper16: or :lower16: on it,
-  // it's just a plain immediate expression, previously those evaluated to
-  // the lower 16 bits of the expression regardless of whether
-  // we have a movt or a movw, but that led to misleadingly results.
-  // This is disallowed in the AsmParser in validateInstruction()
-  // so this should never happen.
-  llvm_unreachable("expression without :upper16: or :lower16:");
+  // If the expression doesn't have :upper16:, :lower16: on it, it's just a
+  // plain immediate expression, previously those evaluated to the lower 16 bits
+  // of the expression regardless of whether we have a movt or a movw, but that
+  // led to misleadingly results.  This is disallowed in the AsmParser in
+  // validateInstruction() so this should never happen.  The same holds for
+  // thumb1 :upper8_15:, :upper0_7:, lower8_15: or :lower0_7: with movs or adds.
+  llvm_unreachable("expression without :upper16:, :lower16:, :upper8_15:,"
+                   ":upper0_7:, lower8_15: or :lower0_7:");
 }
 
 uint32_t ARMMCCodeEmitter::
 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
                     SmallVectorImpl<MCFixup> &Fixups,
                     const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx+1);

llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h

 #include "llvm/MC/MCExpr.h"
 
 namespace llvm {
 
 class ARMMCExpr : public MCTargetExpr {
 public:
   enum VariantKind {
     VK_ARM_None,
-    VK_ARM_HI16,  // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
-    VK_ARM_LO16   // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
+    VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
+    VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
+
+    VK_ARM_HI_8_15, // The R_ARM_THM_ALU_ABS_G3    relocation (:upper8_15: in
+                    // the .s file)
+    VK_ARM_HI_0_7,  // The R_ARM_THM_ALU_ABS_G2_NC relocation (:upper0_8: in the
+                    // .s file)
+    VK_ARM_LO_8_15, // The R_ARM_THM_ALU_ABS_G1_NC relocation (:lower8_15: in
+                    // the .s file)
+    VK_ARM_LO_0_7,  // The R_ARM_THM_ALU_ABS_G0_NC relocation (:lower0_7: in the
+                    // .s file)
   };
 
 private:
   const VariantKind Kind;
   const MCExpr *Expr;
 
   explicit ARMMCExpr(VariantKind Kind, const MCExpr *Expr)
       : Kind(Kind), Expr(Expr) {}
 
 public:
   /// @name Construction
   /// @{
 
   static const ARMMCExpr *create(VariantKind Kind, const MCExpr *Expr,
                                       MCContext &Ctx);
 
   static const ARMMCExpr *createUpper16(const MCExpr *Expr, MCContext &Ctx) {
     return create(VK_ARM_HI16, Expr, Ctx);
   }
 
   static const ARMMCExpr *createLower16(const MCExpr *Expr, MCContext &Ctx) {
     return create(VK_ARM_LO16, Expr, Ctx);
   }
 
+  static const ARMMCExpr *createUpper8_15(const MCExpr *Expr, MCContext &Ctx) {
+    return create(VK_ARM_HI_8_15, Expr, Ctx);
+  }
+
+  static const ARMMCExpr *createUpper0_7(const MCExpr *Expr, MCContext &Ctx) {
+    return create(VK_ARM_HI_0_7, Expr, Ctx);
+  }
+
+  static const ARMMCExpr *createLower8_15(const MCExpr *Expr, MCContext &Ctx) {
+    return create(VK_ARM_LO_8_15, Expr, Ctx);
+  }
+
+  static const ARMMCExpr *createLower0_7(const MCExpr *Expr, MCContext &Ctx) {
+    return create(VK_ARM_LO_0_7, Expr, Ctx);
+  }
+
   /// @}
   /// @name Accessors
   /// @{
 
   /// getOpcode - Get the kind of this expression.
   VariantKind getKind() const { return Kind; }
 
   /// getSubExpr - Get the child of this expression.

llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp

 ARMMCExpr::create(VariantKind Kind, const MCExpr *Expr,
                        MCContext &Ctx) {
   return new (Ctx) ARMMCExpr(Kind, Expr);
 }
 
 void ARMMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
   switch (Kind) {
   default: llvm_unreachable("Invalid kind!");
-  case VK_ARM_HI16: OS << ":upper16:"; break;
-  case VK_ARM_LO16: OS << ":lower16:"; break;
+  case VK_ARM_HI16:
+    OS << ":upper16:";
+    break;
+  case VK_ARM_LO16:
+    OS << ":lower16:";
+    break;
+  case VK_ARM_HI_8_15:
+    OS << ":upper8_15:";
+    break;
+  case VK_ARM_HI_0_7:
+    OS << ":upper0_7:";
+    break;
+  case VK_ARM_LO_8_15:
+    OS << ":lower8_15:";
+    break;
+  case VK_ARM_LO_0_7:
+    OS << ":lower0_7:";
+    break;
   }
 
   const MCExpr *Expr = getSubExpr();
   if (Expr->getKind() != MCExpr::SymbolRef)
     OS << '(';
   Expr->print(OS, MAI);
   if (Expr->getKind() != MCExpr::SymbolRef)
     OS << ')';
 }
 
 void ARMMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
   Streamer.visitUsedExpr(*getSubExpr());
 }

llvm/test/MC/ARM/negative-immediates-thumb1-fail.s

 # RUN: not llvm-mc -triple thumbv7 -mcpu=cortex-m0 %s 2>&1 | FileCheck %s
 
 .thumb
 
 ADDs r1, r0, #0xFFFFFFF5
 # CHECK: error: invalid instruction, any one of the following would fix this:
 # CHECK-DAG: note: instruction requires: thumb2
 # CHECK-DAG: note: invalid operand for instruction
 # CHECK-DAG: note: operand must be an immediate in the range [0,7]
 # CHECK-DAG: note: operand must be a register in range [r0, r7]
 
 ADDs r0, #0xFFFFFEFF
 # CHECK: error: invalid instruction, any one of the following would fix this:
 # CHECK-DAG: note: invalid operand for instruction
-# CHECK-DAG: note: operand must be an immediate in the range [0,255]
+# CHECK-DAG: note: operand must be an immediate in the range [0,255] or a relocatable expression
 
 SUBs r1, r0, #0xFFFFFFF5
 # CHECK: error: invalid instruction, any one of the following would fix this:
 # CHECK-DAG: note: invalid operand for instruction
 # CHECK-DAG: note: operand must be an immediate in the range [0,7]
 # CHECK-DAG: note: operand must be a register in range [r0, r7]
 
 SUBs r0, #0xFFFFFEFF

llvm/test/MC/ARM/thumb-8-bit-relocs.s

+@ RUN: llvm-mc -triple thumbv6m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+.syntax unified
+
+.type function,%function
+function:
+  bx lr
+
+.global external
+.type external,%function
+
+.type test,%function
+test:
+  movs r3, :upper8_15:function
+  adds r3, :upper0_7:function
+  adds r3, :lower8_15:function
+  adds r3, :lower0_7:function
+
+@ CHECK-LABEL: test:
+@ CHECK:  movs r3, :upper8_15:function
+@ CHECK:  adds r3, :upper0_7:function
+@ CHECK:  adds r3, :lower8_15:function
+@ CHECK:  adds r3, :lower0_7:function
+
+@ CHECK-RELOCATIONS: Relocations [
+@ CHECK-RELOCATIONS:     0x2 R_ARM_THM_ALU_ABS_G3 function
+@ CHECK-RELOCATIONS-NEXT:     0x4 R_ARM_THM_ALU_ABS_G2_NC function
+@ CHECK-RELOCATIONS-NEXT:     0x6 R_ARM_THM_ALU_ABS_G1_NC function
+@ CHECK-RELOCATIONS-NEXT:     0x8 R_ARM_THM_ALU_ABS_G0_NC function
+@ CHECK-RELOCATIONS: ]

llvm/test/MC/ARM/thumb-diagnostics.s

 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 @ CHECK-ERRORS: note: too many operands for instruction
 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 @ CHECK-ERRORS:         lsls r4, r5, #32
 @ CHECK-ERRORS:                      ^
 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 @ CHECK-ERRORS: note: too many operands for instruction
 
+@ Out of range immediates for MOVS/ADDS instruction.
+        movs r3, #-1
+        adds r3, #256
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:          ^
+@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:          ^
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:          ^
+@ CHECK-ERRORS-NEXT: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:          ^
+@ CHECK-ERRORS-NEXT: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:          ^
+
 @ Mismatched source/destination operands for MUL instruction.
         muls r1, r2, r3
 @ CHECK-ERRORS: error: destination register must match source register
 @ CHECK-ERRORS:         muls r1, r2, r3
 @ CHECK-ERRORS:              ^
 
 
 @ Out of range immediates for STR instruction.

llvm/test/MC/ARM/thumb-fixups.s

+@ RUN: llvm-mc -triple armv6m-unknown-unknown %s --show-encoding -o - | \
+@ RUN:   FileCheck %s
+
+    movs r3, :upper8_15:_foo
+    adds r3, :upper0_7:_foo
+    adds r3, :lower8_15:_foo
+    adds r3, :lower0_7:_foo
+
+@ CHECK:      movs    r3, :upper8_15:_foo             @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: adds    r3, :upper0_7:_foo              @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_0_7
+@ CHECK-NEXT: adds    r3, :lower8_15:_foo             @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_8_15
+@ CHECK-NEXT: adds    r3, :lower0_7:_foo              @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_0_7
+
+@ GNU syntax variants:
+    movs r3, #:upper8_15:#_foo
+    movs r3, #:upper8_15:_foo
+
+@ CHECK:      movs    r3, :upper8_15:_foo             @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: movs    r3, :upper8_15:_foo             @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15