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- Jan 22 2020, 8:14 AM (176 w, 1 d)
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Mar 15 2023
I'm not sure what is the right protocol for adding review comments to a long-submitted patch.
But, whilst thinking of adding float16 tests, I noticed 4 possible inconsistencies in float32 tests.
Aug 31 2021
Aug 26 2021
Aug 23 2021
Ping?
Ping?
Aug 5 2021
Aug 4 2021
I have moved some CHECK lines around in the test case, as suggested by reviewer.
Updated test case, actioning most of the review comments.
Aug 2 2021
Mar 11 2021
Sep 14 2020
Sep 10 2020
Ping.
Sep 8 2020
Sep 7 2020
Sep 4 2020
Reworded a comment. NFC.
Added comments to implementation of AArch64RegisterInfo::shouldCoalesce()
Sep 3 2020
Sep 2 2020
After review feedback: made some formatting changes in line with standard code style in LLVM.
Sep 1 2020
Abandoning this patch.
I overlooked that NegOk is fine for ADR, encoding A2.
I failed to look beyond encoding A1.
Aug 28 2020
Thanks for the feedback arsenm.
I've made all of the changes you suggested,
with 1 exception:
I have left in the IR for the declaration of @c.
Aug 26 2020
getPCOffset: added handling of LEApcrelJT
Aug 25 2020
Reinstated the change to pc offset.
This is necessary for ARM-state SO immediates.
Aug 20 2020
After review feedback, I removed the change to pc offset estimates from this patch.
This patch is now just about fixing the implementation of SO immediates.
Aug 18 2020
Fix order of arguments in 1 call to isCPEntryInRange()
Aug 17 2020
Aug 13 2020
Jul 30 2020
LGTM.
Jul 29 2020
MIR test further reduced and cleaned up after latest feedback.
• Could you make the MIR test smaller to include minimal instructions trigger the error, so that reviewers can review it easier?
Test was 130 lines. Now 25 lines.
Jul 28 2020
Please review the recent changes made since the last review comments.
Jul 22 2020
Added MIR test, as suggested.
Jul 21 2020
MIR test added, after useful feedback.
Note that this bug is not restricted to loading 16-bit floating point literals using VLDR.16.
The same fault is displayed loading 16-bit short literals using LDRH.
The significant phrase is the Align(PC, 4) part.
The calculated value of the offset depends on the alignment of the VLDR.16 instruction.
That is why the code section needs to be 4-byte aligned.
If the code section is 2-byte aligned and the linker places the section at a non-4-byte aligned address, the offset will point to a different address.
Jul 20 2020
Jul 17 2020
Jul 16 2020
Jul 9 2020
Yes, I used llc -stop-before=machine-cp mcp-dest-regs-no-dup.ll
to create the MIR test mcp-dest-regs-no-dup.mir
Jul 8 2020
Please review the recent changes made since the last review comments.
Jun 30 2020
If the definition is earlyclobber, will it ever reach hasOverlappingMultipleDef?
Jun 26 2020
Satisfy clang-format. NFC.