[DAGCombiner] Do not fold fadd (fmul x, y), (fmul x, y) -> fma x, y, (fmul x, y)

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
   bool CanReassociate =
       Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
   bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
                               Options.UnsafeFPMath || HasFMAD);
   // If the addition is not contractable, do not combine.
   if (!AllowFusionGlobally && !N->getFlags().hasAllowContract())
     return SDValue();
 
+  // Folding fadd (fmul x, y), (fmul x, y) -> fma x, y, (fmul x, y) is never
+  // beneficial. It does not reduce latency. It increases register pressure. It
+  // replaces an fadd with an fma which is a more complex instruction, so is
+  // likely to have a larger encoding, use more functional units, etc.
+  if (N0 == N1)
+    return SDValue();
+
   if (TLI.generateFMAsInMachineCombiner(VT, OptLevel))
     return SDValue();
 
   // Always prefer FMAD to FMA for precision.
   unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
   bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
 
   auto isFusedOp = [&](SDValue N) {

llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

; GCN-NEXT:    ; return to shader part epilog
   %a = fmul contract float %m, 2.0
   %r = fmul reassoc nsz float %a, %s
   ret float %r
 }
 
 define amdgpu_ps float @fma_vs_output_modifier_2(float %x) #0 {
 ; GCN-LABEL: fma_vs_output_modifier_2:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    v_mul_f32_e32 v1, v0, v0
-; GCN-NEXT:    v_fmac_f32_e32 v1, v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v0, v1
+; GCN-NEXT:    v_mul_f32_e64 v0, v0, v0 mul:2
 ; GCN-NEXT:    ; return to shader part epilog
   %m = fmul contract float %x, %x
   %a = fadd nsz contract float %m, %m
   ret float %a
 }
 
 ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
 declare float @llvm.maxnum.f32(float, float) #1