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Differential D146511

Precommit test for #61120
ClosedPublic

Authored by junaire on Mar 21 2023, 4:19 AM.

Details

Reviewers
RKSimon
Summary

Signed-off-by: Jun Zhang <jun@junz.org>

Diff Detail

Unit TestsFailed

TimeTest
70 msx64 debian > Flang.Examples::feature-list-class.f90
70 msx64 debian > Flang.Examples::feature-list-functions.f90

Event Timeline

junaire created this revision.Mar 21 2023, 4:19 AM
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junaire requested review of this revision.Mar 21 2023, 4:19 AM
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junaire added a child revision: D146512: [TLI] SimplifySetCC - Fold ~X >/< ~Y --> Y >/< X.Mar 21 2023, 4:20 AM
junaire added a reviewer: RKSimon.Mar 21 2023, 4:24 AM
Harbormaster completed remote builds in B220668: Diff 506908.Mar 21 2023, 5:09 AM
junaire updated this revision to Diff 506924.Mar 21 2023, 5:24 AM

Add more tests

Harbormaster completed remote builds in B220681: Diff 506924.Mar 21 2023, 6:22 AM
RKSimon added a comment.Mar 21 2023, 8:17 AM

Please can you add remaining icmp predicates - I think we still need sge/uge/eq/ne?

llvm/test/CodeGen/X86/setcc-combine.ll
503

maybe rename these to @cmp_not_????? to better explain the test

584

Please can you add at least one test with the constant on the LHS, to check that existing canonicalization will commute it.

640

<2 x i64> are interesting due to the weak support pre-SSE4 but it'd be good have some other vector types as well

junaire updated this revision to Diff 507264.Mar 22 2023, 1:31 AM
  1. Rename tests.
  2. Add more preds tests
  3. Use <3 x i64> for vector tests but also keep one for <2 x i64>
  4. Add commute tests
junaire marked 3 inline comments as done.Mar 22 2023, 1:36 AM
Harbormaster completed remote builds in B220946: Diff 507264.Mar 22 2023, 2:23 AM
RKSimon added a comment.Mar 22 2023, 4:57 AM

The <3 x i64> is interesting - but I meant other legal SSE vector types likes <16 x i8> / <8 x i16> / <4 x i32>

junaire updated this revision to Diff 507362.Mar 22 2023, 7:42 AM

Use legal SSE types <4 x i32>

Harbormaster completed remote builds in B221024: Diff 507362.Mar 22 2023, 8:36 AM
RKSimon accepted this revision.Mar 22 2023, 9:13 AM

LGTM - cheers

This revision is now accepted and ready to land.Mar 22 2023, 9:13 AM
junaire closed this revision.Mar 22 2023, 9:51 PM

Close it in https://reviews.llvm.org/rG1c420cd4e31f68fedca83b4d3a857a5519f4ce03

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
560 lines

Diff 507362

llvm/test/CodeGen/X86/setcc-combine.ll

Show First 20 Lines • Show All 493 Lines • ▼ Show 20 Lines
; CHECK-NEXT: andnpd %xmm1, %xmm2 ; CHECK-NEXT: andnpd %xmm1, %xmm2
; CHECK-NEXT: orpd %xmm2, %xmm0 ; CHECK-NEXT: orpd %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%neg = fneg double %x %neg = fneg double %x
%cmp = fcmp ogt double %x, 1.0 %cmp = fcmp ogt double %x, 1.0
%r = select i1 %cmp, double %x, double %neg %r = select i1 %cmp, double %x, double %neg
ret double %r ret double %r
} }
define i64 @cmp_sgt_not(i64 %a, i64 %b) {
RKSimonUnsubmitted
Done
ReplyInline Actions

maybe rename these to @cmp_not_????? to better explain the test

RKSimon: maybe rename these to @cmp_not_????? to better explain the test
; CHECK-LABEL: cmp_sgt_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: setg %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp sgt i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_sgt_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_sgt_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $43, %rdi
; CHECK-NEXT: setge %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp sgt i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_sgt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmp_sgt_not_with_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
; CHECK-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp sgt <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_ugt_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_ugt_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp ugt i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_ugt_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_ugt_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $43, %rdi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp ugt i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_ugt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: cmp_ugt_not_with_vec:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
; SSE2-NEXT: pxor %xmm2, %xmm1
; SSE2-NEXT: pxor %xmm2, %xmm0
RKSimonUnsubmitted
Done
ReplyInline Actions

Please can you add at least one test with the constant on the LHS, to check that existing canonicalization will commute it.

RKSimon: Please can you add at least one test with the constant on the LHS, to check that existing…
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: cmp_ugt_not_with_vec:
; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm2, %xmm1
; SSE41-NEXT: pminud %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp ugt <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_sge_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_sge_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: setge %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp sge i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_sge_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_sge_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $42, %rdi
; CHECK-NEXT: setge %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp sge i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_sge_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: cmp_sge_not_with_vec:
; SSE2: # %bb.0:
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
RKSimonUnsubmitted
Done
ReplyInline Actions

<2 x i64> are interesting due to the weak support pre-SSE4 but it'd be good have some other vector types as well

RKSimon: <2 x i64> are interesting due to the weak support pre-SSE4 but it'd be good have some other…
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: cmp_sge_not_with_vec:
; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pmaxud %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
; SSE41-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp uge <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_uge_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_uge_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp uge i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_uge_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_uge_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $42, %rdi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp uge i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_uge_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: cmp_uge_not_with_vec:
; SSE2: # %bb.0:
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: cmp_uge_not_with_vec:
; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pmaxud %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
; SSE41-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp uge <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_sle_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_sle_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: setle %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp sle i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_sle_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_sle_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $43, %rdi
; CHECK-NEXT: setl %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp sle i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_sle_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmp_sle_not_with_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp sle <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_slt_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_slt_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: setl %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp slt i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_slt_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_slt_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $42, %rdi
; CHECK-NEXT: setl %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp slt i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_slt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmp_slt_not_with_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp slt <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_ult_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_ult_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp ult i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_ult_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_ult_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addq $42, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp ult i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_ult_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: cmp_ult_not_with_vec:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: cmp_ult_not_with_vec:
; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm2, %xmm1
; SSE41-NEXT: pmaxud %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp ult <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_ule_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_ule_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rdi, %rsi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp ule i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_ule_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_ule_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $43, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp ule i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_ule_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: cmp_ule_not_with_vec:
; SSE2: # %bb.0:
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
; SSE2-NEXT: pxor %xmm3, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: cmp_ule_not_with_vec:
; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pminud %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
; SSE41-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp ule <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_eq_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_eq_not:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: sete %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp eq i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_eq_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_eq_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $-43, %rdi
; CHECK-NEXT: sete %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp eq i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_eq_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmp_eq_not_with_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp eq <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_ne_not(i64 %a, i64 %b) {
; CHECK-LABEL: cmp_ne_not:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rsi, %rdi
; CHECK-NEXT: setne %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp ne i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_ne_not_with_constant(i64 %a) {
; CHECK-LABEL: cmp_ne_not_with_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $-43, %rdi
; CHECK-NEXT: setne %al
; CHECK-NEXT: negq %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp ne i64 %na, 42
%r = sext i1 %c to i64
ret i64 %r
}
define <4 x i32> @cmp_ne_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmp_ne_not_with_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq
%na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = icmp ne <4 x i32> %na, %nb
%r = sext <4 x i1> %c to <4 x i32>
ret <4 x i32> %r
}
define i64 @cmp_uge_not_commute(i64 %b, i64 %a) {
; CHECK-LABEL: cmp_uge_not_commute:
; CHECK: # %bb.0:
; CHECK-NEXT: notq %rsi
; CHECK-NEXT: notq %rdi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq %rdi, %rsi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%nb = xor i64 %b, -1
%c = icmp uge i64 %na, %nb
%r = sext i1 %c to i64
ret i64 %r
}
define i64 @cmp_ult_not_with_constant_commute(i64 %a) {
; CHECK-LABEL: cmp_ult_not_with_constant_commute:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $43, %rdi
; CHECK-NEXT: adcq $-1, %rax
; CHECK-NEXT: retq
%na = xor i64 %a, -1
%c = icmp ult i64 42, %a
%r = sext i1 %c to i64
ret i64 %r
}
define <2 x i64> @cmp_uge_not_with_vec2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmp_uge_not_with_vec2xi64:
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292159,9223372034707292159]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq
%na = xor <2 x i64> %a, <i64 -1, i64 -1>
%nb = xor <2 x i64> %b, <i64 -1, i64 -1>
%c = icmp uge <2 x i64> %na, %nb
%r = sext <2 x i1> %c to <2 x i64>
ret <2 x i64> %r
}