[TLI] SimplifySetCC - Fold ~X >/< ~Y --> Y >/< X

[junaire]

Summary

Fixes: https://github.com/llvm/llvm-project/issues/61120

Signed-off-by: Jun Zhang <[e-mail]>

[junaire]

Looks like the patch doesn't work for vectors, do you have any insights about it? @RKSimon

[RKSimon]

Thanks for taking a look at this!

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4979

Take a look at https://github.com/llvm/llvm-project/blob/3a8f161a3401edeb58e018e2d389dd2413a6417f/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp#L6501

This shows its safe to handle all icmp predicates - and handles cases where one operand is a constant which can be constant folded

4984

You should be able to use llvm::isBitwiseNot to detect this

[junaire]

1. Use llvm::isBitwiseNot to simplify code.
2. Support X > ~C --> X < ~C

[junaire]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4979

Thanks for the review! However, I'm unsure what is the right way to say 'all icmp predicates' and I'm worried about why vectors don't fold correctly.

If I run llc -mcpu=btver2 test.ll to:

define <2 x i64> @cmp_sgt_not(<2 x i64> %a, <2 x i64> %b) {                                                                                                                                                         %na = xor <2 x i64> %a, <i64 -1, i64 -1>                                                                                                                                                                          %nb = xor <2 x i64> %b, <i64 -1, i64 -1>                                                                                                                                                                          %c = icmp sgt <2 x i64> %na, %nb                                                                                                                                                                                  %r = sext <2 x i1> %c to <2 x i64>                                                                                                                                                                                ret <2 x i64> %r                                                                                                                                                                                                }

It does fold to:

vpcmpgtq        %xmm0, %xmm1, %xmm0                                                                                                                                                                               retq

But for ule it doesn't work as well.

Let me know if you think it's necessary to add more tests for the remaining preds!

[RKSimon]

What regressions are you seeing for ULE vector cases with this fold? Manual optimization looks OK - https://llvm.godbolt.org/z/n9ezae5En

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4982

N0.getValueType().isInteger() should be implied from the CodeCode - I don't think you need it but make it an assert if you're worried

[junaire]

Make N0.getValueType().isInteger() an assert.

[junaire]

In D146512#4209812, @RKSimon wrote:

What regressions are you seeing for ULE vector cases with this fold? Manual optimization looks OK - https://llvm.godbolt.org/z/n9ezae5En

I may misunderstand something. I was expected it could folded like https://llvm.godbolt.org/z/ebfj4MoKr

[junaire]

Revert 'Make N0.getValueType().isInteger() an assert.' since it causes a lot of crashes in the tests.

[junaire]

Make clang-format happy

[junaire]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4982

Looks like it's a must, without the check I saw lots of crashes in the tests. For example:

llc: llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4985: llvm::SDValue llvm::TargetLowering::SimplifySetCC(llvm::EVT, llvm::SDValue, llvm::SDValue, ISD::CondCode, bool, llvm::TargetLowering::DAGCombinerInfo &, const llvm::SDLoc &) const: Assertion `N0.getValueType().isInteger() && "N0 is not an ineger type"' failed.
... Crashes ....
llvm-project/llvm/test/CodeGen/X86/machine-combiner.ll:694:14: error: SSE-LABEL: expected string not found in input
...

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4987

Can you replace this with llvm::isConstantIntBuildVectorOrConstantInt(N1) to support vectors as well?

[junaire]

Use SelectionDAG::isConstantIntBuildVectorOrConstantInt to support vector constant.

[RKSimon]

LGTM - cheers!

[junaire]

In D146512#4213404, @RKSimon wrote:

LGTM - cheers!

Thanks for the review!

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (N0 == N1) {
     // if it is not already.
     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
     if (NewCond != Cond &&
         (DCI.isBeforeLegalizeOps() ||
                             isCondCodeLegal(NewCond, N0.getSimpleValueType())))
       return DAG.getSetCC(dl, VT, N0, N1, NewCond);
   }
 
+  // ~X > ~Y --> Y > X
+  // ~X < ~Y --> Y < X
+  // ~X < C --> X > ~C
+  // ~X > C --> X < ~C
+  if ((isSignedIntSetCC(Cond) || isUnsignedIntSetCC(Cond)) &&
+      N0.getValueType().isInteger()) {
+    if (isBitwiseNot(N0)) {
+      if (isBitwiseNot(N1))
+        return DAG.getSetCC(dl, VT, N1.getOperand(0), N0.getOperand(0), Cond);
+
+      if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
+        SDValue Not = DAG.getNOT(dl, N1, OpVT);
+        return DAG.getSetCC(dl, VT, Not, N0.getOperand(0), Cond);
+      }
+    }
+  }
+
   if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
       N0.getValueType().isInteger()) {
     if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
         N0.getOpcode() == ISD::XOR) {
       // Simplify (X+Y) == (X+Z) -->  Y == Z
       if (N0.getOpcode() == N1.getOpcode()) {
         if (N0.getOperand(0) == N1.getOperand(0))
           return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);

llvm/test/CodeGen/X86/cmov.ll

; CHECK-NEXT:    retq
   %4 = icmp sgt i64 %0, -2147483649
   %5 = select i1 %4, i64 %1, i64 %2
   ret i64 %5
 }
 
 define i32 @smin(i32 %x) {
 ; CHECK-LABEL: smin:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notl %edi
 ; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    notl %edi
 ; CHECK-NEXT:    movl $-1, %eax
-; CHECK-NEXT:    cmovsl %edi, %eax
+; CHECK-NEXT:    cmovnsl %edi, %eax
 ; CHECK-NEXT:    retq
   %not_x = xor i32 %x, -1
   %1 = icmp slt i32 %not_x, -1
   %sel = select i1 %1, i32 %not_x, i32 -1
   ret i32 %sel
 }
 
 define i32 @pr47049_1(i32 %0) {

llvm/test/CodeGen/X86/setcc-combine.ll

; CHECK-NEXT:    retq
   %cmp = fcmp ogt double %x, 1.0
   %r = select i1 %cmp, double %x, double %neg
   ret double %r
 }
 
 define i64 @cmp_sgt_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_sgt_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmpq %rdi, %rsi
 ; CHECK-NEXT:    setg %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp sgt i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_sgt_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_sgt_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $43, %rdi
-; CHECK-NEXT:    setge %al
+; CHECK-NEXT:    cmpq $-43, %rdi
+; CHECK-NEXT:    setl %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp sgt i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_sgt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: cmp_sgt_not_with_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pcmpeqd %xmm2, %xmm2
-; CHECK-NEXT:    pxor %xmm2, %xmm0
-; CHECK-NEXT:    pxor %xmm2, %xmm1
-; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT:    pcmpgtd %xmm0, %xmm1
+; CHECK-NEXT:    movdqa %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp sgt <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
; CHECK-NEXT:    retq
   %c = icmp ugt i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_ugt_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_ugt_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $43, %rdi
-; CHECK-NEXT:    adcq $-1, %rax
+; CHECK-NEXT:    cmpq $-43, %rdi
+; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp ugt i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_ugt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: cmp_ugt_not_with_vec:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
-; SSE2-NEXT:    pxor %xmm2, %xmm1
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
 ; SSE2-NEXT:    pxor %xmm2, %xmm0
-; SSE2-NEXT:    pcmpgtd %xmm1, %xmm0
+; SSE2-NEXT:    pxor %xmm1, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
+; SSE2-NEXT:    movdqa %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: cmp_ugt_not_with_vec:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT:    pxor %xmm2, %xmm0
-; SSE41-NEXT:    pxor %xmm2, %xmm1
-; SSE41-NEXT:    pminud %xmm0, %xmm1
+; SSE41-NEXT:    pminud %xmm1, %xmm0
 ; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
-; SSE41-NEXT:    pxor %xmm2, %xmm0
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm1
+; SSE41-NEXT:    pxor %xmm1, %xmm0
 ; SSE41-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp ugt <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_sge_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_sge_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmpq %rdi, %rsi
 ; CHECK-NEXT:    setge %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp sge i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_sge_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_sge_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $42, %rdi
-; CHECK-NEXT:    setge %al
+; CHECK-NEXT:    cmpq $-42, %rdi
+; CHECK-NEXT:    setl %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp sge i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_sge_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: cmp_sge_not_with_vec:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pcmpeqd %xmm3, %xmm3
-; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT:    pxor %xmm2, %xmm1
 ; SSE2-NEXT:    pxor %xmm2, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm2
-; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
-; SSE2-NEXT:    pxor %xmm3, %xmm2
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm0
+; SSE2-NEXT:    pcmpeqd %xmm1, %xmm1
+; SSE2-NEXT:    pxor %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: cmp_sge_not_with_vec:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT:    pxor %xmm2, %xmm0
-; SSE41-NEXT:    pxor %xmm1, %xmm2
-; SSE41-NEXT:    pmaxud %xmm0, %xmm2
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm0
+; SSE41-NEXT:    pmaxud %xmm1, %xmm0
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
 ; SSE41-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp uge <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_uge_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_uge_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmpq %rdi, %rsi
 ; CHECK-NEXT:    adcq $-1, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp uge i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_uge_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_uge_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $42, %rdi
-; CHECK-NEXT:    adcq $-1, %rax
+; CHECK-NEXT:    cmpq $-42, %rdi
+; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp uge i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_uge_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: cmp_uge_not_with_vec:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pcmpeqd %xmm3, %xmm3
-; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT:    pxor %xmm2, %xmm1
 ; SSE2-NEXT:    pxor %xmm2, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm2
-; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
-; SSE2-NEXT:    pxor %xmm3, %xmm2
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm0
+; SSE2-NEXT:    pcmpeqd %xmm1, %xmm1
+; SSE2-NEXT:    pxor %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: cmp_uge_not_with_vec:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT:    pxor %xmm2, %xmm0
-; SSE41-NEXT:    pxor %xmm1, %xmm2
-; SSE41-NEXT:    pmaxud %xmm0, %xmm2
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm0
+; SSE41-NEXT:    pmaxud %xmm1, %xmm0
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
 ; SSE41-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp uge <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_sle_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_sle_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmpq %rdi, %rsi
 ; CHECK-NEXT:    setle %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp sle i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_sle_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_sle_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $43, %rdi
-; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    cmpq $-43, %rdi
+; CHECK-NEXT:    setge %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp sle i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_sle_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: cmp_sle_not_with_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pcmpeqd %xmm2, %xmm2
-; CHECK-NEXT:    pxor %xmm2, %xmm0
-; CHECK-NEXT:    pxor %xmm2, %xmm1
-; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
-; CHECK-NEXT:    pxor %xmm2, %xmm0
+; CHECK-NEXT:    pcmpgtd %xmm0, %xmm1
+; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
+; CHECK-NEXT:    pxor %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp sle <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_slt_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_slt_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmpq %rdi, %rsi
 ; CHECK-NEXT:    setl %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp slt i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_slt_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_slt_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $42, %rdi
-; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    cmpq $-42, %rdi
+; CHECK-NEXT:    setge %al
 ; CHECK-NEXT:    negq %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp slt i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_slt_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: cmp_slt_not_with_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pcmpeqd %xmm2, %xmm2
-; CHECK-NEXT:    pxor %xmm2, %xmm0
-; CHECK-NEXT:    pxor %xmm1, %xmm2
-; CHECK-NEXT:    pcmpgtd %xmm0, %xmm2
-; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp slt <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
; CHECK-NEXT:    retq
   %c = icmp ult i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_ult_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: cmp_ult_not_with_vec:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT:    pxor %xmm2, %xmm1
 ; SSE2-NEXT:    pxor %xmm2, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm2
-; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
-; SSE2-NEXT:    movdqa %xmm2, %xmm0
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: cmp_ult_not_with_vec:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT:    pxor %xmm2, %xmm0
-; SSE41-NEXT:    pxor %xmm2, %xmm1
-; SSE41-NEXT:    pmaxud %xmm0, %xmm1
+; SSE41-NEXT:    pmaxud %xmm1, %xmm0
 ; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
-; SSE41-NEXT:    pxor %xmm2, %xmm0
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm1
+; SSE41-NEXT:    pxor %xmm1, %xmm0
 ; SSE41-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp ult <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_ule_not(i64 %a, i64 %b) {
 ; CHECK-LABEL: cmp_ule_not:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
-; CHECK-NEXT:    notq %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rdi, %rsi
+; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    adcq $-1, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp ule i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define i64 @cmp_ule_not_with_constant(i64 %a) {
 ; CHECK-LABEL: cmp_ule_not_with_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq $43, %rdi
-; CHECK-NEXT:    sbbq %rax, %rax
+; CHECK-NEXT:    cmpq $-43, %rdi
+; CHECK-NEXT:    adcq $-1, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %c = icmp ule i64 %na, 42
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <4 x i32> @cmp_ule_not_with_vec(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-LABEL: cmp_ule_not_with_vec:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [2147483647,2147483647,2147483647,2147483647]
-; SSE2-NEXT:    pxor %xmm3, %xmm1
-; SSE2-NEXT:    pxor %xmm3, %xmm0
-; SSE2-NEXT:    pcmpgtd %xmm1, %xmm0
+; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE2-NEXT:    pxor %xmm2, %xmm0
+; SSE2-NEXT:    pxor %xmm1, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
+; SSE2-NEXT:    pcmpeqd %xmm0, %xmm0
 ; SSE2-NEXT:    pxor %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: cmp_ule_not_with_vec:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT:    pxor %xmm2, %xmm0
-; SSE41-NEXT:    pxor %xmm1, %xmm2
-; SSE41-NEXT:    pminud %xmm0, %xmm2
-; SSE41-NEXT:    pcmpeqd %xmm2, %xmm0
+; SSE41-NEXT:    pminud %xmm1, %xmm0
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
 ; SSE41-NEXT:    retq
   %na = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %nb = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = icmp ule <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
; CHECK-NEXT:    retq
   %c = icmp ne <4 x i32> %na, %nb
   %r = sext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %r
 }
 
 define i64 @cmp_uge_not_commute(i64 %b, i64 %a) {
 ; CHECK-LABEL: cmp_uge_not_commute:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    notq %rsi
-; CHECK-NEXT:    notq %rdi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq %rdi, %rsi
+; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    adcq $-1, %rax
 ; CHECK-NEXT:    retq
   %na = xor i64 %a, -1
   %nb = xor i64 %b, -1
   %c = icmp uge i64 %na, %nb
   %r = sext i1 %c to i64
   ret i64 %r
 }
; CHECK-NEXT:    retq
   %c = icmp ult i64 42, %a
   %r = sext i1 %c to i64
   ret i64 %r
 }
 
 define <2 x i64> @cmp_uge_not_with_vec2xi64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: cmp_uge_not_with_vec2xi64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movdqa {{.*#+}} xmm2 = [9223372034707292159,9223372034707292159]
-; CHECK-NEXT:    pxor %xmm2, %xmm0
+; CHECK-NEXT:    movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
 ; CHECK-NEXT:    pxor %xmm2, %xmm1
-; CHECK-NEXT:    movdqa %xmm1, %xmm2
-; CHECK-NEXT:    pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT:    pxor %xmm2, %xmm0
+; CHECK-NEXT:    movdqa %xmm0, %xmm2
+; CHECK-NEXT:    pcmpgtd %xmm1, %xmm2
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
-; CHECK-NEXT:    pcmpeqd %xmm0, %xmm1
-; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm0
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; CHECK-NEXT:    pand %xmm3, %xmm0
 ; CHECK-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
 ; CHECK-NEXT:    por %xmm0, %xmm1
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    pxor %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %na = xor <2 x i64> %a, <i64 -1, i64 -1>
   %nb = xor <2 x i64> %b, <i64 -1, i64 -1>
   %c = icmp uge <2 x i64> %na, %nb
   %r = sext <2 x i1> %c to <2 x i64>
   ret <2 x i64> %r
 }