[RISCV] Remove isCall instruction flag from JAL/JALR

[jobnoorman]

Summary

As far as I can tell, the instruction flags set in the various
RISCVInstrInfo*.td files are always under-approximations. That is,
something like isTerminator will only be set for opcodes that are
*always* terminators.

The exception seems to be isCall; this is set for JAL/JALR while these
instruction are not always calls. This patch proposes to remove isCall
from JAL/JALR for consistency.

A follow-up patch will add more detailed analysis of some instruction
properties based on MCInstrAnalysis.

[craig.topper]

LGTM

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 let isReMaterializable = 1, isAsCheapAsAMove = 1,
     IsSignExtendingOpW = 1 in
 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
                   "lui", "$rd, $imm20">, Sched<[WriteIALU]>;
 
 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
                     "auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
 
-let isCall = 1 in
 def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
                   "jal", "$rd, $imm20">, Sched<[WriteJal]>;
 
-let isCall = 1 in
 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
                    (ins GPR:$rs1, simm12:$imm12),
                    "jalr", "$rd, ${imm12}(${rs1})">,
            Sched<[WriteJalr, ReadJalr]>;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 def BEQ  : BranchCC_rri<0b000, "beq">;
 def BNE  : BranchCC_rri<0b001, "bne">;