[Xtensa] Codegen support for memory operations

[andreisfr]

Summary

Implement codegen for address operands of the load operations
L8UI/L16UI/L16SI/L32I and store operations S8I/S16I/S32I.

[andreisfr]

Minor code formatting.

[myhsu]

I just realized that this patch along with nearly all other patches in the series don't have tests, what's your plan on that?
Also, it might be a good idea to add more reviewers, potentially backend maintainers.

[andreisfr]

Hi @myhsu, thank you for your comment. We have plans to add also some tests to the current functionality.

[aykevl]

@andreisfr I believe every patch should stand on its own and have tests for its own functionality. Even if the backend won't be fully functional without all parts included, each commit should still have the ability to be tested as it is added.

[andreisfr]

Added minimal support for stack operations like storeRegToStackSlot/loadRegFromStackSlot/eliminateFrameIndex functions to make possible implement different tests. Added test for load/store operations on stack.

[arsenm]

Basically lgtm with some nits

llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp

57

s/is not/are not/

Can you make this a DiagnosticInfoUnsupported instead?

69–83

Move this to a separate util function

llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

67–68 ↗

(On Diff #544644)

define and init on same line?

80 ↗

(On Diff #544644)

init on definition

86–100 ↗

(On Diff #544644)

Move to separate util function

[arsenm]

llvm/test/CodeGen/Xtensa/stack-access.ll

21–22 ↗

(On Diff #544644)

weird indent

[andreisfr]

Updated according latest changes in main branch and reviewers comments.

llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp

StringRef getPassName() const override {
     return "Xtensa DAG->DAG Pattern Instruction Selection";
   }
 
   // Override SelectionDAGISel.
   void Select(SDNode *Node) override;
 
   bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
                         int Scale) {
-    report_fatal_error("MemReg address is not implemented yet");
+    EVT ValTy = Addr.getValueType();
+
+    // if Address is FI, get the TargetFrameIndex.
+    if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
+      Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+      Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
+
+      return true;
+    }
+
+    if (TM.isPositionIndependent())
+      report_fatal_error("PIC relocations is not supported");
+
+    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
+         Addr.getOpcode() == ISD::TargetGlobalAddress))
+      return false;
+
+    // Addresses of the form FI+const or FI|const
+    bool Valid = false;
+    if (CurDAG->isBaseWithConstantOffset(Addr)) {
+      ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+      int64_t OffsetVal = CN->getSExtValue();
+
+      switch (Scale) {
+      case 1:
+        Valid = (OffsetVal >= 0 && OffsetVal <= 255);
+        break;
+      case 2:
+        Valid =
+            (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);
+        break;
+      case 4:
+        Valid =
+            (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);
+        break;
+      default:
+        break;
+      }
+
+      if (Valid) {
+        // If the first operand is a FI, get the TargetFI Node
+        if (FrameIndexSDNode *FIN =
+                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
+          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+        else
+          Base = Addr.getOperand(0);
+
+        Offset =
+            CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy);
+        return true;
+      }
+    }
+
+    // Last case
+    Base = Addr;
+    Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
     return true;
   }
 
   bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) {
     return selectMemRegAddr(Addr, Base, Offset, 1);
   }
 
   bool selectMemRegAddrISH2(SDValue Addr, SDValue &Base, SDValue &Offset) {

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
   setStackPointerRegisterToSaveRestore(Xtensa::SP);
 
   setSchedulingPreference(Sched::RegPressure);
   
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent);
 
   setMinFunctionAlignment(Align(4));
   
+  // No sign extend instructions for i1
+  for (MVT VT : MVT::integer_valuetypes()) {
+    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
+    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
+    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
+  }
+
   // Compute derived properties from the register classes
   computeRegisterProperties(STI.getRegisterInfo());
 }
 
 //===----------------------------------------------------------------------===//
 // Calling conventions
 //===----------------------------------------------------------------------===//