[Xtensa] Implement load pseudo operations and patterns.

[andreisfr]

Summary

Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

[maciejcz]

The code conforms to ISA. One "optimization" remark: pseudo-instruction might be replaced by tablegen pattern in this case.

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

1141

This snippet can be represented as Tablegen pattern below.
If that is true, we don't have to use pseudo instruction in this case.

def : Pat<(i32 (sextloadi8  addr_ish1:$addr)), 
          (SRAI 
            (SLLI 
              (L8UI addr_ish1:$addr), 
              (i32 24)),
            (i32 24))>;

[arsenm]

Tests

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
 
   MI.eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }
 
 MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
     MachineInstr &MI, MachineBasicBlock *MBB) const {
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  MachineFunction *MF = MBB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
   DebugLoc DL = MI.getDebugLoc();
 
   switch (MI.getOpcode()) {
   case Xtensa::SELECT:
     return emitSelectCC(MI, MBB);
 
   case Xtensa::SLL_P: {
     MachineOperand &R = MI.getOperand(0);
case Xtensa::SRL_P: {
     MachineOperand &SA = MI.getOperand(2);
 
     BuildMI(*MBB, MI, DL, TII.get(Xtensa::SSR)).addReg(SA.getReg());
     BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRL), R.getReg()).addReg(T.getReg());
     MI.eraseFromParent();
     return MBB;
   }
 
+  case Xtensa::L8I_P: {
+    MachineOperand &R = MI.getOperand(0);
+    MachineOperand &Op1 = MI.getOperand(1);
+    MachineOperand &Op2 = MI.getOperand(2);
+
+    const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+    unsigned R1 = MRI.createVirtualRegister(RC);
+
+    BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2);
+
+    unsigned R2 = MRI.createVirtualRegister(RC);
+    BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24);
+    BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg())
+        .addReg(R2)
+        .addImm(24);
+    MI.eraseFromParent();
+    return MBB;
+  }
   default:
     llvm_unreachable("Unexpected instr type to insert");
   }
 }

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

def LEA_ADD : RRI8_Inst<0x02, (outs AR:$t), (ins mem32:$addr),
     bits<12> addr;
 
     let r = 0x0C;
     let imm8{7-0} = addr{11-4};
     let s{3-0} = addr{3-0};
   }
 }
 
+// Xtensa missed L8I load operation, use pseudo operation
+let usesCustomInserter = 1 in
+def L8I_P: Pseudo<(outs AR:$t), (ins mem8:$addr),
+               "!L8I_P $t, $addr",
+                [(set AR:$t, (sextloadi8
+        addr_ish1:$addr))]>;
+
+//extending loads
+def : Pat<(i32 (extloadi1  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
+
 //===----------------------------------------------------------------------===//
 // Conditional branch instructions
 //===----------------------------------------------------------------------===//
 let isBranch = 1, isTerminator = 1 in {
   class Branch_RR<bits<4> oper, string instrAsm, CondCode CC>
       : RRI8_Inst<0x07, (outs),
                  (ins AR:$s, AR:$t, brtarget:$target),
                   instrAsm#"\t$s, $t, $target",

llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

bool XtensaRegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
   Offset = SPOffset + (int64_t)StackSize;
   Offset += MI.getOperand(OpNo + 1).getImm();
 
   LLVM_DEBUG(errs() << "Offset     : " << Offset << "\n"
                     << "<--------->\n");
 
   bool Valid = false;
   switch (MI.getOpcode()) {
+  case Xtensa::L8I_P:
   case Xtensa::L8UI:
   case Xtensa::S8I:
     Valid = (Offset >= 0 && Offset <= 255);
     break;
   case Xtensa::L16SI:
   case Xtensa::L16UI:
   case Xtensa::S16I:
     Valid = (Offset >= 0 && Offset <= 510);