[Xtensa] Implement volatile load/store.

[andreisfr]

Summary

Implement volatile load/store from/to volatile memory location.

[arsenm]

Missing tests

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

1475

It's not currently guaranteed that you have a memory operand

1497

It's not currently guaranteed that you have a memory operand

[arsenm]

Needs tests

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
   case Xtensa::L8I_P: {
     MachineOperand &R = MI.getOperand(0);
     MachineOperand &Op1 = MI.getOperand(1);
     MachineOperand &Op2 = MI.getOperand(2);
 
     const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
     unsigned R1 = MRI.createVirtualRegister(RC);
 
+    const MachineMemOperand &MMO = **MI.memoperands_begin();
+    if (MMO.isVolatile()) {
+      BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW));
+    }
+
     BuildMI(*MBB, MI, DL, TII.get(Xtensa::L8UI), R1).add(Op1).add(Op2);
 
     unsigned R2 = MRI.createVirtualRegister(RC);
     BuildMI(*MBB, MI, DL, TII.get(Xtensa::SLLI), R2).addReg(R1).addImm(24);
     BuildMI(*MBB, MI, DL, TII.get(Xtensa::SRAI), R.getReg())
         .addReg(R2)
         .addImm(24);
     MI.eraseFromParent();
     return MBB;
   }
+  case Xtensa::S8I:
+  case Xtensa::S16I:
+  case Xtensa::S32I:
+  case Xtensa::L8UI:
+  case Xtensa::L16SI:
+  case Xtensa::L16UI:
+  case Xtensa::L32I: {
+    const MachineMemOperand &MMO = **MI.memoperands_begin();
+    if (MMO.isVolatile()) {
+      BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW));
+    }
+    return MBB;
+  }
   default:
     llvm_unreachable("Unexpected instr type to insert");
   }
 }

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

def SRL_P : Pseudo<(outs AR:$r), (ins AR:$t, AR:$sa),
                     [(set AR:$r, (srl AR:$t, AR:$sa))]>;
 }
 
 //===----------------------------------------------------------------------===//
 // Load and store instructions
 //===----------------------------------------------------------------------===//
 
 // Load instructions
-let mayLoad = 1 in {
+let mayLoad = 1, usesCustomInserter = 1 in {
 
   class Load_RRI8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
         ComplexPattern addrOp, Operand memOp>
     : RRI8_Inst<0x02, (outs AR:$t), (ins memOp:$addr),
                 instrAsm#"\t$t, $addr",
                [(set AR:$t, (opNode addrOp:$addr))]> {
     bits<12> addr;
 
     let r = oper;
     let imm8{7-0} = addr{11-4};
     let s{3-0} = addr{3-0};
   }
 }
 
 def L8UI  : Load_RRI8<0x00, "l8ui", zextloadi8, addr_ish1, mem8>;
 def L16SI : Load_RRI8<0x09, "l16si", sextloadi16, addr_ish2, mem16>;
 def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>;
 def L32I  : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>;
 
 // Store instructions
-let mayStore = 1 in {
+let mayStore = 1, usesCustomInserter = 1 in {
   class Store_II8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
         ComplexPattern addrOp, Operand memOp>
     : RRI8_Inst<0x02, (outs), (ins AR:$t, memOp:$addr),
                 instrAsm#"\t$t, $addr",
                [(opNode AR:$t, addrOp:$addr)]> {
     bits<12> addr;
 
     let r = oper;