[m68k] Add TLS Support

[0x59616e]

Summary

This patch introduces TLS (Thread-Local Storage) support to the LLVM m68k backend.

[0x59616e]

A few minor adjustments are required.

[0x59616e]

Add some comments

[jrtc27]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1432

None of this is m68k-specific (with the exception of using unsigned instead of unsigned long), these long comments are just a repeat of how ELF TLS works in general. I don't think they belong here.

1453

Skip the custom node / pseudo and use LowerCallTo?

1500

Skip the custom node / pseudo and use LowerCallTo?

1517

Ditto

llvm/lib/Target/M68k/M68kInstrArithmetic.td

317

Presumably because you're abusing M68kISD::ADD, which has type MxSDT_BiArithCCROut:

// RES, CCR <- op LHS, RHS
def MxSDT_BiArithCCROut : SDTypeProfile<2, 2, [
  /* RES */ SDTCisInt<0>,
  /* CCR */ SDTCisVT<1, i8>,
  /* LHS */ SDTCisSameAs<0, 2>,
  /* RHS */ SDTCisSameAs<0, 3>
]>;

You're using it as if it only had one i32 result, but it's iN,i8 = M68kISD::ADD iN, iN. Since you don't care about CCR here presumably you can just use a normal ISD::ADD instead, but if you do then use the right types.

llvm/lib/Target/M68k/M68kInstrCompiler.td

133 ↗

(On Diff #501464)

Why the blank lines?

134 ↗

(On Diff #501464)

: needs a space

134 ↗

(On Diff #501464)

Surely this function call clobbers all call-clobbered registers like any other architecture's __tls_get_addr? Glancing at glibc, the version used for statically-linked binaries is implemented in C so won't be doing anything special to preserve registers.

135 ↗

(On Diff #501464)

AFAICT this is also implemented in C and thus clobbers the usual call-clobbered registers.

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

161

Comment

llvm/lib/Target/M68k/MCTargetDesc/M68kELFObjectWriter.cpp

74

These should be deindented, but the other variants don't do this so now it's all an inconsistent mess.

llvm/test/CodeGen/M68k/TLS/tlsie.ll

20

These shouldn't be in UTC tests. Besides, it's implied by the assembly, and if you want to test the relocation emission then write MC tests for that part.

[0x59616e]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1432

The code generation snippet for TLS is complicated. These comments help clarify the details and may be helpful for me or others who come to maintain it in the future.

[0x59616e]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1432

*The details of how TLS works are complex*

[jrtc27]

llvm/lib/Target/M68k/M68kISelLowering.cpp

1432

And those who want the details can go read Drepper's TLS document. All these comments are just noise; for anyone who knows how TLS works (which, if you're reading/writing this part of the compiler, you should) it serves no purpose and makes the code harder to read, and for anyone who doesn't they should go read the actual document. Or just read the code, it's not all that complicated, it's clearly just doing __tls_get_addr(GOT + sym@TLSGD), __tls_get_addr(GOT + sym@TLSLDM) + sym@TLSLD, __m68k_read_tp() + *(GOT + sym@GOTTPOFF) and __m68k_read_tp() + sym@TPOFF. If every common bit of lowering were documented like these then the backends would be absurdly large, but we don't, we generally only document places where there are unusual or complicated things going on.

[0x59616e]

This comment was removed by 0x59616e.

[0x59616e]

address feedbacks

[glaubitz]

Do we have any more issues left to address? Seems like all comments have been marked as "done".

[jrtc27]

Some minor comments

llvm/lib/Target/M68k/M68kISelLowering.cpp

1522

Not a useful error message

llvm/test/CodeGen/M68k/TLS/tlsgd.ll

12

Best to use nounwind in tests where you don't care about CFI but get them due to function calls

llvm/test/CodeGen/M68k/TLS/tlsie.ll

11

Why do we need the stack adjustment? We're not passing any arguments to __m68k_read_tp. Or is this some stack alignment issue to compensate for the implicit push of the return address?

llvm/test/CodeGen/M68k/TLS/tlsld.ll

9

Teach ASM_FUNCTION_M68K_RE in UpdateTestChecks to filter these

llvm/test/CodeGen/M68k/TLS/tlsle.ll

4–5

[0x59616e]

address feedbacks

[0x59616e]

llvm/test/CodeGen/M68k/TLS/tlsie.ll

11

This adjustment is the consequence of M68kSubtarget::stackAlignment [0]

The comment says:

/// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment = 8;

I don't know why it is set to 8 as the ABI only requires 2.

@myhsu do you have any clue ?

[0] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/M68k/M68kSubtarget.h#L73

[myhsu]

llvm/test/CodeGen/M68k/TLS/tlsie.ll

11

This adjustment is the consequence of M68kSubtarget::stackAlignment [0]

The comment says:

/// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment = 8;

I don't know why it is set to 8 as the ABI only requires 2.

@myhsu do you have any clue ?

[0] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/M68k/M68kSubtarget.h#L73

I'm not sure why it was assigned 8 bytes even after reading the change log. But I'm pretty sure we want to change that (in another patch, of course) to the minimum alignment, which is 2 bytes.

[glaubitz]

Any updates on this?

[0x59616e]

No updates here. Ready for review.

[jrtc27]

One nit to fix when committing, otherwise nothing jumps out as wrong to me. Someone else with m68k knowledge should give it a once-over.

llvm/utils/UpdateTestChecks/asm.py

67 ↗

(On Diff #519017)

“funciton” in the comment, and should be a separate commit

[RKSimon]

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

670

(style) Avoid auto - use SDValue

672

(style) MachineSDNode *Res

[0x59616e]

Address feedbacks

[glaubitz]

I guess we're good to go now, aren't we?

[0x59616e]

ping. Any suggestion ?

[0x59616e]

The critial C++ part has been well reviewed by jrtc27 and RKSimon. I think the last step would be to verify the correctness of the genenrated m68k assembly. @glaubitz @myhsu could you help on this ? If the generated assembly is ok then I think we can give it a go. @glaubitz I have assigned you as a reviewer so you can decide it on you own.

[glaubitz]

In D144941#4390275, @0x59616e wrote:

The critial C++ part has been well reviewed by jrtc27 and RKSimon. I think the last step would be to verify the correctness of the genenrated m68k assembly. @glaubitz @myhsu could you help on this ? If the generated assembly is ok then I think we can give it a go. @glaubitz I have assigned you as a reviewer so you can decide it on you own.

The patch set allowed me to compile C++ that was making use of TLS and fixed a bug that I originally ran into. So I think it's good to land.

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

if (Node->isMachineOpcode()) {
     Node->setNodeId(-1);
     return; // Already selected.
   }
 
   switch (Opcode) {
   default:
     break;
 
+  case ISD::GLOBAL_OFFSET_TABLE: {
+    SDValue GOT = CurDAG->getTargetExternalSymbol(
+        "_GLOBAL_OFFSET_TABLE_", MVT::i32, M68kII::MO_GOTPCREL);
+    MachineSDNode *Res =
+        CurDAG->getMachineNode(M68k::LEA32q, DL, MVT::i32, GOT);
+    ReplaceNode(Node, Res);
+    return;
+  }
+
   case M68kISD::GLOBAL_BASE_REG:
     ReplaceNode(Node, getGlobalBaseReg());
     return;
   }
 
   SelectCode(Node);
 }
 

llvm/lib/Target/M68k/M68kISelLowering.h

private:
 
   SDValue LowerATOMICFENCE(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
                           CallingConv::ID CallConv, bool IsVarArg,
                           const SmallVectorImpl<ISD::InputArg> &Ins,
                           const SDLoc &DL, SelectionDAG &DAG,
                           SmallVectorImpl<SDValue> &InVals) const;
+  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 
   /// LowerFormalArguments - transform physical registers into virtual
   /// registers and generate load operations for arguments places on the stack.
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,
                                bool IsVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
 
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       LLVMContext &Context) const override;
 
   /// Lower the result values of a call into the
   /// appropriate copies out of appropriate physical registers.
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
                       SelectionDAG &DAG) const override;
 
+  SDValue LowerExternalSymbolCall(SelectionDAG &DAG, SDLoc loc,
+                                  llvm::StringRef SymbolName,
+                                  ArgListTy &&ArgList) const;
+  SDValue getTLSGetAddr(GlobalAddressSDNode *GA, SelectionDAG &DAG,
+                        unsigned TargetFlags) const;
+  SDValue getM68kReadTp(SDLoc Loc, SelectionDAG &DAG) const;
+
+  SDValue LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
+                                 SelectionDAG &DAG) const;
+  SDValue LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
+                               SelectionDAG &DAG) const;
+  SDValue LowerTLSInitialExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) const;
+  SDValue LowerTLSLocalExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) const;
+
   bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
                               SDValue C) const override;
 
   MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
                                        MachineBasicBlock *MBB) const;
   MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
                                           MachineBasicBlock *BB) const;
 

llvm/lib/Target/M68k/M68kISelLowering.cpp

SDValue M68kTargetLowering::LowerOperation(SDValue Op,
   case ISD::SHL_PARTS:
     return LowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:
     return LowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:
     return LowerShiftRightParts(Op, DAG, false);
   case ISD::ATOMIC_FENCE:
     return LowerATOMICFENCE(Op, DAG);
+  case ISD::GlobalTLSAddress:
+    return LowerGlobalTLSAddress(Op, DAG);
   }
 }
 
+SDValue M68kTargetLowering::LowerExternalSymbolCall(SelectionDAG &DAG,
+                                                    SDLoc Loc,
+                                                    llvm::StringRef SymbolName,
+                                                    ArgListTy &&ArgList) const {
+  PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
+  CallLoweringInfo CLI(DAG);
+  CLI.setDebugLoc(Loc)
+      .setChain(DAG.getEntryNode())
+      .setLibCallee(CallingConv::C, PtrTy,
+                    DAG.getExternalSymbol(SymbolName.data(),
+                                          getPointerMemTy(DAG.getDataLayout())),
+                    std::move(ArgList));
+  return LowerCallTo(CLI).first;
+}
+
+SDValue M68kTargetLowering::getTLSGetAddr(GlobalAddressSDNode *GA,
+                                          SelectionDAG &DAG,
+                                          unsigned TargetFlags) const {
+  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
+  SDValue TGA = DAG.getTargetGlobalAddress(
+      GA->getGlobal(), GA, GA->getValueType(0), GA->getOffset(), TargetFlags);
+  SDValue Arg = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, GOT, TGA);
+
+  PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
+
+  ArgListTy Args;
+  ArgListEntry Entry;
+  Entry.Node = Arg;
+  Entry.Ty = PtrTy;
+  Args.push_back(Entry);
+  return LowerExternalSymbolCall(DAG, SDLoc(GA), "__tls_get_addr",
+                                 std::move(Args));
+}
+
+SDValue M68kTargetLowering::getM68kReadTp(SDLoc Loc, SelectionDAG &DAG) const {
+  return LowerExternalSymbolCall(DAG, Loc, "__m68k_read_tp", ArgListTy());
+}
+
+SDValue M68kTargetLowering::LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
+                                                   SelectionDAG &DAG) const {
+  return getTLSGetAddr(GA, DAG, M68kII::MO_TLSGD);
+}
+
+SDValue M68kTargetLowering::LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
+                                                 SelectionDAG &DAG) const {
+  SDValue Addr = getTLSGetAddr(GA, DAG, M68kII::MO_TLSLDM);
+  SDValue TGA =
+      DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
+                                 GA->getOffset(), M68kII::MO_TLSLD);
+  return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Addr);
+}
+
+SDValue M68kTargetLowering::LowerTLSInitialExec(GlobalAddressSDNode *GA,
+                                                SelectionDAG &DAG) const {
+  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
+  SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
+  SDValue TGA =
+      DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
+                                 GA->getOffset(), M68kII::MO_TLSIE);
+  SDValue Addr = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, GOT);
+  SDValue Offset =
+      DAG.getLoad(MVT::i32, SDLoc(GA), DAG.getEntryNode(), Addr,
+                  MachinePointerInfo::getGOT(DAG.getMachineFunction()));
+
+  return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, Offset, Tp);
+}
+
+SDValue M68kTargetLowering::LowerTLSLocalExec(GlobalAddressSDNode *GA,
+                                              SelectionDAG &DAG) const {
+  SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
+  SDValue TGA =
+      DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
+                                 GA->getOffset(), M68kII::MO_TLSLE);
+  return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Tp);
+}
+
+SDValue M68kTargetLowering::LowerGlobalTLSAddress(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  assert(Subtarget.isTargetELF());
+
+  auto *GA = cast<GlobalAddressSDNode>(Op);
+  TLSModel::Model AccessModel = DAG.getTarget().getTLSModel(GA->getGlobal());
+
+  switch (AccessModel) {
+  case TLSModel::GeneralDynamic:
+    return LowerTLSGeneralDynamic(GA, DAG);
+  case TLSModel::LocalDynamic:
+    return LowerTLSLocalDynamic(GA, DAG);
+  case TLSModel::InitialExec:
+    return LowerTLSInitialExec(GA, DAG);
+  case TLSModel::LocalExec:
+    return LowerTLSLocalExec(GA, DAG);
+  }
+
+  llvm_unreachable("Unexpected TLS access model type");
+}
+
 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
                                                 SDValue C) const {
   // Shifts and add instructions in M68000 and M68010 support
   // up to 32 bits, but mul only has 16-bit variant. So it's almost
   // certainly beneficial to lower 8/16/32-bit mul to their
   // add / shifts counterparts. But for 64-bits mul, it might be
   // safer to just leave it to compiler runtime implementations.
   return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();

llvm/lib/Target/M68k/M68kInstrArithmetic.td

 // Add/Sub
 //===----------------------------------------------------------------------===//
 
 defm ADD : MxBiArOp_DF<"add",  MxAdd, 1, 0xD, 0x6>;
 defm ADD : MxBiArOp_AF<"adda", MxAdd, 0xD>;
 defm SUB : MxBiArOp_DF<"sub",  MxSub, 0, 0x9, 0x4>;
 defm SUB : MxBiArOp_AF<"suba", MxSub, 0x9>;
 
+// This pattern is used to enable the instruction selector to select ADD32ab
+// for global values that are allocated in thread-local storage, i.e.:
+//   t8: i32 = ISD::ADD GLOBAL_OFFSET_TABLE, TargetGlobalTLSAddress:i32<ptr @myvar>
+//     ====>
+//   t8: i32,i8 = ADD32ab GLOBAL_OFFSET_TABLE, TargetGlobalTLSAddress:i32<ptr @myvar>
+def : Pat<(add MxARD32:$src, tglobaltlsaddr:$opd), (ADD32ab MxARD32:$src, MxAL32:$opd)>;
 
 let Uses = [CCR], Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 /// Encoding for Extended forms
 /// ------------------------------------------------------
 ///  F  E  D  C | B  A  9 | 8 | 7  6 | 5  4 | 3 | 2  1  0
 /// ------------------------------------------------------

llvm/lib/Target/M68k/M68kInstrInfo.cpp

 M68kInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
   using namespace M68kII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},
       {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},
       {MO_GOT, "m68k-got"},
       {MO_GOTOFF, "m68k-gotoff"},
       {MO_GOTPCREL, "m68k-gotpcrel"},
-      {MO_PLT, "m68k-plt"}};
+      {MO_PLT, "m68k-plt"},
+      {MO_TLSGD, "m68k-tlsgd"},
+      {MO_TLSLD, "m68k-tlsld"},
+      {MO_TLSLDM, "m68k-tlsldm"},
+      {MO_TLSIE, "m68k-tlsie"},
+      {MO_TLSLE, "m68k-tlsle"}};
   return ArrayRef(TargetFlags);
 }
 
 #undef DEBUG_TYPE
 #define DEBUG_TYPE "m68k-create-global-base-reg"
 
 #define PASS_NAME "M68k PIC Global Base Reg Initialization"
 

llvm/lib/Target/M68k/M68kMCInstLower.cpp

case M68kII::MO_GOT:
     RefKind = MCSymbolRefExpr::VK_GOT;
     break;
   case M68kII::MO_GOTOFF:
     RefKind = MCSymbolRefExpr::VK_GOTOFF;
     break;
   case M68kII::MO_PLT:
     RefKind = MCSymbolRefExpr::VK_PLT;
     break;
+  case M68kII::MO_TLSGD:
+    RefKind = MCSymbolRefExpr::VK_TLSGD;
+    break;
+  case M68kII::MO_TLSLD:
+    RefKind = MCSymbolRefExpr::VK_TLSLD;
+    break;
+  case M68kII::MO_TLSLDM:
+    RefKind = MCSymbolRefExpr::VK_TLSLDM;
+    break;
+  case M68kII::MO_TLSIE:
+    RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
+    break;
+  case M68kII::MO_TLSLE:
+    RefKind = MCSymbolRefExpr::VK_TPOFF;
+    break;
   }
 
   if (!Expr) {
     Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
   }
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) {
     Expr = MCBinaryExpr::createAdd(

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

enum TOF {
   ///    name@GOTPCREL
   MO_GOTPCREL,
 
   /// On a symbol operand this indicates that the immediate is offset to the
   /// PLT entry of symbol name from the current code location.
   ///
   ///    name@PLT
   MO_PLT,
+
+  /// On a symbol operand, this indicates that the immediate is the offset to
+  /// the slot in GOT which stores the information for accessing the TLS
+  /// variable. This is used when operating in Global Dynamic mode.
+  ///    name@TLSGD
+  MO_TLSGD,
+
+  /// On a symbol operand, this indicates that the immediate is the offset to
+  /// variable within the thread local storage when operating in Local Dynamic
+  /// mode.
+  ///    name@TLSLD
+  MO_TLSLD,
+
+  /// On a symbol operand, this indicates that the immediate is the offset to
+  /// the slot in GOT which stores the information for accessing the TLS
+  /// variable. This is used when operating in Local Dynamic mode.
+  ///    name@TLSLDM
+  MO_TLSLDM,
+
+  /// On a symbol operand, this indicates that the immediate is the offset to
+  /// the variable within the thread local storage when operating in Initial
+  /// Exec mode.
+  ///    name@TLSIE
+  MO_TLSIE,
+
+  /// On a symbol operand, this indicates that the immediate is the offset to
+  /// the variable within in the thread local storage when operating in Local
+  /// Exec mode.
+  ///    name@TLSLE
+  MO_TLSLE,
+
 }; // enum TOF
 
 /// Return true if the specified TargetFlag operand is a reference to a stub
 /// for a global, not the global itself.
 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
   switch (TargetFlag) {
   default:
     return false;

llvm/lib/Target/M68k/MCTargetDesc/M68kELFObjectWriter.cpp

unsigned M68kELFObjectWriter::getRelocType(MCContext &Ctx,
                                            const MCFixup &Fixup,
                                            bool IsPCRel) const {
   MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
   unsigned Kind = Fixup.getKind();
   M68kRelType Type = getType(Kind, Modifier, IsPCRel);
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
+
+  case MCSymbolRefExpr::VK_TLSGD:
+    switch (Type) {
+    case RT_32:
+      return ELF::R_68K_TLS_GD32;
+    case RT_16:
+      return ELF::R_68K_TLS_GD16;
+    case RT_8:
+      return ELF::R_68K_TLS_GD8;
+    }
+    llvm_unreachable("Unrecognized size");
+  case MCSymbolRefExpr::VK_TLSLDM:
+    switch (Type) {
+    case RT_32:
+      return ELF::R_68K_TLS_LDM32;
+    case RT_16:
+      return ELF::R_68K_TLS_LDM16;
+    case RT_8:
+      return ELF::R_68K_TLS_LDM8;
+    }
+    llvm_unreachable("Unrecognized size");
+  case MCSymbolRefExpr::VK_TLSLD:
+    switch (Type) {
+    case RT_32:
+      return ELF::R_68K_TLS_LDO32;
+    case RT_16:
+      return ELF::R_68K_TLS_LDO16;
+    case RT_8:
+      return ELF::R_68K_TLS_LDO8;
+    }
+    llvm_unreachable("Unrecognized size");
+  case MCSymbolRefExpr::VK_GOTTPOFF:
+    switch (Type) {
+    case RT_32:
+      return ELF::R_68K_TLS_IE32;
+    case RT_16:
+      return ELF::R_68K_TLS_IE16;
+    case RT_8:
+      return ELF::R_68K_TLS_IE8;
+    }
+    llvm_unreachable("Unrecognized size");
+  case MCSymbolRefExpr::VK_TPOFF:
+    switch (Type) {
+    case RT_32:
+      return ELF::R_68K_TLS_LE32;
+    case RT_16:
+      return ELF::R_68K_TLS_LE16;
+    case RT_8:
+      return ELF::R_68K_TLS_LE8;
+    }
+    llvm_unreachable("Unrecognized size");
   case MCSymbolRefExpr::VK_None:
     switch (Type) {
     case RT_32:
       return IsPCRel ? ELF::R_68K_PC32 : ELF::R_68K_32;
     case RT_16:
       return IsPCRel ? ELF::R_68K_PC16 : ELF::R_68K_16;
     case RT_8:
       return IsPCRel ? ELF::R_68K_PC8 : ELF::R_68K_8;

llvm/test/CodeGen/M68k/TLS/tlsgd.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck %s
+
+@myvar = external thread_local global i32, align 4
+
+define ptr @get_addr() nounwind {
+; CHECK-LABEL: get_addr:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
+; CHECK-NEXT:    adda.l myvar@TLSGD, %a0
+; CHECK-NEXT:    move.l %a0, (%sp)
+; CHECK-NEXT:    jsr (__tls_get_addr@PLT,%pc)
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsie.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k -o - %s | FileCheck %s
+
+@myvar = external thread_local global i32, align 4
+
+define dso_local ptr @get_addr() nounwind {
+; CHECK-LABEL: get_addr:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    jsr __m68k_read_tp@PLT
+; CHECK-NEXT:    move.l %a0, %d0
+; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
+; CHECK-NEXT:    add.l (0,myvar@GOTTPOFF,%a0), %d0
+; CHECK-NEXT:    move.l %d0, %a0
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsld.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck %s
+
+@myvar = internal thread_local global i32 2, align 4
+
+define dso_local ptr @get_addr() nounwind {
+; CHECK-LABEL: get_addr:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
+; CHECK-NEXT:    adda.l myvar@TLSLDM, %a0
+; CHECK-NEXT:    move.l %a0, (%sp)
+; CHECK-NEXT:    jsr (__tls_get_addr@PLT,%pc)
+; CHECK-NEXT:    adda.l myvar@TLSLD, %a0
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsle.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k -o - %s | FileCheck %s
+
+@myvar = internal thread_local global i32 2, align 4
+
+define dso_local ptr @get_addr() nounwind {
+; CHECK-LABEL: get_addr:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    suba.l #4, %sp
+; CHECK-NEXT:    jsr __m68k_read_tp@PLT
+; CHECK-NEXT:    adda.l myvar@TPOFF, %a0
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    rts
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)