[m68k] Implement BSR Instruction

[RKSimon]

disassembler tests?

[0x59616e]

Add disassembler test

[myhsu]

LGTM with minor suggestions

llvm/lib/Target/M68k/M68kInstrControl.td

239

another way to simplify this part of the code is to conditionally assign different layout of dags to Inst using TYPE.Size. Such that

1. You can have just one dag disp template argument
2. You don't need the empty (ascend) on line 248

Personally I don't have strong opinion on whether to adopt this simplification since the current version is not utterly messy, so it's up to you

[glaubitz]

Could someone with permissions land this? Thanks!

[myhsu]

In D143315#4215608, @glaubitz wrote:

Could someone with permissions land this? Thanks!

I believe @0x59616e 's plan is to land the entire patch series at once

[glaubitz]

In D143315#4216861, @myhsu wrote:

In D143315#4215608, @glaubitz wrote:

Could someone with permissions land this? Thanks!

I believe @0x59616e 's plan is to land the entire patch series at once

OK, makes sense.

[0x59616e]

Sorry for holding this for so long. I will come back next week since we have a a 5-day holiday in Taiwan.

llvm/lib/Target/M68k/M68kInstrControl.td

 //===-- M68kInstrControl.td - Control Flow Instructions ----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file describes the M68k jump, return, call, and related instructions.
 /// Here is the current status of the file:
 ///
 ///  Machine:
 ///
-///       BRA   [x]     BSR  [ ]     Bcc [~]     DBcc [ ]     FBcc [ ]
+///       BRA   [x]     BSR  [~]     Bcc [~]     DBcc [ ]     FBcc [ ]
 ///       FDBcc [ ]     FNOP [ ]     FPn [ ]     FScc [ ]     FTST [ ]
 ///       JMP   [~]     JSR  [x]     NOP [x]     RTD  [!]     RTR  [ ]
 ///       RTS   [x]     Scc  [~]     TST [ ]
 ///
 ///  Pseudo:
 ///
 ///          RET [x]
 ///    TCRETURNj [x]   TCRETURNq [x]

 def BRA8  : MxBra<MxBrTarget8,
                   (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
 
 def BRA16 : MxBra<MxBrTarget16, (descend 0b0000, 0b0000),
                   (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
 
 def : Pat<(br bb:$target), (BRA8 MxBrTarget8:$target)>;
 
+/// -------------------------------------------------
+///  F  E  D  C  B  A  9  8 | 7  6  5  4  3  2  1  0
+/// -------------------------------------------------
+///  0  1  1  0  0  0  0  1 |   8-BIT DISPLACEMENT
+/// -------------------------------------------------
+///  16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
+/// -------------------------------------------------
+///  32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
+/// -------------------------------------------------
+
+let isBranch = 1, isTerminator = 1 in
+class MxBsr<Operand TARGET, MxType TYPE, dag disp_8, dag disp_16_32>
+    : MxInst<(outs), (ins TARGET:$dst), "bsr."#TYPE.Prefix#"\t$dst"> {
+  let Inst = (ascend
+                (descend 0b0110, 0b0001, disp_8),
+                 disp_16_32
+              );
+}
+
+def BSR8 : MxBsr<MxBrTarget8, MxType8,
+                (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
+
+def BSR16 : MxBsr<MxBrTarget16, MxType16, (descend 0b0000, 0b0000),
+                (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
+
+def BSR32 : MxBsr<MxBrTarget32, MxType32, (descend 0b1111, 0b1111),
+                (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
+                                     (decoder "DecodeImm32"))>;
 
 //===----------------------------------------------------------------------===//
 // Call
 //===----------------------------------------------------------------------===//
 
 // All calls clobber the non-callee saved registers. %SP is marked as
 // a use to prevent stack-pointer assignments that appear immediately
 // before calls from potentially appearing dead. Uses for argument

llvm/test/MC/Disassembler/M68k/control.txt

 # RUN: llvm-mc -disassemble -triple m68k %s | FileCheck %s
 
 # CHECK: bra $0
 0x60 0x00 0x00 0x00
 # CHECK: jsr $0
 0x4e 0xb9 0x00 0x00 0x00 0x00
 # CHECK: rts
 0x4e 0x75
 # CHECK: seq %d0
 0x57 0xc0
 # CHECK: sgt %d0
 0x5e 0xc0
 # CHECK: nop
 0x4e 0x71
+
+# CHECK: bsr.b $1
+0x61 0x01
+
+# CHECK: bsr.w $f01
+0x61 0x00 0x0f 0x01
+
+# CHECK: bsr.l $f0001
+0x61 0xff 0x00 0x0f 0x00 0x01

llvm/test/MC/M68k/Control/bsr.s

+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+  ; CHECK:      bsr.b   .LBB0_1
+  ; CHECK-SAME: encoding: [0x61,A]
+        ; CHECK:      fixup A - offset: 1, value: .LBB0_1-1, kind: FK_PCRel_1
+  bsr.b .LBB0_1
+  ; CHECK:      bsr.w   .LBB0_2
+  ; CHECK-SAME: encoding: [0x61,0x00,A,A]
+        ; CHECK:      fixup A - offset: 2, value: .LBB0_2, kind: FK_PCRel_2
+  bsr.w .LBB0_2
+  ; CHECK:     bsr.l   .LBB0_3
+  ; CHECK-SAME: encoding: [0x61,0xff,A,A,A,A] 
+        ; CHECK:      fixup A - offset: 2, value: .LBB0_3, kind: FK_PCRel_4
+  bsr.l .LBB0_3  
+.LBB0_1:
+  ; CHECK:      add.l  #0, %d0
+  ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x00]
+  add.l #0, %d0
+  ; CHECK:      rts
+  ; CHECK-SAME: encoding: [0x4e,0x75]
+  rts
+.LBB0_2:
+  ; CHECK:      add.l  #1, %d0
+  ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x01]
+  add.l #1, %d0
+  ; CHECK:      rts
+  ; CHECK-SAME: encoding: [0x4e,0x75]
+  rts
+.LBB0_3:
+  ; CHECK:      add.l  #1, %d0
+  ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x01]
+  add.l #1, %d0
+  ; CHECK:      rts
+  ; CHECK-SAME: encoding: [0x4e,0x75]
+  rts

llvm/test/MC/M68k/Relaxations/bsr.s

+; RUN: llvm-mc -triple=m68k -motorola-integers -filetype=obj < %s \
+; RUN:     | llvm-objdump -d - | FileCheck %s
+
+; CHECK-LABEL: <TIGHT>:
+TIGHT:
+  ; CHECK: bsr.w   $7a
+  bsr.w .LBB0_2
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+.LBB0_2:
+  add.l #0, %d0
+  rts
+
+; CHECK-LABEL: <RELAXED>:
+RELAXED:
+  ; CHECK: bsr.b   $82
+  bsr.b .LBB1_2
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+  move.l  $0, $0
+.LBB1_2:
+  add.l #0, %d0
+  rts
+
+; CHECK-LABEL: <ZERO>:
+ZERO:
+  ; CHECK: bsr.w    $2
+  bsr.w .LBB2_1
+.LBB2_1:
+  add.l #0, %d0
+  rts

llvm/test/MC/M68k/Relocations/text-plt.s

 ; RUN: llvm-mc -triple m68k -filetype=obj %s -o - \
 ; RUN:   | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
 ; RUN: llvm-mc -triple m68k -show-encoding %s -o - \
 ; RUN:   | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
 
 ; RELOC: R_68K_PLT16 target 0x0
 ; INSTR: jsr     (target@PLT,%pc)
 ; FIXUP: fixup A - offset: 2, value: target@PLT, kind: FK_PCRel_2
 jsr (target@PLT,%pc)
+
+; RELOC: R_68K_PLT32  __tls_get_addr 0x0
+; INSTR: bsr.l   __tls_get_addr@PLT
+; FIXUP: fixup A - offset: 2, value: __tls_get_addr@PLT, kind: FK_PCRel_4
+bsr.l __tls_get_addr@PLT