[m68k] Add TLS support

[0x59616e]

Summary

Add TLS support to m68k backend in LLVM

This change introduces support for Thread-Local Storage (TLS) in the m68k backend of LLVM. TLS is implemented using the pseudo instruction TLS_(GD|LD|IE|LE), which is later expanded into the corresponding instruction in AsmPrinter.

[glaubitz]

Doesn't seem to build at the moment:

/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp: In member function ‘void llvm::M68kAsmPrinter::LowerTLSDynamic(const llvm::MachineInstr*)’:
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:124:52: error: ‘ADD32ab’ is not a member of ‘llvm::M68k’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:124:52: note: suggested alternative: ‘ADD32ar’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
                                                    ADD32ar
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:131:52: error: ‘BSR32’ is not a member of ‘llvm::M68k’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::BSR32).addExpr(TlsGetAddr),
                                                    ^~~~~
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:131:52: note: suggested alternative: ‘LSR32di’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::BSR32).addExpr(TlsGetAddr),
                                                    ^~~~~
                                                    LSR32di
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:142:52: error: ‘ADD32ab’ is not a member of ‘llvm::M68k’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:142:52: note: suggested alternative: ‘ADD32ar’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
                                                    ADD32ar
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp: In member function ‘void llvm::M68kAsmPrinter::LowerTLSExec(const llvm::MachineInstr*)’:
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:179:54: error: ‘ADD32ab’ is not a member of ‘llvm::M68k’
     OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                      ^~~~~~~
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:179:54: note: suggested alternative: ‘ADD32ar’
     OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                      ^~~~~~~
                                                      ADD32ar
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:192:52: error: ‘ADD32ab’ is not a member of ‘llvm::M68k’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
/data/home/glaubitz/llvm-project/llvm/lib/Target/M68k/M68kAsmPrinter.cpp:192:52: note: suggested alternative: ‘ADD32ar’
   OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
                                                    ^~~~~~~
                                                    ADD32ar

[0x59616e]

In D143317#4104732, @glaubitz wrote:

Doesn't seem to build at the moment:

D143316 and D143315 are required to build this.

[jrtc27]

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

671

Yeah, indeed, this should be done in ISelLowering, not in AsmPrinter

[myhsu]

just skimmed through the patch but I think either ISelLowering (in which case you probably don't need the custom ISD) or the pseudo instruction expanding Pass will be a better place to put the main logics, rather than AsmPrinter.

[0x59616e]

Plan to update the code per the advice received

[0x59616e]

The access model type is disambiguated at ISelLowering, but it still needs to be expanded in AsmPrinter. I am uncertain how to express the Global Offset Table in MachineInstr.

[jrtc27]

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

115

This is how you do GOT accesses…

llvm/lib/Target/M68k/M68kAsmPrinter.h

explicit M68kAsmPrinter(TargetMachine &TM,
       : AsmPrinter(TM, std::move(Streamer)) {
     Subtarget = static_cast<M68kTargetMachine &>(TM).getSubtargetImpl();
   }
 
   StringRef getPassName() const override { return "M68k Assembly Printer"; }
 
   virtual bool runOnMachineFunction(MachineFunction &MF) override;
 
+  void LowerTLSDynamic(const MachineInstr *MI, bool isGeneralDynamic);
+  void LowerTLSExec(const MachineInstr *MI, bool isInitialExec);
+  void LowerTLS(const MachineInstr *MI);
+
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &OS) override;
 
   void emitInstruction(const MachineInstr *MI) override;
   void emitFunctionBodyStart() override;
   void emitFunctionBodyEnd() override;
   void emitStartOfAsmFile(Module &M) override;
   void emitEndOfAsmFile(Module &M) override;
 };
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_M68K_M68KASMPRINTER_H

llvm/lib/Target/M68k/M68kAsmPrinter.cpp

 
 #include "M68kAsmPrinter.h"
 
 #include "M68k.h"
 #include "M68kMachineFunction.h"
 #include "MCTargetDesc/M68kInstPrinter.h"
 #include "TargetInfo/M68kTargetInfo.h"
 
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/TargetRegistry.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "m68k-asm-printer"
 
 bool M68kAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   MMFI = MF.getInfo<M68kMachineFunctionInfo>();
if (!ExtraCode || !ExtraCode[0]) {
     printOperand(MI, OpNo, OS);
     return false;
   }
 
   // Fallback to the default implementation.
   return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
 }
 
+static void EmitLoadGOTInstr(MCStreamer *Streamer, MCContext &Ctx,
+                             const MCSubtargetInfo &SI) {
+  const auto *GOTRefExpr = MCSymbolRefExpr::create(
+      "_GLOBAL_OFFSET_TABLE_", MCSymbolRefExpr::VK_GOTPCREL, Ctx);
+  Streamer->emitInstruction(MCInstBuilder(M68k::LEA32q)
+                                .addReg(M68k::A5)
+                                .addExpr(GOTRefExpr)
+                                .addReg(M68k::A5),
+                            SI);
+}
+
+void M68kAsmPrinter::LowerTLSDynamic(const MachineInstr *MI,
+                                     bool isGeneralDynamic) {
+  // General Dynamic:
+  //  lea (%pc, _GLOBAL_OFFSET_TABLE_@GOTPC),%a5
+  //  adda.l #myvar@TLSGD,%a5
+  //  move.l %a5,-(%sp)
+  //  bsr.l __tls_get_addr@PLTPC
+  //  add.l #4, %sp
+
+  // Local Dynamic:
+  //  lea (%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %a5
+  //  adda.l #myvar@TLSLDM,%a5
+  //  move.l %a5,-(%sp)
+  //  bsr.l __tls_get_addr@PLTPC
+  //  add.l #4,%sp
+  //  adda.l #myvar@TLSLDO,%a0
+
+  MCContext &Ctx = OutContext;
+  const MCSubtargetInfo &SI = getSubtargetInfo();
+  const MachineOperand &MO = MI->getOperand(0);
+  assert(MO.isGlobal());
+
+  const auto *TLSRefExpr = MCSymbolRefExpr::create(
+      MO.getGlobal()->getName(),
+      isGeneralDynamic ? MCSymbolRefExpr::VK_TLSGD : MCSymbolRefExpr::VK_TLSLDM,
+      Ctx);
+  const auto *TlsGetAddr =
+      MCSymbolRefExpr::create("__tls_get_addr", MCSymbolRefExpr::VK_PLT, Ctx);
+
+  EmitLoadGOTInstr(OutStreamer.get(), Ctx, SI);
+
+  OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
+                                   .addReg(M68k::A5)
+                                   .addReg(M68k::A5)
+                                   .addExpr(TLSRefExpr),
+                               SI);
+  OutStreamer->emitInstruction(
+      MCInstBuilder(M68k::MOV32ea).addReg(M68k::SP).addReg(M68k::A5), SI);
+  OutStreamer->emitInstruction(MCInstBuilder(M68k::BSR32).addExpr(TlsGetAddr),
+                               SI);
+  OutStreamer->emitInstruction(
+      MCInstBuilder(M68k::ADD32ai).addReg(M68k::SP).addReg(M68k::SP).addImm(4),
+      SI);
+
+  if (isGeneralDynamic)
+    return;
+
+  TLSRefExpr = MCSymbolRefExpr::create(MO.getGlobal()->getName(),
+                                       MCSymbolRefExpr::VK_TLSLD, Ctx);
+  OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
+                                   .addReg(M68k::A0)
+                                   .addReg(M68k::A0)
+                                   .addExpr(TLSRefExpr),
+                               SI);
+}
+
+void M68kAsmPrinter::LowerTLSExec(const MachineInstr *MI, bool isInitialExec) {
+  // Initial Exec:
+  //   jsr __m68k_read_tp
+  //   lea (%pc, _GLOBAL_OFFSET_TABLE_@GOTPC),%a5
+  //   adda.l myvar@TLSIE,%a5
+  //   adda.l (%a5),%a0
+
+  // Local Exec:
+  //   jsr __m68k_read_tp
+  //   adda.l #myvar@TLSLE,%a0
+
+  MCContext &Ctx = OutContext;
+  const MCSubtargetInfo &SI = getSubtargetInfo();
+  const MachineOperand &MO = MI->getOperand(0);
+  assert(MO.isGlobal());
+
+  const auto *ReadTpExpr =
+      MCSymbolRefExpr::create("__m68k_read_tp", MCSymbolRefExpr::VK_None, Ctx);
+  OutStreamer->emitInstruction(MCInstBuilder(M68k::CALLb).addExpr(ReadTpExpr),
+                               SI);
+
+  const auto *TLSRefExpr = MCSymbolRefExpr::create(
+      MO.getGlobal()->getName(),
+      isInitialExec ? MCSymbolRefExpr::VK_GOTTPOFF : MCSymbolRefExpr::VK_TPOFF,
+      Ctx);
+
+  if (isInitialExec) {
+    EmitLoadGOTInstr(OutStreamer.get(), Ctx, SI);
+    OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
+                                     .addReg(M68k::A5)
+                                     .addReg(M68k::A5)
+                                     .addExpr(TLSRefExpr),
+                                 SI);
+    OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32aj)
+                                     .addReg(M68k::A0)
+                                     .addReg(M68k::A0)
+                                     .addReg(M68k::A5),
+                                 SI);
+    return;
+  }
+
+  OutStreamer->emitInstruction(MCInstBuilder(M68k::ADD32ab)
+                                   .addReg(M68k::A0)
+                                   .addReg(M68k::A0)
+                                   .addExpr(TLSRefExpr),
+                               SI);
+}
+
+void M68kAsmPrinter::LowerTLS(const MachineInstr *MI) {
+  switch (MI->getOpcode()) {
+  case M68k::TLS_GD:
+    return LowerTLSDynamic(MI, /*isGeneralDynamic*/ true);
+  case M68k::TLS_LD:
+    return LowerTLSDynamic(MI, /*isGeneralDynamic*/ false);
+  case M68k::TLS_IE:
+    return LowerTLSExec(MI, /*isInitialExec*/ true);
+  case M68k::TLS_LE:
+    return LowerTLSExec(MI, /*isInitalExec*/ false);
+
+  default:
+    llvm_unreachable("unexpected flag");
+  }
+}
+
 void M68kAsmPrinter::emitInstruction(const MachineInstr *MI) {
   M68k_MC::verifyInstructionPredicates(MI->getOpcode(),
                                        getSubtargetInfo().getFeatureBits());
 
   switch (MI->getOpcode()) {
   default: {
     if (MI->isPseudo()) {
       LLVM_DEBUG(dbgs() << "Pseudo opcode(" << MI->getOpcode()
                         << ") found in EmitInstruction()\n");
       llvm_unreachable("Cannot proceed");
     }
     break;
   }
   case M68k::TAILJMPj:
   case M68k::TAILJMPq:
     // Lower these as normal, but add some comments.
     OutStreamer->AddComment("TAILCALL");
     break;
+  case M68k::TLS_GD:
+  case M68k::TLS_LD:
+  case M68k::TLS_IE:
+  case M68k::TLS_LE:
+    LowerTLS(MI);
+    return;
   }
 
   MCInst TmpInst0;
   MCInstLowering->Lower(MI, TmpInst0);
   OutStreamer->emitInstruction(TmpInst0, getSubtargetInfo());
 }
 
 void M68kAsmPrinter::emitFunctionBodyStart() {}

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

#include "M68kGenDAGISel.inc"
   bool SelectARIPI(SDNode *Parent, SDValue N, SDValue &Base);
   bool SelectARIPD(SDNode *Parent, SDValue N, SDValue &Base);
   bool SelectARID(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Base);
   bool SelectARII(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Base,
                   SDValue &Index);
   bool SelectAL(SDNode *Parent, SDValue N, SDValue &Sym);
   bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm);
   bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index);
-
+  void SelectTLS(SDNode *Node, SDLoc DL, unsigned Opcode);
   // If Address Mode represents Frame Index store FI in Disp and
   // Displacement bit size in Base. These values are read symmetrically by
   // M68kRegisterInfo::eliminateFrameIndex method
   inline bool getFrameIndexAddress(M68kISelAddressMode &AM, const SDLoc &DL,
                                    SDValue &Disp, SDValue &Base) {
     if (AM.BaseType == M68kISelAddressMode::Base::FrameIndexBase) {
       Disp = getI32Imm(AM.Disp, DL);
       Base = CurDAG->getTargetFrameIndex(
void M68kDAGToDAGISel::Select(SDNode *Node) {
 
   switch (Opcode) {
   default:
     break;
 
   case M68kISD::GLOBAL_BASE_REG:
     ReplaceNode(Node, getGlobalBaseReg());
     return;
+
+  case M68kISD::TLS_GD:
+    return SelectTLS(Node, DL, M68k::TLS_GD);
+  case M68kISD::TLS_LD:
+    return SelectTLS(Node, DL, M68k::TLS_LD);
+  case M68kISD::TLS_IE:
+    return SelectTLS(Node, DL, M68k::TLS_IE);
+  case M68kISD::TLS_LE:
+    return SelectTLS(Node, DL, M68k::TLS_LE);
   }
 
   SelectCode(Node);
+  LLVM_DEBUG(CurDAG->dump());
+}
+
+void M68kDAGToDAGISel::SelectTLS(SDNode *Node, SDLoc DL, unsigned Opcode) {
+  auto *NewNode = CurDAG->getMachineNode(Opcode, DL, Node->getValueType(0),
+                                         Node->getOperand(0));
+  ReplaceNode(Node, NewNode);
+  return;
 }
 
 bool M68kDAGToDAGISel::SelectARIPI(SDNode *Parent, SDValue N, SDValue &Base) {
   LLVM_DEBUG(dbgs() << "Selecting AddrType::ARIPI: ");
   LLVM_DEBUG(dbgs() << "NOT IMPLEMENTED\n");
   return false;
 }
 

llvm/lib/Target/M68k/M68kISelLowering.h

enum NodeType {
   /// Special wrapper used under M68k PIC mode for PC
   /// relative displacements.
   WrapperPC,
 
   // For allocating variable amounts of stack space when using
   // segmented stacks. Check if the current stacklet has enough space, and
   // falls back to heap allocation if not.
   SEG_ALLOCA,
+
+  /// Thread local storage support.
+  TLS_GD,
+  TLS_LD,
+  TLS_IE,
+  TLS_LE,
 };
 } // namespace M68kISD
 
 /// Define some predicates that are used for node matching.
 namespace M68k {
 
 /// Determines whether the callee is required to pop its
 /// own arguments. Callee pop is necessary to support tail calls.
private:
   SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 
   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                           CallingConv::ID CallConv, bool IsVarArg,
                           const SmallVectorImpl<ISD::InputArg> &Ins,
                           const SDLoc &DL, SelectionDAG &DAG,
                           SmallVectorImpl<SDValue> &InVals) const;
+  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 
   /// LowerFormalArguments - transform physical registers into virtual
   /// registers and generate load operations for arguments places on the stack.
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,
                                bool IsVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;

llvm/lib/Target/M68k/M68kISelLowering.cpp

SDValue M68kTargetLowering::LowerOperation(SDValue Op,
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::SHL_PARTS:
     return LowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:
     return LowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:
     return LowerShiftRightParts(Op, DAG, false);
+  case ISD::GlobalTLSAddress:
+    return LowerGlobalTLSAddress(Op, DAG);
   }
 }
 
+static SDValue LowerTLS(GlobalAddressSDNode *GA, SelectionDAG &DAG,
+                        unsigned Opcode) {
+  SDLoc DL(GA);
+  SDValue TGA = DAG.getTargetGlobalAddress(
+      GA->getGlobal(), GA, GA->getValueType(0), GA->getOffset());
+  return DAG.getNode(Opcode, DL, GA->getValueType(0), TGA);
+}
+
+static SDValue LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
+                                      SelectionDAG &DAG) {
+  return LowerTLS(GA, DAG, M68kISD::TLS_GD);
+}
+
+static SDValue LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
+                                    SelectionDAG &DAG) {
+  return LowerTLS(GA, DAG, M68kISD::TLS_LD);
+}
+
+static SDValue LowerTLSInitialExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) {
+  return LowerTLS(GA, DAG, M68kISD::TLS_IE);
+}
+
+static SDValue LowerTLSLocalExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) {
+  return LowerTLS(GA, DAG, M68kISD::TLS_LE);
+}
+
+SDValue M68kTargetLowering::LowerGlobalTLSAddress(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  assert(Subtarget.isTargetELF());
+
+  auto *GA = cast<GlobalAddressSDNode>(Op);
+  TLSModel::Model AccessModel = DAG.getTarget().getTLSModel(GA->getGlobal());
+
+  switch (AccessModel) {
+  case TLSModel::GeneralDynamic:
+    return LowerTLSGeneralDynamic(GA, DAG);
+  case TLSModel::LocalDynamic:
+    return LowerTLSLocalDynamic(GA, DAG);
+  case TLSModel::InitialExec:
+    return LowerTLSInitialExec(GA, DAG);
+  case TLSModel::LocalExec:
+    return LowerTLSLocalExec(GA, DAG);
+  }
+
+  llvm_unreachable("should not be here");
+}
+
 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
                                                 SDValue C) const {
   // Shifts and add instructions in M68000 and M68010 support
   // up to 32 bits, but mul only has 16-bit variant. So it's almost
   // certainly beneficial to lower 8/16/32-bit mul to their
   // add / shifts counterparts. But for 64-bits mul, it might be
   // safer to just leave it to compiler runtime implementations.
   return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case M68kISD::GLOBAL_BASE_REG:
     return "M68kISD::GLOBAL_BASE_REG";
   case M68kISD::Wrapper:
     return "M68kISD::Wrapper";
   case M68kISD::WrapperPC:
     return "M68kISD::WrapperPC";
   case M68kISD::SEG_ALLOCA:
     return "M68kISD::SEG_ALLOCA";
+  case M68kISD::TLS_GD:
+    return "M68kISD::TLS_GD";
+  case M68kISD::TLS_LD:
+    return "M68kISD::TLS_LD";
+  case M68kISD::TLS_IE:
+    return "M68kISD::TLS_IE";
+  case M68kISD::TLS_LE:
+    return "M68kISD::TLS_LE";
   default:
     return NULL;
   }
 }
 
 CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool Return,
                                               bool IsVarArg) const {
   if (Return)
     return RetCC_M68k_C;
   else
     return CC_M68k_C;
 }

llvm/lib/Target/M68k/M68kInstrCompiler.td

 // allocated by bumping the stack pointer. Otherwise memory is allocated from
 // the heap.
 //===----------------------------------------------------------------------===//
 
 let Defs = [SP, CCR], Uses = [SP] in
 let usesCustomInserter = 1 in
 def SALLOCA : MxPseudo<(outs MxARD32:$dst), (ins MxARD32:$size),
                        [(set iPTR:$dst, (MxSegAlloca iPTR:$size))]>;
+
+//===----------------------------------------------------------------------===//
+// Thread local storage support
+//===----------------------------------------------------------------------===//
+
+let isCall = 1, Defs = [A0, A5], mayLoad = 1 in {
+
+def TLS_GD : MxPseudo<(outs), (ins MxAL32:$sym)>;
+def TLS_LD : MxPseudo<(outs), (ins MxAL32:$sym)>;
+def TLS_IE : MxPseudo<(outs), (ins MxAL32:$sym)>;
+def TLS_LE : MxPseudo<(outs), (ins MxAL32:$sym)>;
+
+}

llvm/lib/Target/M68k/M68kInstrInfo.cpp

 M68kInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
   using namespace M68kII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},
       {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},
       {MO_GOT, "m68k-got"},
       {MO_GOTOFF, "m68k-gotoff"},
       {MO_GOTPCREL, "m68k-gotpcrel"},
-      {MO_PLT, "m68k-plt"}};
+      {MO_PLT, "m68k-plt"},
+      {MO_TLS_GD, "m68k-tlsgd"},
+      {MO_TLS_LD, "m68k-tlsld"},
+      {MO_TLS_IE, "m68k-tlsie"},
+      {MO_TLS_LE, "m68k-tlsle"}};
   return ArrayRef(TargetFlags);
 }
 
 namespace {
 /// Create Global Base Reg pass. This initializes the PIC global base register
 struct CGBR : public MachineFunctionPass {
   static char ID;
   CGBR() : MachineFunctionPass(ID) {}

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

enum TOF {
   /// On a symbol operand this indicates that the immediate is the pc-relative
   /// address of the symbol.
   MO_PC_RELATIVE_ADDRESS,
 
   /// On a symbol operand this indicates that the immediate is the offset to
   /// the GOT entry for the symbol name from the base of the GOT.
   ///
   ///    name@GOT
   MO_GOT,
 
   /// On a symbol operand this indicates that the immediate is the offset to
   /// the location of the symbol name from the base of the GOT.
   ///
   ///    name@GOTOFF
   MO_GOTOFF,
 
   /// On a symbol operand this indicates that the immediate is offset to the
   /// GOT entry for the symbol name from the current code location.
   ///
   ///    name@GOTPCREL
   MO_GOTPCREL,
 
   /// On a symbol operand this indicates that the immediate is offset to the
   /// PLT entry of symbol name from the current code location.
   ///
   ///    name@PLT
   MO_PLT,
+
+  MO_TLS_GD,
+  MO_TLS_LD,
+  MO_TLS_IE,
+  MO_TLS_LE,
 }; // enum TOF
 
 /// Return true if the specified TargetFlag operand is a reference to a stub
 /// for a global, not the global itself.
 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
   switch (TargetFlag) {
   default:
     return false;

llvm/lib/Target/M68k/MCTargetDesc/M68kELFObjectWriter.cpp

 
 unsigned M68kELFObjectWriter::getRelocType(MCContext &Ctx,
                                            const MCValue &Target,
                                            const MCFixup &Fixup,
                                            bool IsPCRel) const {
   MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
   unsigned Kind = Fixup.getKind();
   M68kRelType Type = getType(Kind, Modifier, IsPCRel);
+
+#define MAP_RELOC_TYPE(KIND, TYPE)                                             \
+  case MCSymbolRefExpr::KIND:                                                  \
+    switch (Type) {                                                            \
+    case RT_32:                                                                \
+      return ELF::TYPE##32;                                                    \
+    case RT_16:                                                                \
+      return ELF::TYPE##16;                                                    \
+    case RT_8:                                                                 \
+      return ELF::TYPE##8;                                                     \
+    }                                                                          \
+    llvm_unreachable("Unrecognized size");
+
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
+
+    MAP_RELOC_TYPE(VK_TLSGD, R_68K_TLS_GD)
+    MAP_RELOC_TYPE(VK_TLSLDM, R_68K_TLS_LDM)
+    MAP_RELOC_TYPE(VK_TLSLD, R_68K_TLS_LDO)
+    MAP_RELOC_TYPE(VK_GOTTPOFF, R_68K_TLS_IE)
+    MAP_RELOC_TYPE(VK_TPOFF, R_68K_TLS_LE)
+
   case MCSymbolRefExpr::VK_None:
     switch (Type) {
     case RT_32:
       return IsPCRel ? ELF::R_68K_PC32 : ELF::R_68K_32;
     case RT_16:
       return IsPCRel ? ELF::R_68K_PC16 : ELF::R_68K_16;
     case RT_8:
       return IsPCRel ? ELF::R_68K_PC8 : ELF::R_68K_8;

llvm/test/CodeGen/M68k/TLS/tlsgd.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck --check-prefix=CODEGEN %s
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s --filetype=obj \
+; RUN:      | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
+
+@myvar = external thread_local global i32, align 4
+
+define ptr @get_addr() {
+; CODEGEN-LABEL: get_addr:
+; CODEGEN:         .cfi_startproc
+; CODEGEN-NEXT:  ; %bb.0: ; %entry
+; CODEGEN-NEXT:    suba.l #4, %sp
+; CODEGEN-NEXT:    .cfi_def_cfa_offset -8
+; CODEGEN-NEXT:    movem.l %a5, (0,%sp) ; 8-byte Folded Spill
+; CODEGEN-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a5
+; CODEGEN-NEXT:    adda.l myvar@TLSGD, %a5
+; CODEGEN-NEXT:    move.l %a5, -(%sp)
+; CODEGEN-NEXT:    bsr.l __tls_get_addr@PLT
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    move.l %a0, %d0
+; CODEGEN-NEXT:    movem.l (0,%sp), %a5 ; 8-byte Folded Reload
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    rts
+
+; RELOC-LABEL: Section (3) .rela.text
+; RELOC-NEXT: 0xE R_68K_GOTPCREL16 _GLOBAL_OFFSET_TABLE_ 0x0
+; RELOC-NEXT: 0x12 R_68K_TLS_GD32 myvar 0x0
+; RELOC-NEXT: 0x1A R_68K_PLT32 __tls_get_addr 0x0
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsie.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k -o - %s | FileCheck --check-prefix=CODEGEN %s
+; RUN: llc -mtriple=m68k -o - %s --filetype=obj \
+; RUN:      | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
+
+@myvar = external thread_local global i32, align 4
+
+define dso_local ptr @get_addr() {
+; CODEGEN-LABEL: get_addr:
+; CODEGEN:         .cfi_startproc
+; CODEGEN-NEXT:  ; %bb.0: ; %entry
+; CODEGEN-NEXT:    suba.l #4, %sp
+; CODEGEN-NEXT:    .cfi_def_cfa_offset -8
+; CODEGEN-NEXT:    movem.l %a5, (0,%sp) ; 8-byte Folded Spill
+; CODEGEN-NEXT:    jsr __m68k_read_tp
+; CODEGEN-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a5
+; CODEGEN-NEXT:    adda.l myvar@GOTTPOFF, %a5
+; CODEGEN-NEXT:    adda.l (%a5), %a0
+; CODEGEN-NEXT:    move.l %a0, %d0
+; CODEGEN-NEXT:    movem.l (0,%sp), %a5 ; 8-byte Folded Reload
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    rts
+
+; RELOC-LABEL: Section (3) .rela.text
+; RELOC-NEXT: 0xE R_68K_32 __m68k_read_tp 0x0
+; RELOC-NEXT: 0x14 R_68K_GOTPCREL16 _GLOBAL_OFFSET_TABLE_ 0x0
+; RELOC-NEXT: 0x18 R_68K_TLS_IE32 myvar 0x0
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsld.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck --check-prefix=CODEGEN %s
+; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s --filetype=obj \
+; RUN:      | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
+
+@myvar = internal thread_local global i32 2, align 4
+
+define dso_local ptr @get_addr() {
+; CODEGEN-LABEL: get_addr:
+; CODEGEN:       .Lget_addr$local:
+; CODEGEN-NEXT:    .type .Lget_addr$local,@function
+; CODEGEN-NEXT:    .cfi_startproc
+; CODEGEN-NEXT:  ; %bb.0: ; %entry
+; CODEGEN-NEXT:    suba.l #4, %sp
+; CODEGEN-NEXT:    .cfi_def_cfa_offset -8
+; CODEGEN-NEXT:    movem.l %a5, (0,%sp) ; 8-byte Folded Spill
+; CODEGEN-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a5
+; CODEGEN-NEXT:    adda.l myvar@TLSLDM, %a5
+; CODEGEN-NEXT:    move.l %a5, -(%sp)
+; CODEGEN-NEXT:    bsr.l __tls_get_addr@PLT
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    adda.l myvar@TLSLD, %a0
+; CODEGEN-NEXT:    move.l %a0, %d0
+; CODEGEN-NEXT:    movem.l (0,%sp), %a5 ; 8-byte Folded Reload
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    rts
+
+; RELOC-LABEL: Section (3) .rela.text {
+; RELOC-NEXT: 0xE R_68K_GOTPCREL16 _GLOBAL_OFFSET_TABLE_ 0x0
+; RELOC-NEXT: 0x12 R_68K_TLS_LDM32 myvar 0x0
+; RELOC-NEXT: 0x1A R_68K_PLT32 __tls_get_addr 0x0
+; RELOC-NEXT: 0x26 R_68K_TLS_LDO32 myvar 0x0
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsle.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k -o - %s | FileCheck --check-prefix=CODEGEN %s
+; RUN: llc -mtriple=m68k -o - %s --filetype=obj \
+; RUN:      | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
+
+@myvar = internal thread_local global i32 2, align 4
+
+define dso_local ptr @get_addr() {
+; CODEGEN-LABEL: get_addr:
+; CODEGEN:         .cfi_startproc
+; CODEGEN-NEXT:  ; %bb.0: ; %entry
+; CODEGEN-NEXT:    suba.l #4, %sp
+; CODEGEN-NEXT:    .cfi_def_cfa_offset -8
+; CODEGEN-NEXT:    movem.l %a5, (0,%sp) ; 8-byte Folded Spill
+; CODEGEN-NEXT:    jsr __m68k_read_tp
+; CODEGEN-NEXT:    adda.l myvar@TPOFF, %a0
+; CODEGEN-NEXT:    move.l %a0, %d0
+; CODEGEN-NEXT:    movem.l (0,%sp), %a5 ; 8-byte Folded Reload
+; CODEGEN-NEXT:    adda.l #4, %sp
+; CODEGEN-NEXT:    rts
+
+; RELOC-LABEL: Section (3) .rela.text
+; RELOC-NEXT: 0xE R_68K_32 __m68k_read_tp 0x0
+; RELOC-NEXT: 0x14 R_68K_TLS_LE32 myvar 0x0
+
+entry:
+  %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
+  ret ptr %0
+}
+
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)