[DAG] Handle build_vector with all undefs in reduceBuildVecTruncToBitCast

[Pierre-vh]

Summary

While working on D143731 I hit a case where a build_vector with 2 undef operands could be generated (with one undef hidden behind a bitcast).
That made reduceBuildVecTruncToBitCast crash because it seems to assume there is at least one good operand.

[arsenm]

llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll

875 ↗

(On Diff #496864)

Shouldn't use anonymous values in tests

914 ↗

(On Diff #496864)

Can this not reduce at all?

[Pierre-vh]

Reduce test, move test elsewhere (as it doesn't have a bitcast anymore)

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (In.getOpcode() != ISD::SRL) {
 
       // The extracted value is not extracted at the right position
       if (ShiftAmt != i * ScalarTypeBitsize)
         return SDValue();
     }
   }
 
   // Only cast if the size is the same
-  if (Src.getValueType().getSizeInBits() != VT.getSizeInBits())
+  if (!Src || Src.getValueType().getSizeInBits() != VT.getSizeInBits())
     return SDValue();
 
   return DAG.getBitcast(VT, Src);
 }
 
 SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
                                            ArrayRef<int> VectorMask,
                                            SDValue VecIn1, SDValue VecIn2,

llvm/test/CodeGen/AMDGPU/undef-build-vector.ll

+; RUN: llc -march=amdgcn < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+
+; Checks that we don't crash when code produces a build_vector with two undef operands.
+
+; CHECK: {{^}}buildvector_undefs:
+define amdgpu_kernel void @buildvector_undefs(<2 x i16> %in) {
+entry:
+  %i0 = call <16 x i16> @llvm.vector.insert.v16i16.v2i16(<16 x i16> poison, <2 x i16> %in, i64 0)
+  %i1 = call <16 x i16> @llvm.vector.insert.v16i16.v2i16(<16 x i16> %i0, <2 x i16> zeroinitializer, i64 2)
+  store <16 x i16> %i1, ptr addrspace(1) null, align 32
+  ret void
+}
+
+declare <2 x i16> @llvm.vector.extract.v2i16.v16i16(<16 x i16>, i64 immarg)
+declare <16 x i16> @llvm.vector.insert.v16i16.v2i16(<16 x i16>, <2 x i16>, i64 immarg)