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[RISCV][Docs] Document code generation for vector extension
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Authored by luke on Jan 23 2023, 3:55 AM.



Over the past few weeks I've been documenting my understanding of how code is generated for the vector extension.
I thought it would be useful to solidify this knowledge somewhere, so I have written a document that is largely based off of the original RFC, but updated for the current state of lib/Target/RISCV.

Specifically, it gives a walkthrough of how code is generated for

  • Scalable vectors
  • Fixed-length vectors
  • Vector predication instructions

It may be the case that this documentation is too implementation specific and will get outdated quickly, so let me know if there is a better place to share this knowledge.
And likewise, there may be parts that I'm misunderstanding, so please feel free to correct me!

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luke created this revision.Jan 23 2023, 3:55 AM
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luke requested review of this revision.Jan 23 2023, 3:55 AM
luke edited the summary of this revision. (Show Details)Jan 23 2023, 4:05 AM
luke added inline comments.Jan 23 2023, 4:07 AM

Am I correct in understanding that the main reason for the VL nodes is that it defers having to select an LMUL? Or is there another reason as to why they are used vs just selecting a pseudo instruction directly and using a constant for its VL operand

luke added a comment.Jan 23 2023, 4:08 AM

Rendered PDF

Thanks for kicking this off. Unfortunately I don't have the time right now to give an in-depth review.

I only did a quick review.


VLEN is not limited to 128 bits. It can be 32 or 64.


This mapping also prevents the value of vscale from being examined if ELEN and VLEN are both 32.


This file is also used VP intrinsics for scalable vectors.

Matt added a subscriber: Matt.Feb 6 2023, 9:14 AM
luke added inline comments.Feb 6 2023, 3:02 PM

I'm not sure if I understand, could you clarified by what you mean by examined? Is it related to


This is mentioned in the vector predication section below

luke updated this revision to Diff 495284.EditedFeb 6 2023, 3:14 PM

Add section on standard vector extensions

craig.topper added inline comments.Feb 6 2023, 3:19 PM

We can't use llvm.vscale or ISD:VSCALE if ELEN is 32. See this code in RISCVISelLowering.cpp. Specifically the fatal_error.

case ISD::VSCALE: {
  MVT VT = Op.getSimpleValueType();
  SDLoc DL(Op);
  // We define our scalable vector types for lmul=1 to use a 64 bit known
  // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
  // vscale as VLENB / 8.
  static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
  if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
    report_fatal_error("Support for VLEN==32 is incomplete.");
craig.topper added inline comments.Feb 6 2023, 3:25 PM

Selecting a pseudoinstruction from lowering would be make it difficult to do other optimizations without checking different combinations of pseudoinstruction opcodes.

We can't use the fixed vector types in the isel patterns because the mapping from fixed vector type to LMUL isn't static and isel patterns require the types to be explicitly mentioned in the patterns.

luke added inline comments.Feb 6 2023, 3:39 PM

Thanks, that makes sense.

luke updated this revision to Diff 495299.Feb 6 2023, 3:42 PM

Add note about mapping of types when VLEN=32