MachineIRBuilder: Rename buildMerge. NFC

[rovka]

Summary

buildMerge may build a G_MERGE_VALUES, G_BUILD_VECTOR or
G_CONCAT_VECTORS. Rename it to buildMergeLikeOp.

This is a follow-up suggested in https://reviews.llvm.org/D140964

[foad]

LGTM, thanks!

[rovka]

Thanks for the quick review! I'm going to leave this around until tomorrow, in case anyone wants to bikeshed about the new name.

[aemerson]

Seems perfectly reasonable to me.

[scott.linder]

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

[rovka]

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

Sounds good, thanks :)

[foad]

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

I'm not a huge fan of the "Op" part either, but there is a precedent for it in the GMergeLikeOp wrapper class.

[rovka]

In D141372#4042701, @foad wrote:

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

I'm not a huge fan of the "Op" part either, but there is a precedent for it in the GMergeLikeOp wrapper class.

There could be an argument made that both GMergeLikeOp and buildAssertOp should use Instr instead of Op, too... Should I just rename all of them?

[foad]

In D141372#4042763, @rovka wrote:

In D141372#4042701, @foad wrote:

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

I'm not a huge fan of the "Op" part either, but there is a precedent for it in the GMergeLikeOp wrapper class.

There could be an argument made that both GMergeLikeOp and buildAssertOp should use Instr instead of Op, too... Should I just rename all of them?

I don't mind either way.

[aemerson]

In D141372#4042763, @rovka wrote:

In D141372#4042701, @foad wrote:

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

I'm not a huge fan of the "Op" part either, but there is a precedent for it in the GMergeLikeOp wrapper class.

There could be an argument made that both GMergeLikeOp and buildAssertOp should use Instr instead of Op, too... Should I just rename all of them?

As a separate commit yes that seems fine to me.

[scott.linder]

In D141372#4044590, @aemerson wrote:

In D141372#4042763, @rovka wrote:

In D141372#4042701, @foad wrote:

In D141372#4040553, @scott.linder wrote:

Tiny driveby bikeshed (feel free to ignore): buildMergeLikeInstr? It is longer, but Op seems to more commonly mean "Operand" here (save for some stuff like buildAssertOp).

I'm not a huge fan of the "Op" part either, but there is a precedent for it in the GMergeLikeOp wrapper class.

There could be an argument made that both GMergeLikeOp and buildAssertOp should use Instr instead of Op, too... Should I just rename all of them?

As a separate commit yes that seems fine to me.

+1 to renaming in a pre-patch

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (auto *SrcMerge = dyn_cast<GMerge>(SrcMI)) {
 
         const unsigned NumSrcs = DstSize / MergeSrcSize;
         assert(NumSrcs < SrcMI->getNumOperands() - 1 &&
                "trunc(merge) should require less inputs than merge");
         SmallVector<Register, 8> SrcRegs(NumSrcs);
         for (unsigned i = 0; i < NumSrcs; ++i)
           SrcRegs[i] = SrcMerge->getSourceReg(i);
 
-        Builder.buildMerge(DstReg, SrcRegs);
+        Builder.buildMergeLikeOp(DstReg, SrcRegs);
         UpdatedDefs.push_back(DstReg);
       } else {
         // Unable to combine
         return false;
       }
 
       markInstAndDefDead(MI, *SrcMerge, DeadInsts);
       return true;
bool tryCombineMergeLike(GMergeLikeOp &MI,
               (EltUnmergeIdx != 0))
             return false;
           if (!isSequenceFromUnmerge(MI, i, UnmergeI, 0, NumElts, EltSize))
             return false;
           ConcatSources.push_back(UnmergeI->getSourceReg());
         }
 
         MIB.setInstrAndDebugLoc(MI);
-        MIB.buildMerge(Dst, ConcatSources);
+        MIB.buildMergeLikeOp(Dst, ConcatSources);
         DeadInsts.push_back(&MI);
         return true;
       }
 
       return false;
     }
   };
 
if (NumMergeRegs < NumDefs) {
       const unsigned NumRegs = NumMergeRegs / NumDefs;
       for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
         SmallVector<Register, 8> Regs;
         for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs;
              ++j, ++Idx)
           Regs.push_back(MergeI->getOperand(Idx).getReg());
 
         Register DefReg = MI.getReg(DefIdx);
-        Builder.buildMerge(DefReg, Regs);
+        Builder.buildMergeLikeOp(DefReg, Regs);
         UpdatedDefs.push_back(DefReg);
       }
 
     } else {
       LLT MergeSrcTy = MRI.getType(MergeI->getOperand(1).getReg());
 
       if (!ConvertOp && DestTy != MergeSrcTy)
         ConvertOp = TargetOpcode::G_BITCAST;

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre The entire register \p Res (and no more) must be covered by the input
   ///      registers.
   /// \pre The type of all \p Ops registers must be identical.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction. The
   ///         opcode of the new instruction will depend on the types of both
   ///         the destination and the sources.
-  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
-  MachineInstrBuilder buildMerge(const DstOp &Res,
+  MachineInstrBuilder buildMergeLikeOp(const DstOp &Res,
+                                       ArrayRef<Register> Ops);
+  MachineInstrBuilder buildMergeLikeOp(const DstOp &Res,
                                        std::initializer_list<SrcOp> Ops);
 
   /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
   ///
   /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre The entire register \p Res (and no more) must be covered by the input
   ///      registers.

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

if (LCMTy == LLTy) {
     return B.buildConcatVectors(DstRegs[0], SrcRegs);
   }
 
   // We need to create an unmerge to the result registers, which may require
   // widening the original value.
   Register UnmergeSrcReg;
   if (LCMTy != PartLLT) {
     assert(DstRegs.size() == 1);
-    return B.buildDeleteTrailingVectorElements(DstRegs[0],
-                                               B.buildMerge(LCMTy, SrcRegs));
+    return B.buildDeleteTrailingVectorElements(
+        DstRegs[0], B.buildMergeLikeOp(LCMTy, SrcRegs));
   } else {
     // We don't need to widen anything if we're extracting a scalar which was
     // promoted to a vector e.g. s8 -> v4s8 -> s8
     assert(SrcRegs.size() == 1);
     UnmergeSrcReg = SrcRegs[0];
   }
 
   int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
   }
 
   if (!LLTy.isVector() && !PartLLT.isVector()) {
     assert(OrigRegs.size() == 1);
     LLT OrigTy = MRI.getType(OrigRegs[0]);
 
     unsigned SrcSize = PartLLT.getSizeInBits().getFixedSize() * Regs.size();
     if (SrcSize == OrigTy.getSizeInBits())
-      B.buildMerge(OrigRegs[0], Regs);
+      B.buildMergeLikeOp(OrigRegs[0], Regs);
     else {
-      auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
+      auto Widened = B.buildMergeLikeOp(LLT::scalar(SrcSize), Regs);
       B.buildTrunc(OrigRegs[0], Widened);
     }
 
     return;
   }
 
   if (PartLLT.isVector()) {
     assert(OrigRegs.size() == 1);
if (DstEltTy == PartLLT) {
     // Deal with vector with 64-bit elements decomposed to 32-bit
     // registers. Need to create intermediate 64-bit elements.
     SmallVector<Register, 8> EltMerges;
     int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
 
     assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
 
     for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
-      auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));
+      auto Merge =
+          B.buildMergeLikeOp(RealDstEltTy, Regs.take_front(PartsPerElt));
       // Fix the type in case this is really a vector of pointers.
       MRI.setType(Merge.getReg(0), RealDstEltTy);
       EltMerges.push_back(Merge.getReg(0));
       Regs = Regs.drop_front(PartsPerElt);
     }
 
     B.buildBuildVector(OrigRegs[0], EltMerges);
   } else {
if (SrcTy.isScalar() && DstTy.isScalar()) {
       UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
     } else {
       // Widen to the common type.
       // FIXME: This should respect the extend type
       Register Undef = B.buildUndef(SrcTy).getReg(0);
       SmallVector<Register, 8> MergeParts(1, SrcReg);
       for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
         MergeParts.push_back(Undef);
-      UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
+      UnmergeSrc = B.buildMergeLikeOp(LCMTy, MergeParts).getReg(0);
     }
   }
 
   if (LCMTy.isVector() && CoveringSize != SrcSize)
     UnmergeSrc = B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
 
   B.buildUnmerge(DstRegs, UnmergeSrc);
 }

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

void CombinerHelper::applyCombineShuffleVector(MachineInstr &MI,
                                                const ArrayRef<Register> Ops) {
   Register DstReg = MI.getOperand(0).getReg();
   Builder.setInsertPt(*MI.getParent(), MI);
   Register NewDstReg = MRI.cloneVirtualRegister(DstReg);
 
   if (Ops.size() == 1)
     Builder.buildCopy(NewDstReg, Ops[0]);
   else
-    Builder.buildMerge(NewDstReg, Ops);
+    Builder.buildMergeLikeOp(NewDstReg, Ops);
 
   MI.eraseFromParent();
   replaceRegWith(MRI, DstReg, NewDstReg);
 }
 
 namespace {
 
 /// Select a preference between two uses. CurrentUse is the current preference
if (MI.getOpcode() == TargetOpcode::G_LSHR) {
     //   dst = G_MERGE_VALUES (G_LSHR hi, C - 32), 0
 
     if (NarrowShiftAmt != 0) {
       Narrowed = Builder.buildLShr(HalfTy, Narrowed,
         Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
     }
 
     auto Zero = Builder.buildConstant(HalfTy, 0);
-    Builder.buildMerge(DstReg, { Narrowed, Zero });
+    Builder.buildMergeLikeOp(DstReg, {Narrowed, Zero});
   } else if (MI.getOpcode() == TargetOpcode::G_SHL) {
     Register Narrowed = Unmerge.getReg(0);
     //  dst = G_SHL s64:x, C for C >= 32
     // =>
     //   lo, hi = G_UNMERGE_VALUES x
     //   dst = G_MERGE_VALUES 0, (G_SHL hi, C - 32)
     if (NarrowShiftAmt != 0) {
       Narrowed = Builder.buildShl(HalfTy, Narrowed,
         Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
     }
 
     auto Zero = Builder.buildConstant(HalfTy, 0);
-    Builder.buildMerge(DstReg, { Zero, Narrowed });
+    Builder.buildMergeLikeOp(DstReg, {Zero, Narrowed});
   } else {
     assert(MI.getOpcode() == TargetOpcode::G_ASHR);
     auto Hi = Builder.buildAShr(
       HalfTy, Unmerge.getReg(1),
       Builder.buildConstant(HalfTy, HalfSize - 1));
 
     if (ShiftVal == HalfSize) {
       // (G_ASHR i64:x, 32) ->
       //   G_MERGE_VALUES hi_32(x), (G_ASHR hi_32(x), 31)
-      Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi });
+      Builder.buildMergeLikeOp(DstReg, {Unmerge.getReg(1), Hi});
     } else if (ShiftVal == Size - 1) {
       // Don't need a second shift.
       // (G_ASHR i64:x, 63) ->
       //   %narrowed = (G_ASHR hi_32(x), 31)
       //   G_MERGE_VALUES %narrowed, %narrowed
-      Builder.buildMerge(DstReg, { Hi, Hi });
+      Builder.buildMergeLikeOp(DstReg, {Hi, Hi});
     } else {
       auto Lo = Builder.buildAShr(
         HalfTy, Unmerge.getReg(1),
         Builder.buildConstant(HalfTy, ShiftVal - HalfSize));
 
       // (G_ASHR i64:x, C) ->, for C >= 32
       //   G_MERGE_VALUES (G_ASHR hi_32(x), C - 32), (G_ASHR hi_32(x), 31)
-      Builder.buildMerge(DstReg, { Lo, Hi });
+      Builder.buildMergeLikeOp(DstReg, {Lo, Hi});
     }
   }
 
   MI.eraseFromParent();
 }
 
 bool CombinerHelper::tryCombineShiftToUnmerge(MachineInstr &MI,
                                               unsigned TargetShiftAmount) {

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

void LegalizerHelper::extractVectorParts(Register Reg, unsigned NumElts,
   // elements. Remaining element(s) will be (used to build vector) Leftover.
   SmallVector<Register, 8> Elts;
   extractParts(Reg, EltTy, RegNumElts, Elts);
 
   unsigned Offset = 0;
   // Requested sub-vectors of NarrowTy.
   for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) {
     ArrayRef<Register> Pieces(&Elts[Offset], NumElts);
-    VRegs.push_back(MIRBuilder.buildMerge(NarrowTy, Pieces).getReg(0));
+    VRegs.push_back(MIRBuilder.buildMergeLikeOp(NarrowTy, Pieces).getReg(0));
   }
 
   // Leftover element(s).
   if (LeftoverNumElts == 1) {
     VRegs.push_back(Elts[Offset]);
   } else {
     LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy);
     ArrayRef<Register> Pieces(&Elts[Offset], LeftoverNumElts);
-    VRegs.push_back(MIRBuilder.buildMerge(LeftoverTy, Pieces).getReg(0));
+    VRegs.push_back(MIRBuilder.buildMergeLikeOp(LeftoverTy, Pieces).getReg(0));
   }
 }
 
 void LegalizerHelper::insertParts(Register DstReg,
                                   LLT ResultTy, LLT PartTy,
                                   ArrayRef<Register> PartRegs,
                                   LLT LeftoverTy,
                                   ArrayRef<Register> LeftoverRegs) {
   if (!LeftoverTy.isValid()) {
     assert(LeftoverRegs.empty());
 
     if (!ResultTy.isVector()) {
-      MIRBuilder.buildMerge(DstReg, PartRegs);
+      MIRBuilder.buildMergeLikeOp(DstReg, PartRegs);
       return;
     }
 
     if (PartTy.isVector())
       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
     else
       MIRBuilder.buildBuildVector(DstReg, PartRegs);
     return;
for (unsigned i = 0; i < PartRegs.size() - 1; ++i)
     appendVectorElts(AllElts, PartRegs[i]);
 
   Register Leftover = PartRegs[PartRegs.size() - 1];
   if (MRI.getType(Leftover).isScalar())
     AllElts.push_back(Leftover);
   else
     appendVectorElts(AllElts, Leftover);
 
-  MIRBuilder.buildMerge(DstReg, AllElts);
+  MIRBuilder.buildMergeLikeOp(DstReg, AllElts);
 }
 
 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs.
 static void getUnmergeResults(SmallVectorImpl<Register> &Regs,
                               const MachineInstr &MI) {
   assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
 
   const int StartIdx = Regs.size();
if (AllPadReg) {
       // copies of padding bits.
       Remerge[I] = AllPadReg;
       continue;
     }
 
     if (NumSubParts == 1)
       Remerge[I] = SubMerge[0];
     else
-      Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
+      Remerge[I] = MIRBuilder.buildMergeLikeOp(NarrowTy, SubMerge).getReg(0);
 
     // In the sign extend padding case, re-use the first all-signbit merge.
     if (AllMergePartsArePadding && !AllPadReg)
       AllPadReg = Remerge[I];
   }
 
   VRegs = std::move(Remerge);
   return LCMTy;
 }
 
 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
                                                ArrayRef<Register> RemergeRegs) {
   LLT DstTy = MRI.getType(DstReg);
 
   // Create the merge to the widened source, and extract the relevant bits into
   // the result.
 
   if (DstTy == LCMTy) {
-    MIRBuilder.buildMerge(DstReg, RemergeRegs);
+    MIRBuilder.buildMergeLikeOp(DstReg, RemergeRegs);
     return;
   }
 
-  auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
+  auto Remerge = MIRBuilder.buildMergeLikeOp(LCMTy, RemergeRegs);
   if (DstTy.isScalar() && LCMTy.isScalar()) {
     MIRBuilder.buildTrunc(DstReg, Remerge);
     return;
   }
 
   if (LCMTy.isVector()) {
     unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits();
     SmallVector<Register, 8> UnmergeDefs(NumDefs);
     UnmergeDefs[0] = DstReg;
     for (unsigned I = 1; I != NumDefs; ++I)
       UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy);
 
     MIRBuilder.buildUnmerge(UnmergeDefs,
-                            MIRBuilder.buildMerge(LCMTy, RemergeRegs));
+                            MIRBuilder.buildMergeLikeOp(LCMTy, RemergeRegs));
     return;
   }
 
   llvm_unreachable("unhandled case");
 }
 
 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
 #define RTLIBCASE_INT(LibcallPrefix)                                           \
case TargetOpcode::G_IMPLICIT_DEF: {
 
     SmallVector<Register, 2> DstRegs;
     for (int i = 0; i < NumParts; ++i)
       DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));
 
     if (DstTy.isVector())
       MIRBuilder.buildBuildVector(DstReg, DstRegs);
     else
-      MIRBuilder.buildMerge(DstReg, DstRegs);
+      MIRBuilder.buildMergeLikeOp(DstReg, DstRegs);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_CONSTANT: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
     unsigned TotalSize = Ty.getSizeInBits();
     unsigned NarrowSize = NarrowTy.getSizeInBits();
case TargetOpcode::G_FREEZE: {
 
     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
     SmallVector<Register, 8> Parts;
     for (unsigned i = 0; i < Unmerge->getNumDefs(); ++i) {
       Parts.push_back(
           MIRBuilder.buildFreeze(NarrowTy, Unmerge.getReg(i)).getReg(0));
     }
 
-    MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Parts);
+    MIRBuilder.buildMergeLikeOp(MI.getOperand(0).getReg(), Parts);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
   case TargetOpcode::G_SADDO:
   case TargetOpcode::G_SSUBO:
   case TargetOpcode::G_SADDE:
case TargetOpcode::G_PHI: {
     for (unsigned i = 0; i < NumParts; ++i) {
       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
       MachineInstrBuilder MIB =
           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
     }
     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
-    MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
+    MIRBuilder.buildMergeLikeOp(MI.getOperand(0), DstRegs);
     Observer.changedInstr(MI);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
   case TargetOpcode::G_INSERT_VECTOR_ELT: {
     if (TypeIdx != 2)
       return UnableToLegalize;
for (int i = 0; i < NumParts; ++i) {
                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
                 .getReg(0));
         PartialExtensionReg = DstRegs.back();
       }
     }
 
     // Gather the destination registers into the final destination.
     Register DstReg = MI.getOperand(0).getReg();
-    MIRBuilder.buildMerge(DstReg, DstRegs);
+    MIRBuilder.buildMergeLikeOp(DstReg, DstRegs);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_BSWAP:
   case TargetOpcode::G_BITREVERSE: {
     if (SizeOp0 % NarrowSize != 0)
       return UnableToLegalize;
 
     Observer.changingInstr(MI);
     SmallVector<Register, 2> SrcRegs, DstRegs;
     unsigned NumParts = SizeOp0 / NarrowSize;
     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
 
     for (unsigned i = 0; i < NumParts; ++i) {
       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
                                            {SrcRegs[NumParts - 1 - i]});
       DstRegs.push_back(DstPart.getReg(0));
     }
 
-    MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
+    MIRBuilder.buildMergeLikeOp(MI.getOperand(0), DstRegs);
 
     Observer.changedInstr(MI);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_PTR_ADD:
   case TargetOpcode::G_PTRMASK: {
     if (TypeIdx != 1)
for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
       Unmerges.push_back(UndefReg);
   }
 
   const int PartsPerGCD = WideSize / GCD;
 
   // Build merges of each piece.
   ArrayRef<Register> Slicer(Unmerges);
   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
-    auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
+    auto Merge =
+        MIRBuilder.buildMergeLikeOp(WideTy, Slicer.take_front(PartsPerGCD));
     NewMergeRegs.push_back(Merge.getReg(0));
   }
 
   // A truncate may be necessary if the requested type doesn't evenly divide the
   // original result type.
   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
-    MIRBuilder.buildMerge(DstReg, NewMergeRegs);
+    MIRBuilder.buildMergeLikeOp(DstReg, NewMergeRegs);
   } else {
-    auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
+    auto FinalMerge = MIRBuilder.buildMergeLikeOp(WideDstTy, NewMergeRegs);
     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
   }
 
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
if (PartsPerRemerge == 1) {
 
     SmallVector<Register, 8> RemergeParts;
     for (int I = 0; I != NumDst; ++I) {
       for (int J = 0; J < PartsPerRemerge; ++J) {
         const int Idx = I * PartsPerRemerge + J;
         RemergeParts.emplace_back(Parts[Idx]);
       }
 
-      MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts);
+      MIRBuilder.buildMergeLikeOp(MI.getOperand(I).getReg(), RemergeParts);
       RemergeParts.clear();
     }
   }
 
   MI.eraseFromParent();
   return Legalized;
 }
 
if (DstTy.isVector()) {
       }
 
       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy);
       for (Register &SrcReg : SrcRegs)
         SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0);
     } else
       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy);
 
-    MIRBuilder.buildMerge(Dst, SrcRegs);
+    MIRBuilder.buildMergeLikeOp(Dst, SrcRegs);
     MI.eraseFromParent();
     return Legalized;
   }
 
   if (DstTy.isVector()) {
     SmallVector<Register, 8> SrcRegs;
     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
-    MIRBuilder.buildMerge(Dst, SrcRegs);
+    MIRBuilder.buildMergeLikeOp(Dst, SrcRegs);
     MI.eraseFromParent();
     return Legalized;
   }
 
   return UnableToLegalize;
 }
 
 /// Figure out the bit offset into a register when coercing a vector index for
LegalizerHelper::fewerElementsVectorMultiEltType(
   }
 
   // Merge small outputs into MI's output for each def operand.
   if (NumLeftovers) {
     for (unsigned i = 0; i < NumDefs; ++i)
       mergeMixedSubvectors(MI.getReg(i), OutputRegs[i]);
   } else {
     for (unsigned i = 0; i < NumDefs; ++i)
-      MIRBuilder.buildMerge(MI.getReg(i), OutputRegs[i]);
+      MIRBuilder.buildMergeLikeOp(MI.getReg(i), OutputRegs[i]);
   }
 
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::fewerElementsVectorPhi(GenericMachineInstr &MI,
for (unsigned j = 0; j < NumInputs / 2; ++j) {
       Phi.add(MI.getOperand(1 + j * 2 + 1));
     }
   }
 
   // Merge small outputs into MI's def.
   if (NumLeftovers) {
     mergeMixedSubvectors(MI.getReg(0), OutputRegs);
   } else {
-    MIRBuilder.buildMerge(MI.getReg(0), OutputRegs);
+    MIRBuilder.buildMergeLikeOp(MI.getReg(0), OutputRegs);
   }
 
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
if (TypeIdx == 1) {
     }
 
     SmallVector<Register, 8> NarrowTyElts;
     unsigned NumNarrowTyElts = NarrowTy.getNumElements();
     unsigned NumNarrowTyPieces = DstTy.getNumElements() / NumNarrowTyElts;
     for (unsigned i = 0, Offset = 0; i < NumNarrowTyPieces;
          ++i, Offset += NumNarrowTyElts) {
       ArrayRef<Register> Pieces(&Elts[Offset], NumNarrowTyElts);
-      NarrowTyElts.push_back(MIRBuilder.buildMerge(NarrowTy, Pieces).getReg(0));
+      NarrowTyElts.push_back(
+          MIRBuilder.buildMergeLikeOp(NarrowTy, Pieces).getReg(0));
     }
 
-    MIRBuilder.buildMerge(DstReg, NarrowTyElts);
+    MIRBuilder.buildMergeLikeOp(DstReg, NarrowTyElts);
     MI.eraseFromParent();
     return Legalized;
   }
 
   assert(TypeIdx == 0 && "Bad type index");
   if ((NarrowTy.getSizeInBits() % SrcTy.getSizeInBits() != 0) ||
       (DstTy.getSizeInBits() % NarrowTy.getSizeInBits() != 0))
     return UnableToLegalize;
LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
   SmallVector<Register, 8> NarrowTyElts;
   unsigned NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
   unsigned NumSrcElts = SrcTy.isVector() ? SrcTy.getNumElements() : 1;
   unsigned NumElts = NarrowTy.getNumElements() / NumSrcElts;
   for (unsigned i = 0; i < NumParts; ++i) {
     SmallVector<Register, 8> Sources;
     for (unsigned j = 0; j < NumElts; ++j)
       Sources.push_back(MI.getOperand(1 + i * NumElts + j).getReg());
-    NarrowTyElts.push_back(MIRBuilder.buildMerge(NarrowTy, Sources).getReg(0));
+    NarrowTyElts.push_back(
+        MIRBuilder.buildMergeLikeOp(NarrowTy, Sources).getReg(0));
   }
 
-  MIRBuilder.buildMerge(DstReg, NarrowTyElts);
+  MIRBuilder.buildMergeLikeOp(DstReg, NarrowTyElts);
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
                                                            unsigned TypeIdx,
                                                            LLT NarrowVecTy) {

 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
                                              const LLT HalfTy, const LLT AmtTy) {
 
   Register InL = MRI.createGenericVirtualRegister(HalfTy);
   Register InH = MRI.createGenericVirtualRegister(HalfTy);
   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
 
   if (Amt.isZero()) {
-    MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
+    MIRBuilder.buildMergeLikeOp(MI.getOperand(0), {InL, InH});
     MI.eraseFromParent();
     return Legalized;
   }
 
   LLT NVT = HalfTy;
   unsigned NVTBits = HalfTy.getSizeInBits();
   unsigned VTBits = 2 * NVTBits;
 
if (Amt.ugt(VTBits)) {
       auto OrRHS = MIRBuilder.buildShl(
           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
 
       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
     }
   }
 
-  MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
+  MIRBuilder.buildMergeLikeOp(MI.getOperand(0), {Lo, Hi});
   MI.eraseFromParent();
 
   return Legalized;
 }
 
 // TODO: Optimize if constant shift amount.
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_ASHR: {
     ResultRegs[0] = Lo.getReg(0);
     ResultRegs[1] = Hi.getReg(0);
     break;
   }
   default:
     llvm_unreachable("not a shift");
   }
 
-  MIRBuilder.buildMerge(DstReg, ResultRegs);
+  MIRBuilder.buildMergeLikeOp(DstReg, ResultRegs);
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
                                        LLT MoreTy) {
   assert(TypeIdx == 0 && "Expecting only Idx 0");
LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
   SmallVector<Register, 2> Src1Parts, Src2Parts;
   SmallVector<Register, 2> DstTmpRegs(DstTmpParts);
   extractParts(Src1, NarrowTy, NumParts, Src1Parts);
   extractParts(Src2, NarrowTy, NumParts, Src2Parts);
   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
 
   // Take only high half of registers if this is high mul.
   ArrayRef<Register> DstRegs(&DstTmpRegs[DstTmpParts - NumParts], NumParts);
-  MIRBuilder.buildMerge(DstReg, DstRegs);
+  MIRBuilder.buildMergeLikeOp(DstReg, DstRegs);
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx,
                                    LLT NarrowTy) {
   if (TypeIdx != 0)
for (int i = 0; i < NumParts; ++i) {
 
     DstRegs.push_back(SegReg);
   }
 
   Register DstReg = MI.getOperand(0).getReg();
   if (MRI.getType(DstReg).isVector())
     MIRBuilder.buildBuildVector(DstReg, DstRegs);
   else if (DstRegs.size() > 1)
-    MIRBuilder.buildMerge(DstReg, DstRegs);
+    MIRBuilder.buildMergeLikeOp(DstReg, DstRegs);
   else
     MIRBuilder.buildCopy(DstReg, DstRegs[0]);
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
for (int I = 0, E = SrcRegs.size(); I != E; ++I) {
     MIRBuilder.buildInsert(DstReg, SrcReg, SegReg, InsertOffset);
     DstRegs.push_back(DstReg);
   }
 
   uint64_t WideSize = DstRegs.size() * NarrowSize;
   Register DstReg = MI.getOperand(0).getReg();
   if (WideSize > RegTy.getSizeInBits()) {
     Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize));
-    MIRBuilder.buildMerge(MergeReg, DstRegs);
+    MIRBuilder.buildMergeLikeOp(MergeReg, DstRegs);
     MIRBuilder.buildTrunc(DstReg, MergeReg);
   } else
-    MIRBuilder.buildMerge(DstReg, DstRegs);
+    MIRBuilder.buildMergeLikeOp(DstReg, DstRegs);
 
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
                                    LLT NarrowTy) {
LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) {
 
   int64_t IdxVal;
   if (mi_match(Idx, MRI, m_ICst(IdxVal)) && IdxVal <= NumElts) {
     SmallVector<Register, 8> SrcRegs;
     extractParts(SrcVec, EltTy, NumElts, SrcRegs);
 
     if (InsertVal) {
       SrcRegs[IdxVal] = MI.getOperand(2).getReg();
-      MIRBuilder.buildMerge(DstReg, SrcRegs);
+      MIRBuilder.buildMergeLikeOp(DstReg, SrcRegs);
     } else {
       MIRBuilder.buildCopy(DstReg, SrcRegs[IdxVal]);
     }
 
     MI.eraseFromParent();
     return Legalized;
   }
 
if ((Offset % SrcEltSize == 0) && (DstSize % SrcEltSize == 0) &&
       SmallVector<Register, 8> SubVectorElts;
       for (unsigned Idx = Offset / SrcEltSize;
            Idx < (Offset + DstSize) / SrcEltSize; ++Idx) {
         SubVectorElts.push_back(Unmerge.getReg(Idx));
       }
       if (SubVectorElts.size() == 1)
         MIRBuilder.buildCopy(Dst, SubVectorElts[0]);
       else
-        MIRBuilder.buildMerge(Dst, SubVectorElts);
+        MIRBuilder.buildMergeLikeOp(Dst, SubVectorElts);
 
       MI.eraseFromParent();
       return Legalized;
     }
   }
 
   if (DstTy.isScalar() &&
       (SrcTy.isScalar() ||
if ((Offset % EltSize == 0) && (InsertSize % EltSize == 0) &&
         ++Idx;
       }
 
       // Remaining elements from Src after insert
       for (; Idx < DstTy.getNumElements(); ++Idx) {
         DstElts.push_back(UnmergeSrc.getReg(Idx));
       }
 
-      MIRBuilder.buildMerge(Dst, DstElts);
+      MIRBuilder.buildMergeLikeOp(Dst, DstElts);
       MI.eraseFromParent();
       return Legalized;
     }
   }
 
   if (InsertTy.isVector() ||
       (DstTy.isVector() && DstTy.getElementType() != InsertTy))
     return UnableToLegalize;

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

MachineIRBuilder::buildPadVectorWithUndefElements(const DstOp &Res,
   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
   SmallVector<Register, 8> Regs;
   for (auto Op : Unmerge.getInstr()->defs())
     Regs.push_back(Op.getReg());
   Register Undef = buildUndef(Op0Ty.getElementType()).getReg(0);
   unsigned NumberOfPadElts = ResTy.getNumElements() - Regs.size();
   for (unsigned i = 0; i < NumberOfPadElts; ++i)
     Regs.push_back(Undef);
-  return buildMerge(Res, Regs);
+  return buildMergeLikeOp(Res, Regs);
 }
 
 MachineInstrBuilder
 MachineIRBuilder::buildDeleteTrailingVectorElements(const DstOp &Res,
                                                     const SrcOp &Op0) {
   LLT ResTy = Res.getLLTTy(*getMRI());
   LLT Op0Ty = Op0.getLLTTy(*getMRI());
 
   assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
   assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
          "Different vector element types");
   assert((ResTy.getNumElements() < Op0Ty.getNumElements()) &&
          "Op0 has fewer elements");
 
   SmallVector<Register, 8> Regs;
   auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
   for (unsigned i = 0; i < ResTy.getNumElements(); ++i)
     Regs.push_back(Unmerge.getReg(i));
-  return buildMerge(Res, Regs);
+  return buildMergeLikeOp(Res, Regs);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
   return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
 }
 
 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
   assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
#endif
   Extract.addImm(Index);
   return Extract;
 }
 
 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
 }
 
-MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
+MachineInstrBuilder MachineIRBuilder::buildMergeLikeOp(const DstOp &Res,
                                                        ArrayRef<Register> Ops) {
   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
   // we need some temporary storage for the DstOp objects. Here we use a
   // sufficiently large SmallVector to not go through the heap.
   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
   assert(TmpVec.size() > 1);
   return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
 }
 
 MachineInstrBuilder
-MachineIRBuilder::buildMerge(const DstOp &Res,
+MachineIRBuilder::buildMergeLikeOp(const DstOp &Res,
                                    std::initializer_list<SrcOp> Ops) {
   assert(Ops.size() > 1);
   return buildInstr(getOpcodeForMerge(Res, Ops), Res, Ops);
 }
 
 unsigned MachineIRBuilder::getOpcodeForMerge(const DstOp &DstOp,
                                              ArrayRef<SrcOp> SrcOps) const {
   if (DstOp.getLLTTy(*getMRI()).isVector()) {
     if (SrcOps[0].getLLTTy(*getMRI()).isVector())

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
                 // We don't handle VA types which are not exactly twice the
                 // size, but can easily be done in future.
                 if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
                   LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
                   return false;
                 }
                 auto Undef = MIRBuilder.buildUndef({OldLLT});
                 CurVReg =
-                    MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
+                    MIRBuilder.buildMergeLikeOp({NewLLT}, {CurVReg, Undef})
+                        .getReg(0);
               } else {
                 // Just do a vector extend.
                 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
                               .getReg(0);
               }
             } else if (NewLLT.getNumElements() == 2) {
               // We need to pad a <1 x S> type to <2 x S>. Since we don't have
               // <1 x S> vector types in GISel we use a build_vector instead

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

assert((*MI.memoperands_begin())->getSuccessOrdering() ==
                AtomicOrdering::Monotonic ||
            (*MI.memoperands_begin())->getSuccessOrdering() ==
                AtomicOrdering::Unordered);
     assert(ST->hasLSE2() && "ldp/stp not single copy atomic without +lse2");
     LLT s64 = LLT::scalar(64);
     MachineInstrBuilder NewI;
     if (MI.getOpcode() == TargetOpcode::G_LOAD) {
       NewI = MIRBuilder.buildInstr(AArch64::LDPXi, {s64, s64}, {});
-      MIRBuilder.buildMerge(ValReg, {NewI->getOperand(0), NewI->getOperand(1)});
+      MIRBuilder.buildMergeLikeOp(ValReg,
+                                  {NewI->getOperand(0), NewI->getOperand(1)});
     } else {
       auto Split = MIRBuilder.buildUnmerge(s64, MI.getOperand(0));
       NewI = MIRBuilder.buildInstr(
           AArch64::STPXi, {}, {Split->getOperand(0), Split->getOperand(1)});
     }
     Register Base;
     int Offset;
     matchLDPSTPAddrMode(MI.getOperand(1).getReg(), Base, Offset, MRI);
CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch},
                                  NewI->getOperand(1)});
   }
 
   CAS.cloneMemRefs(MI);
   constrainSelectedInstRegOperands(*CAS, *ST->getInstrInfo(),
                                    *MRI.getTargetRegisterInfo(),
                                    *ST->getRegBankInfo());
 
-  MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi});
+  MIRBuilder.buildMergeLikeOp(MI.getOperand(0), {DstLo, DstHi});
   MI.eraseFromParent();
   return true;
 }
 
 bool AArch64LegalizerInfo::legalizeCTTZ(MachineInstr &MI,
                                         LegalizerHelper &Helper) const {
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

if (DestAS == AMDGPUAS::FLAT_ADDRESS &&
     if (!ApertureReg.isValid())
       return false;
 
     // Coerce the type of the low half of the result so we can use merge_values.
     Register SrcAsInt = B.buildPtrToInt(S32, Src).getReg(0);
 
     // TODO: Should we allow mismatched types but matching sizes in merges to
     // avoid the ptrtoint?
-    auto BuildPtr = B.buildMerge(DstTy, {SrcAsInt, ApertureReg});
+    auto BuildPtr = B.buildMergeLikeOp(DstTy, {SrcAsInt, ApertureReg});
 
     if (isKnownNonNull(Src, MRI, TM, SrcAS)) {
       B.buildCopy(Dst, BuildPtr);
       MI.eraseFromParent();
       return true;
     }
 
     auto SegmentNull = B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
   }
 
   if (SrcAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
       DstTy.getSizeInBits() == 64) {
     const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
     uint32_t AddrHiVal = Info->get32BitAddressHighBits();
     auto PtrLo = B.buildPtrToInt(S32, Src);
     auto HighAddr = B.buildConstant(S32, AddrHiVal);
-    B.buildMerge(Dst, {PtrLo, HighAddr});
+    B.buildMergeLikeOp(Dst, {PtrLo, HighAddr});
     MI.eraseFromParent();
     return true;
   }
 
   DiagnosticInfoUnsupported InvalidAddrSpaceCast(
       MF.getFunction(), "invalid addrspacecast", B.getDebugLoc());
 
   LLVMContext &Ctx = MF.getFunction().getContext();
bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc(
   const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31);
   auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
 
   const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
 
   const auto Zero32 = B.buildConstant(S32, 0);
 
   // Extend back to 64-bits.
-  auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit});
+  auto SignBit64 = B.buildMergeLikeOp(S64, {Zero32, SignBit});
 
   auto Shr = B.buildAShr(S64, FractMask, Exp);
   auto Not = B.buildNot(S64, Shr);
   auto Tmp0 = B.buildAnd(S64, Src, Not);
   auto FiftyOne = B.buildConstant(S32, FractBits - 1);
 
   auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32);
   auto ExpGt51 = B.buildICmp(CmpInst::ICMP_SGT, S1, Exp, FiftyOne);
bool AMDGPULegalizerInfo::legalizeFPTOI(MachineInstr &MI,
   auto Fma = B.buildFMA(SrcLT, FloorMul, K1, Trunc, Flags);
 
   auto Hi = (Signed && SrcLT == S64) ? B.buildFPTOSI(S32, FloorMul)
                                      : B.buildFPTOUI(S32, FloorMul);
   auto Lo = B.buildFPTOUI(S32, Fma);
 
   if (Signed && SrcLT == S32) {
     // Flip the result based on the signedness, which is either all 0s or 1s.
-    Sign = B.buildMerge(S64, {Sign, Sign});
+    Sign = B.buildMergeLikeOp(S64, {Sign, Sign});
     // r := xor({lo, hi}, sign) - sign;
-    B.buildSub(Dst, B.buildXor(S64, B.buildMerge(S64, {Lo, Hi}), Sign), Sign);
+    B.buildSub(Dst, B.buildXor(S64, B.buildMergeLikeOp(S64, {Lo, Hi}), Sign),
+               Sign);
   } else
-    B.buildMerge(Dst, {Lo, Hi});
+    B.buildMergeLikeOp(Dst, {Lo, Hi});
   MI.eraseFromParent();
 
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
                                                MachineInstr &MI) const {
   MachineFunction &MF = Helper.MIRBuilder.getMF();
bool AMDGPULegalizerInfo::legalizeInsertVectorElt(
   unsigned NumElts = VecTy.getNumElements();
   if (IdxVal < NumElts) {
     SmallVector<Register, 8> SrcRegs;
     for (unsigned i = 0; i < NumElts; ++i)
       SrcRegs.push_back(MRI.createGenericVirtualRegister(EltTy));
     B.buildUnmerge(SrcRegs, Vec);
 
     SrcRegs[IdxVal] = MI.getOperand(2).getReg();
-    B.buildMerge(Dst, SrcRegs);
+    B.buildMergeLikeOp(Dst, SrcRegs);
   } else {
     B.buildUndef(Dst);
   }
 
   MI.eraseFromParent();
   return true;
 }
 
bool AMDGPULegalizerInfo::legalizeBuildVector(
   Register Src1 = MI.getOperand(2).getReg();
 
   if (MI.getOpcode() == AMDGPU::G_BUILD_VECTOR_TRUNC) {
     assert(MRI.getType(Src0) == S32);
     Src0 = B.buildTrunc(S16, MI.getOperand(1).getReg()).getReg(0);
     Src1 = B.buildTrunc(S16, MI.getOperand(2).getReg()).getReg(0);
   }
 
-  auto Merge = B.buildMerge(S32, {Src0, Src1});
+  auto Merge = B.buildMergeLikeOp(S32, {Src0, Src1});
   B.buildBitcast(Dst, Merge);
 
   MI.eraseFromParent();
   return true;
 }
 
 // Build a big integer multiply or multiply-add using MAD_64_32 instructions.
 //
auto buildMadChain =
           bool HaveSmallAccum = false;
           Register Tmp;
 
           if (LocalAccum[0]) {
             if (LocalAccum.size() == 1) {
               Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0);
               HaveSmallAccum = true;
             } else if (LocalAccum[1]) {
-              Tmp = B.buildMerge(S64, LocalAccum).getReg(0);
+              Tmp = B.buildMergeLikeOp(S64, LocalAccum).getReg(0);
               HaveSmallAccum = false;
             } else {
               Tmp = B.buildZExt(S64, LocalAccum[0]).getReg(0);
               HaveSmallAccum = true;
             }
           } else {
             assert(LocalAccum.size() == 1 || !LocalAccum[1]);
             Tmp = getZero64();
bool AMDGPULegalizerInfo::legalizeMul(LegalizerHelper &Helper,
   }
   B.buildUnmerge(Src0Parts, Src0);
   B.buildUnmerge(Src1Parts, Src1);
 
   SmallVector<Register, 2> AccumRegs(NumParts);
   buildMultiply(Helper, AccumRegs, Src0Parts, Src1Parts, UsePartialMad64_32,
                 SeparateOddAlignedProducts);
 
-  B.buildMerge(DstReg, AccumRegs);
+  B.buildMergeLikeOp(DstReg, AccumRegs);
   MI.eraseFromParent();
   return true;
 
 }
 
 // Legalize ctlz/cttz to ffbh/ffbl instead of the default legalization to
 // ctlz/cttz_zero_undef. This allows us to fix up the result for the zero input
 // case with a single min instruction instead of a compare+select.
void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B,
                                                         Register Denom) const {
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   const LLT S1 = LLT::scalar(1);
   Register RcpLo, RcpHi;
 
   std::tie(RcpLo, RcpHi) = emitReciprocalU64(B, Denom);
 
-  auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi});
+  auto Rcp = B.buildMergeLikeOp(S64, {RcpLo, RcpHi});
 
   auto Zero64 = B.buildConstant(S64, 0);
   auto NegDenom = B.buildSub(S64, Zero64, Denom);
 
   auto MulLo1 = B.buildMul(S64, NegDenom, Rcp);
   auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1);
 
   auto UnmergeMulHi1 = B.buildUnmerge(S32, MulHi1);
   Register MulHi1_Lo = UnmergeMulHi1.getReg(0);
   Register MulHi1_Hi = UnmergeMulHi1.getReg(1);
 
   auto Add1_Lo = B.buildUAddo(S32, S1, RcpLo, MulHi1_Lo);
   auto Add1_Hi = B.buildUAdde(S32, S1, RcpHi, MulHi1_Hi, Add1_Lo.getReg(1));
-  auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi});
+  auto Add1 = B.buildMergeLikeOp(S64, {Add1_Lo, Add1_Hi});
 
   auto MulLo2 = B.buildMul(S64, NegDenom, Add1);
   auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2);
   auto UnmergeMulHi2 = B.buildUnmerge(S32, MulHi2);
   Register MulHi2_Lo = UnmergeMulHi2.getReg(0);
   Register MulHi2_Hi = UnmergeMulHi2.getReg(1);
 
   auto Zero32 = B.buildConstant(S32, 0);
   auto Add2_Lo = B.buildUAddo(S32, S1, Add1_Lo, MulHi2_Lo);
   auto Add2_Hi = B.buildUAdde(S32, S1, Add1_Hi, MulHi2_Hi, Add2_Lo.getReg(1));
-  auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi});
+  auto Add2 = B.buildMergeLikeOp(S64, {Add2_Lo, Add2_Hi});
 
   auto UnmergeNumer = B.buildUnmerge(S32, Numer);
   Register NumerLo = UnmergeNumer.getReg(0);
   Register NumerHi = UnmergeNumer.getReg(1);
 
   auto MulHi3 = B.buildUMulH(S64, Numer, Add2);
   auto Mul3 = B.buildMul(S64, Denom, MulHi3);
   auto UnmergeMul3 = B.buildUnmerge(S32, Mul3);
   Register Mul3_Lo = UnmergeMul3.getReg(0);
   Register Mul3_Hi = UnmergeMul3.getReg(1);
   auto Sub1_Lo = B.buildUSubo(S32, S1, NumerLo, Mul3_Lo);
   auto Sub1_Hi = B.buildUSube(S32, S1, NumerHi, Mul3_Hi, Sub1_Lo.getReg(1));
   auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi);
-  auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi});
+  auto Sub1 = B.buildMergeLikeOp(S64, {Sub1_Lo, Sub1_Hi});
 
   auto UnmergeDenom = B.buildUnmerge(S32, Denom);
   Register DenomLo = UnmergeDenom.getReg(0);
   Register DenomHi = UnmergeDenom.getReg(1);
 
   auto CmpHi = B.buildICmp(CmpInst::ICMP_UGE, S1, Sub1_Hi, DenomHi);
   auto C1 = B.buildSExt(S32, CmpHi);
 
   auto CmpLo = B.buildICmp(CmpInst::ICMP_UGE, S1, Sub1_Lo, DenomLo);
   auto C2 = B.buildSExt(S32, CmpLo);
 
   auto CmpEq = B.buildICmp(CmpInst::ICMP_EQ, S1, Sub1_Hi, DenomHi);
   auto C3 = B.buildSelect(S32, CmpEq, C2, C1);
 
   // TODO: Here and below portions of the code can be enclosed into if/endif.
   // Currently control flow is unconditional and we have 4 selects after
   // potential endif to substitute PHIs.
 
   // if C3 != 0 ...
   auto Sub2_Lo = B.buildUSubo(S32, S1, Sub1_Lo, DenomLo);
   auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1));
   auto Sub2_Hi = B.buildUSube(S32, S1, Sub2_Mi, Zero32, Sub2_Lo.getReg(1));
-  auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi});
+  auto Sub2 = B.buildMergeLikeOp(S64, {Sub2_Lo, Sub2_Hi});
 
   auto One64 = B.buildConstant(S64, 1);
   auto Add3 = B.buildAdd(S64, MulHi3, One64);
 
   auto C4 =
       B.buildSExt(S32, B.buildICmp(CmpInst::ICMP_UGE, S1, Sub2_Hi, DenomHi));
   auto C5 =
       B.buildSExt(S32, B.buildICmp(CmpInst::ICMP_UGE, S1, Sub2_Lo, DenomLo));
   auto C6 = B.buildSelect(
       S32, B.buildICmp(CmpInst::ICMP_EQ, S1, Sub2_Hi, DenomHi), C5, C4);
 
   // if (C6 != 0)
   auto Add4 = B.buildAdd(S64, Add3, One64);
   auto Sub3_Lo = B.buildUSubo(S32, S1, Sub2_Lo, DenomLo);
 
   auto Sub3_Mi = B.buildUSube(S32, S1, Sub2_Mi, DenomHi, Sub2_Lo.getReg(1));
   auto Sub3_Hi = B.buildUSube(S32, S1, Sub3_Mi, Zero32, Sub3_Lo.getReg(1));
-  auto Sub3 = B.buildMerge(S64, {Sub3_Lo, Sub3_Hi});
+  auto Sub3 = B.buildMergeLikeOp(S64, {Sub3_Lo, Sub3_Hi});
 
   // endif C6
   // endif C3
 
   if (DstDivReg) {
     auto Sel1 = B.buildSelect(
         S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Add4, Add3);
     B.buildSelect(DstDivReg, B.buildICmp(CmpInst::ICMP_NE, S1, C3, Zero32),
if (NumValueDWords == 1) {
       B.buildUnmerge({Dst, StatusDst}, LoadDstReg);
     } else {
       SmallVector<Register, 5> LoadElts;
       for (unsigned I = 0; I != NumValueDWords; ++I)
         LoadElts.push_back(B.getMRI()->createGenericVirtualRegister(S32));
       LoadElts.push_back(StatusDst);
       B.buildUnmerge(LoadElts, LoadDstReg);
       LoadElts.truncate(NumValueDWords);
-      B.buildMerge(Dst, LoadElts);
+      B.buildMergeLikeOp(Dst, LoadElts);
     }
   } else if ((!IsD16 && MemTy.getSizeInBits() < 32) ||
              (IsD16 && !Ty.isVector())) {
     Register LoadDstReg = B.getMRI()->createGenericVirtualRegister(S32);
     buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset,
                     Format, AuxiliaryData, MMO, IsTyped, HasVIndex, B);
     B.setInsertPt(B.getMBB(), ++B.getInsertPt());
     B.buildTrunc(Dst, LoadDstReg);
   } else if (Unpacked && IsD16 && Ty.isVector()) {
     LLT UnpackedTy = Ty.changeElementSize(32);
     Register LoadDstReg = B.getMRI()->createGenericVirtualRegister(UnpackedTy);
     buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset,
                     Format, AuxiliaryData, MMO, IsTyped, HasVIndex, B);
     B.setInsertPt(B.getMBB(), ++B.getInsertPt());
     // FIXME: G_TRUNC should work, but legalization currently fails
     auto Unmerge = B.buildUnmerge(S32, LoadDstReg);
     SmallVector<Register, 4> Repack;
     for (unsigned I = 0, N = Unmerge->getNumOperands() - 1; I != N; ++I)
       Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0));
-    B.buildMerge(Dst, Repack);
+    B.buildMergeLikeOp(Dst, Repack);
   } else {
     buildBufferLoad(Opc, Dst, RSrc, VIndex, VOffset, SOffset, ImmOffset, Format,
                     AuxiliaryData, MMO, IsTyped, HasVIndex, B);
   }
 
   MI.eraseFromParent();
   return true;
 }
Opcode = AMDGPU::getMIMGOpcode(
         NumVDataDwords, NumVAddrDwords);
   }
   assert(Opcode != -1);
 
   SmallVector<Register, 12> Ops;
   if (UseNSA && IsGFX11Plus) {
     auto packLanes = [&Ops, &S32, &V3S32, &B](Register Src) {
       auto Unmerge = B.buildUnmerge({S32, S32, S32}, Src);
-      auto Merged = B.buildMerge(
+      auto Merged = B.buildMergeLikeOp(
           V3S32, {Unmerge.getReg(0), Unmerge.getReg(1), Unmerge.getReg(2)});
       Ops.push_back(Merged.getReg(0));
     };
 
     Ops.push_back(NodePtr);
     Ops.push_back(RayExtent);
     packLanes(RayOrigin);
 
     if (IsA16) {
       auto UnmergeRayDir = B.buildUnmerge({S16, S16, S16}, RayDir);
       auto UnmergeRayInvDir = B.buildUnmerge({S16, S16, S16}, RayInvDir);
-      auto MergedDir = B.buildMerge(
+      auto MergedDir = B.buildMergeLikeOp(
           V3S32,
-          {B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(0),
+          {B.buildBitcast(S32,
+                          B.buildMergeLikeOp(V2S16, {UnmergeRayInvDir.getReg(0),
                                                      UnmergeRayDir.getReg(0)}))
                .getReg(0),
-           B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(1),
+           B.buildBitcast(S32,
+                          B.buildMergeLikeOp(V2S16, {UnmergeRayInvDir.getReg(1),
                                                      UnmergeRayDir.getReg(1)}))
                .getReg(0),
-           B.buildBitcast(S32, B.buildMerge(V2S16, {UnmergeRayInvDir.getReg(2),
+           B.buildBitcast(S32,
+                          B.buildMergeLikeOp(V2S16, {UnmergeRayInvDir.getReg(2),
                                                      UnmergeRayDir.getReg(2)}))
                .getReg(0)});
       Ops.push_back(MergedDir.getReg(0));
     } else {
       packLanes(RayDir);
       packLanes(RayInvDir);
     }
   } else {
     if (Is64) {
if (UseNSA && IsGFX11Plus) {
 
     packLanes(RayOrigin);
     if (IsA16) {
       auto UnmergeRayDir = B.buildUnmerge({S16, S16, S16}, RayDir);
       auto UnmergeRayInvDir = B.buildUnmerge({S16, S16, S16}, RayInvDir);
       Register R1 = MRI.createGenericVirtualRegister(S32);
       Register R2 = MRI.createGenericVirtualRegister(S32);
       Register R3 = MRI.createGenericVirtualRegister(S32);
-      B.buildMerge(R1, {UnmergeRayDir.getReg(0), UnmergeRayDir.getReg(1)});
-      B.buildMerge(R2, {UnmergeRayDir.getReg(2), UnmergeRayInvDir.getReg(0)});
-      B.buildMerge(R3,
-                   {UnmergeRayInvDir.getReg(1), UnmergeRayInvDir.getReg(2)});
+      B.buildMergeLikeOp(R1,
+                         {UnmergeRayDir.getReg(0), UnmergeRayDir.getReg(1)});
+      B.buildMergeLikeOp(R2,
+                         {UnmergeRayDir.getReg(2), UnmergeRayInvDir.getReg(0)});
+      B.buildMergeLikeOp(
+          R3, {UnmergeRayInvDir.getReg(1), UnmergeRayInvDir.getReg(2)});
       Ops.push_back(R1);
       Ops.push_back(R2);
       Ops.push_back(R3);
     } else {
       packLanes(RayDir);
       packLanes(RayInvDir);
     }
   }
 
   if (!UseNSA) {
     // Build a single vector containing all the operands so far prepared.
     LLT OpTy = LLT::fixed_vector(Ops.size(), 32);
-    Register MergedOps = B.buildMerge(OpTy, Ops).getReg(0);
+    Register MergedOps = B.buildMergeLikeOp(OpTy, Ops).getReg(0);
     Ops.clear();
     Ops.push_back(MergedOps);
   }
 
   auto MIB = B.buildInstr(AMDGPU::G_AMDGPU_INTRIN_BVH_INTERSECT_RAY)
     .addDef(DstReg)
     .addImm(Opcode);
 

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

for (unsigned i = 0; i < NumParts; ++i) {
     B.buildInstr(AMDGPU::V_READFIRSTLANE_B32, {DstPart}, {SrcPart});
 
     DstParts.push_back(DstPart);
   }
 
   if (Bits == 32)
     return DstParts[0];
 
-  Register Dst = B.buildMerge(Ty, DstParts).getReg(0);
+  Register Dst = B.buildMergeLikeOp(Ty, DstParts).getReg(0);
   MRI.setRegBank(Dst, AMDGPU::SGPRRegBank);
   return Dst;
 }
 
 /// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs. If
 /// any of the required SGPR operands are VGPRs, perform a waterfall loop to
 /// execute the instruction for each unique combination of values in all lanes
 /// in the wave. The block will be split such that rest of the instructions are
if (RSrcBank != &AMDGPU::SGPRRegBank) {
     executeInWaterfallLoop(B, make_range(Span.begin(), Span.end()),
                            OpsToWaterfall, MRI);
   }
 
   if (NumLoads != 1) {
     if (Ty.isVector())
       B.buildConcatVectors(Dst, LoadParts);
     else
-      B.buildMerge(Dst, LoadParts);
+      B.buildMergeLikeOp(Dst, LoadParts);
   }
 
   // We removed the instruction earlier with a waterfall loop.
   if (RSrcBank == &AMDGPU::SGPRRegBank)
     MI.eraseFromParent();
 
   return true;
 }
if (auto ConstWidth = getIConstantVRegValWithLookThrough(WidthReg, MRI)) {
       if (WidthImm <= 32) {
         // Use bitfield extract on the lower 32-bit source, and then sign-extend
         // or clear the upper 32-bits.
         auto Extract =
             Signed ? B.buildSbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg)
                    : B.buildUbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg);
         auto Extend =
             Signed ? B.buildAShr(S32, Extract, B.buildConstant(S32, 31)) : Zero;
-        B.buildMerge(DstReg, {Extract, Extend});
+        B.buildMergeLikeOp(DstReg, {Extract, Extend});
       } else {
         // Use bitfield extract on upper 32-bit source, and combine with lower
         // 32-bit source.
         auto UpperWidth = B.buildConstant(S32, WidthImm - 32);
         auto Extract =
             Signed
                 ? B.buildSbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth)
                 : B.buildUbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth);
-        B.buildMerge(DstReg, {UnmergeSOffset.getReg(0), Extract});
+        B.buildMergeLikeOp(DstReg, {UnmergeSOffset.getReg(0), Extract});
       }
       MI.eraseFromParent();
       return true;
     }
 
     // Expand to Src >> Offset << (64 - Width) >> (64 - Width) using 64-bit
     // operations.
     auto ExtShift = B.buildSub(S32, B.buildConstant(S32, 64), WidthReg);
if (Accumulate) {
     }
   } else {
     if (IsUnsigned) {
       Carry = B.buildConstant(CarryType, 0).getReg(0);
       MRI.setRegBank(Carry, CarryBank);
     }
   }
 
-  B.buildMerge(Dst0, {DstLo, DstHi});
+  B.buildMergeLikeOp(Dst0, {DstLo, DstHi});
 
   if (DstOnValu) {
     B.buildCopy(Dst1, Carry);
   } else {
     B.buildTrunc(Dst1, Carry);
   }
 
   MI.eraseFromParent();
Register AMDGPURegisterBankInfo::handleD16VData(MachineIRBuilder &B,
 
   SmallVector<Register, 4> WideRegs;
   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
     WideRegs.push_back(Unmerge.getReg(I));
 
   const LLT S32 = LLT::scalar(32);
   int NumElts = StoreVT.getNumElements();
 
-  return B.buildMerge(LLT::fixed_vector(NumElts, S32), WideRegs).getReg(0);
+  return B.buildMergeLikeOp(LLT::fixed_vector(NumElts, S32), WideRegs)
+      .getReg(0);
 }
 
 static std::pair<Register, unsigned>
 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
   int64_t Const;
   if (mi_match(Reg, MRI, m_ICst(Const)))
     return std::pair(Register(), Const);
 

llvm/lib/Target/ARM/ARMCallLowering.cpp

unsigned assignCustomValue(ARMCallLowering::ArgInfo &Arg,
 
     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
 
     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
     if (!IsLittle)
       std::swap(NewRegs[0], NewRegs[1]);
 
-    MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
+    MIRBuilder.buildMergeLikeOp(Arg.Regs[0], NewRegs);
 
     return 1;
   }
 
   /// Marking a physical register as used is different between formal
   /// parameters, where it's a basic block live-in, and call returns, where it's
   /// an implicit-def of the call instruction.
   virtual void markPhysRegUsed(unsigned PhysReg) = 0;

llvm/lib/Target/Mips/MipsCallLowering.cpp

MipsIncomingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg,
 
   auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg());
   auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg());
   if (!STI.isLittle())
     std::swap(CopyLo, CopyHi);
 
   Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
   Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) };
-  MIRBuilder.buildMerge(Arg.OrigRegs[0], {CopyLo, CopyHi});
+  MIRBuilder.buildMergeLikeOp(Arg.OrigRegs[0], {CopyLo, CopyHi});
 
   markPhysRegUsed(VALo.getLocReg());
   markPhysRegUsed(VAHi.getLocReg());
   return 2;
 }
 
 namespace {
 class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

if (MI.getOpcode() == G_LOAD) {
       } else {
         auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize);
         auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize);
 
         auto Load_P2Half = MIRBuilder.buildLoad(s32, BaseAddr, *P2HalfMemOp);
         auto Load_Rem = MIRBuilder.buildLoad(s32, Addr, *RemMemOp);
 
         if (Size == 64)
-          MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem});
+          MIRBuilder.buildMergeLikeOp(Val, {Load_P2Half, Load_Rem});
         else {
-          auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem});
+          auto Merge =
+              MIRBuilder.buildMergeLikeOp(s64, {Load_P2Half, Load_Rem});
           MIRBuilder.buildTrunc(Val, Merge);
         }
       }
     }
     MI.eraseFromParent();
     break;
   }
   case G_UITOFP: {
case G_UITOFP: {
     // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
     // unsigned to double. Mantissa has 52 bits so we use following trick:
     // First make floating point bit mask 0x43300000ABCDEFGH.
     // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
     // Next, subtract  2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
     // Done. Trunc double to float if needed.
 
     auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000));
-    auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)});
+    auto Bitcast = MIRBuilder.buildMergeLikeOp(s64, {Src, C_HiMask.getReg(0)});
 
     MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
         s64, BitsToDouble(UINT64_C(0x4330000000000000)));
 
     if (DstTy == s64)
       MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
     else {
       MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);

llvm/lib/Target/X86/X86CallLowering.cpp

if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
 
     X86OutgoingValueAssigner Assigner(RetCC_X86);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB);
     if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
                                        Info.CallConv, Info.IsVarArg))
       return false;
 
     if (!NewRegs.empty())
-      MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
+      MIRBuilder.buildMergeLikeOp(Info.OrigRet.Regs[0], NewRegs);
   }
 
   CallSeqStart.addImm(Assigner.getStackSize())
       .addImm(0 /* see getFrameTotalSize */)
       .addImm(0 /* see getFrameAdjustment */);
 
   unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
   MIRBuilder.buildInstr(AdjStackUp)

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

TEST_F(AArch64GISelMITest, LowerMergeValues) {
   // 24 = 3 3 3   3 3 3   3 3
   //     => 9
   //
   // This can do 3 merges, but need an extra implicit_def.
   SmallVector<Register, 8> Merge0Ops;
   for (int I = 0; I != 8; ++I)
     Merge0Ops.push_back(B.buildConstant(S3, I).getReg(0));
 
-  auto Merge0 = B.buildMerge(S24, Merge0Ops);
+  auto Merge0 = B.buildMergeLikeOp(S24, Merge0Ops);
 
   // 21 = 3 3 3   3 3 3   3
   //     => 9, 2 extra implicit_def needed
   //
   SmallVector<Register, 8> Merge1Ops;
   for (int I = 0; I != 7; ++I)
     Merge1Ops.push_back(B.buildConstant(S3, I).getReg(0));
 
-  auto Merge1 = B.buildMerge(S21, Merge1Ops);
+  auto Merge1 = B.buildMergeLikeOp(S21, Merge1Ops);
 
   SmallVector<Register, 8> Merge2Ops;
   for (int I = 0; I != 2; ++I)
     Merge2Ops.push_back(B.buildConstant(S8, I).getReg(0));
 
-  auto Merge2 = B.buildMerge(S16, Merge2Ops);
+  auto Merge2 = B.buildMergeLikeOp(S16, Merge2Ops);
 
   B.setInstr(*Merge0);
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
             Helper.widenScalar(*Merge0, 1, S9));
   B.setInstr(*Merge1);
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
             Helper.widenScalar(*Merge1, 1, S9));
 
TEST_F(AArch64GISelMITest, WidenScalarMergeValuesPointer) {
 
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   const LLT P0 = LLT::pointer(0, 64);
 
   auto Lo = B.buildTrunc(S32, Copies[0]);
   auto Hi = B.buildTrunc(S32, Copies[1]);
 
-  auto Merge = B.buildMerge(P0, {Lo, Hi});
+  auto Merge = B.buildMergeLikeOp(P0, {Lo, Hi});
 
   B.setInstr(*Merge);
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
             Helper.widenScalar(*Merge, 1, S64));
 
   auto CheckStr = R"(
    CHECK: [[TRUNC0:%[0-9]+]]:_(s32) = G_TRUNC
    CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC
TEST_F(AArch64GISelMITest, LibcallFPTrunc) {
   LLT S16{LLT::scalar(16)};
   LLT S32{LLT::scalar(32)};
   LLT S64{LLT::scalar(64)};
   LLT S128{LLT::scalar(128)};
   auto MIBTrunc = B.buildTrunc(S32, Copies[0]);
   auto MIBFPTrunc1 =
       B.buildInstr(TargetOpcode::G_FPTRUNC, {S16}, {MIBTrunc});
 
-  auto MIBMerge = B.buildMerge(S128, {Copies[1], Copies[2]});
+  auto MIBMerge = B.buildMergeLikeOp(S128, {Copies[1], Copies[2]});
 
   auto MIBFPTrunc2 =
       B.buildInstr(TargetOpcode::G_FPTRUNC, {S64}, {MIBMerge});
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LostDebugLocObserver DummyLocObserver("");
   LegalizerHelper Helper(*MF, Info, Observer, B);
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

TEST_F(AArch64GISelMITest, BuildXor) {
   LLT S64 = LLT::scalar(64);
   LLT S128 = LLT::scalar(128);
   SmallVector<Register, 4> Copies;
   collectCopies(Copies, MF);
   B.buildXor(S64, Copies[0], Copies[1]);
   B.buildNot(S64, Copies[0]);
 
   // Make sure this works with > 64-bit types
-  auto Merge = B.buildMerge(S128, {Copies[0], Copies[1]});
+  auto Merge = B.buildMergeLikeOp(S128, {Copies[0], Copies[1]});
   B.buildNot(S128, Merge);
   auto CheckStr = R"(
   ; CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
   ; CHECK: [[XOR0:%[0-9]+]]:_(s64) = G_XOR [[COPY0]]:_, [[COPY1]]:_
   ; CHECK: [[NEGONE64:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
   ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY0]]:_, [[NEGONE64]]:_
   ; CHECK: [[MERGE:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY0]]:_(s64), [[COPY1]]:_(s64)
TEST_F(AArch64GISelMITest, BuildAtomicRMW) {
   ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_FADD [[PTR]]:_(p0), [[COPY0]]:_ :: (load store unordered (s64))
   ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_ATOMICRMW_FSUB [[PTR]]:_(p0), [[COPY0]]:_ :: (load store unordered (s64))
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
-TEST_F(AArch64GISelMITest, BuildMerge) {
+TEST_F(AArch64GISelMITest, BuildMergeLikeOp) {
   setUp();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   Register RegC0 = B.buildConstant(S32, 0).getReg(0);
   Register RegC1 = B.buildConstant(S32, 1).getReg(0);
   Register RegC2 = B.buildConstant(S32, 2).getReg(0);
   Register RegC3 = B.buildConstant(S32, 3).getReg(0);
 
   // Merging plain constants as one big blob of bit should produce a
   // G_MERGE_VALUES.
-  B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
+  B.buildMergeLikeOp(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
   // Merging plain constants to a vector should produce a G_BUILD_VECTOR.
   LLT V2x32 = LLT::fixed_vector(2, 32);
-  Register RegC0C1 =
-      B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0);
-  Register RegC2C3 =
-      B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0);
+  Register RegC0C1 = B.buildMergeLikeOp(V2x32, {RegC0, RegC1}).getReg(0);
+  Register RegC2C3 = B.buildMergeLikeOp(V2x32, {RegC2, RegC3}).getReg(0);
   // Merging vector constants to a vector should produce a G_CONCAT_VECTORS.
-  B.buildMerge(LLT::fixed_vector(4, 32), {RegC0C1, RegC2C3});
+  B.buildMergeLikeOp(LLT::fixed_vector(4, 32), {RegC0C1, RegC2C3});
   // Merging vector constants to a plain type is not allowed.
   // Nothing else to test.
 
   auto CheckStr = R"(
   ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
   ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3