[RISCV] Add intrinsics support for RISCV XTHeadVdot Extension

[JojoR]

Summary

This patch adds clang support for XTHeadVdot extension,
which is documented here, it's based on standard vector extension v1.0:

https://github.com/T-head-Semi/thead-extension-spec

[jrtc27]

clang/include/clang/Basic/riscv_vector.td

2384

This is an ugly name that isn't consistent with anything...

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c

5 ↗

(On Diff #487648)

Still not sure if these should be in riscv_vector.h or not... probably makes sense but a part of me says no

[JojoR]

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c

5 ↗

(On Diff #487648)

Any suggestions ?

[kito-cheng]

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c

5 ↗

(On Diff #487648)

Separated header file would be better, maybe thead_vector.h, and also extend the pragma syntax to #pragma clang riscv intrinsic thead-vector.

so the content of thead_vector.h only need header guard #pragma clang riscv intrinsic thead-vector.

[JojoR]

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/xtheadvdot-vmaqa.c

5 ↗

(On Diff #487648)

Ok & thanks, I will update later :)

[JojoR]

Separated header file would be better, maybe thead_vector.h, and also extend the pragma syntax to #pragma clang riscv intrinsic thead-vector.
so the content of thead_vector.h only need header guard #pragma clang riscv intrinsic thead-vector.

@kito-cheng From RVV pragma implementation, the 'xtheadvdot' intrinsics could been filtered out according to command line.
Of course I could add thead_vector.h and include vector.h, but is it really necessary ?

[JojoR]

@craig.topper
@kito-cheng
@asb
@eopXD
@jrtc27

Any comments or suggestions ?

[JojoR]

In D141346#4157530, @JojoR wrote:

Separated header file would be better, maybe thead_vector.h, and also extend the pragma syntax to #pragma clang riscv intrinsic thead-vector.
so the content of thead_vector.h only need header guard #pragma clang riscv intrinsic thead-vector.

@kito-cheng From RVV pragma implementation, the 'xtheadvdot' intrinsics could been filtered out according to command line.
Of course I could add thead_vector.h and include vector.h, but is it really necessary ?

@kito-cheng Ping ...

[kito-cheng]

FYI: https://reviews.llvm.org/D148308, this patch has implemented a new pragma, you can reference that to separated t-head stuffs from riscv_vector.h

[eopXD]

Unit tests?

clang/include/clang/Basic/riscv_thead_vector.td

+//===-- riscv_thead_vector.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by T-Head of Alibaba.
+//
+//===----------------------------------------------------------------------===//
+
+multiclass TH_VdotOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
+                                      list<list<string>> suffixes_prototypes> {
+    let OverloadedName = NAME in
+    defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
+}
+
+let RequiredFeatures = ["THeadVdot"],
+    UnMaskedPolicyScheme = HasPolicyOperand,
+    HasMaskedOffOperand = false,
+    Log2LMUL = [-1, 0, 1, 2, 3] in {
+defm th_vmaqau  : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqau", "c",
+                                             [["vv", "Uh", "UhUhUvUv"],
+                                              ["vx", "Uh", "UhUhUeUv"]]>;
+defm th_vmaqa   : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqa", "c",
+                                             [["vv", "h", "hhvv"],
+                                              ["vx", "h", "hhev"]]>;
+defm th_vmaqasu : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqasu", "c",
+                                             [["vv", "h", "hhvUv"],
+                                              ["vx", "h", "hheUv"]]>;
+defm th_vmaqaus : TH_VdotOutOp1Op2BuiltinSet<"th_vmaqaus", "c",
+                                             [["vx", "h", "hhUev"]]>;
+}

clang/include/clang/Basic/riscv_vector.td

 //   e: type of "t" as is (identity)
 //   v: computes a vector type whose element type is "t" for the current LMUL
 //   w: computes a vector type identical to what 'v' computes except for the
 //      element type which is twice as wide as the element type of 'v'
 //   q: computes a vector type identical to what 'v' computes except for the
 //      element type which is four times as wide as the element type of 'v'
 //   o: computes a vector type identical to what 'v' computes except for the
 //      element type which is eight times as wide as the element type of 'v'
+//   h: computes a vector type identical to what 'v' computes except for the
+//      element type which is four times as wide as the element type of 'v',
+//      and keep LMUL same with the original vector type
 //   m: computes a vector type identical to what 'v' computes except for the
 //      element type which is bool
 //   0: void type, ignores "t"
 //   z: size_t, ignores "t"
 //   t: ptrdiff_t, ignores "t"
 //   u: unsigned long, ignores "t"
 //   l: long, ignores "t"
 //
let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
       }
       }] in {
     foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
       def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
     }
   }
 }
+
+//===----------------------------------------------------------------------===//
+// Vendor extensions
+//===----------------------------------------------------------------------===//
+include "clang/Basic/riscv_thead_vector.td"

clang/include/clang/Support/RISCVVIntrinsicUtils.h

 using VScaleVal = std::optional<unsigned>;
 
 // Modifier for vector type.
 enum class VectorTypeModifier : uint8_t {
   NoModifier,
   Widening2XVector,
   Widening4XVector,
   Widening8XVector,
+  Widening4XSEW,
   MaskVector,
   Log2EEW3,
   Log2EEW4,
   Log2EEW5,
   Log2EEW6,
   FixedSEW8,
   FixedSEW16,
   FixedSEW32,

 };
 
 // RVVRequire should be sync'ed with target features, but only
 // required features used in riscv_vector.td.
 enum RVVRequire : uint8_t {
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_THeadVdot = 1 << 2,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_THeadVdot)
 };
 
 // Raw RVV intrinsic info, used to expand later.
 // This struct is highly compact for minimized code size.
 struct RVVIntrinsicRecord {
   // Intrinsic name, e.g. vadd_vv
   const char *Name;
 

clang/lib/Sema/SemaRISCVVectorLookup.cpp

bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                               Preprocessor &PP) override;
 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
   const TargetInfo &TI = Context.getTargetInfo();
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
+  bool HasTHeadVdot = TI.hasFeature("xtheadvdot");
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : RVVIntrinsicRecords) {
     // Create Intrinsics for each type and LMUL.
     BasicType BaseType = BasicType::Unknown;
     ArrayRef<PrototypeDescriptor> BasicProtoSeq =
         ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength);
for (auto &Record : RVVIntrinsicRecords) {
     bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
     bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
     SmallVector<Policy> SupportedUnMaskedPolicies =
         RVVIntrinsic::getSupportedUnMaskedPolicies();
     SmallVector<Policy> SupportedMaskedPolicies =
         RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy,
                                                  Record.HasMaskPolicy);
 
+    // Check requirement.
+    if (((Record.RequiredExtensions & RVV_REQ_THeadVdot) == RVV_REQ_THeadVdot) &&
+        !HasTHeadVdot)
+      continue;
+
     for (unsigned int TypeRangeMaskShift = 0;
          TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);
          ++TypeRangeMaskShift) {
       unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
       BaseType = static_cast<BasicType>(BaseTypeI);
 
       if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
         continue;

clang/lib/Support/RISCVVIntrinsicUtils.cpp

PrototypeDescriptor::parsePrototypeDescriptor(
   case 'q':
     PT = BaseTypeModifier::Vector;
     VTM = VectorTypeModifier::Widening4XVector;
     break;
   case 'o':
     PT = BaseTypeModifier::Vector;
     VTM = VectorTypeModifier::Widening8XVector;
     break;
+  case 'h':
+    PT = BaseTypeModifier::Vector;
+    VTM = VectorTypeModifier::Widening4XSEW;
+    break;
   case 'm':
     PT = BaseTypeModifier::Vector;
     VTM = VectorTypeModifier::MaskVector;
     break;
   case '0':
     PT = BaseTypeModifier::Void;
     break;
   case 'z':
case VectorTypeModifier::Widening4XVector:
     LMUL.MulLog2LMUL(2);
     Scale = LMUL.getScale(ElementBitwidth);
     break;
   case VectorTypeModifier::Widening8XVector:
     ElementBitwidth *= 8;
     LMUL.MulLog2LMUL(3);
     Scale = LMUL.getScale(ElementBitwidth);
     break;
+  case VectorTypeModifier::Widening4XSEW:
+    ElementBitwidth *= 4;
+    Scale = LMUL.getScale(ElementBitwidth);
+    break;
   case VectorTypeModifier::MaskVector:
     ScalarType = ScalarTypeKind::Boolean;
     Scale = LMUL.getScale(ElementBitwidth);
     ElementBitwidth = 1;
     break;
   case VectorTypeModifier::Log2EEW3:
     applyLog2EEW(3);
     break;
else if (PolicyAttrs.isTAPolicy()) {
         BuiltinName += "_ta";
     } else
       llvm_unreachable("Unhandled policy condition");
   }
 }
 
 SmallVector<PrototypeDescriptor> parsePrototypes(StringRef Prototypes) {
   SmallVector<PrototypeDescriptor> PrototypeDescriptors;
-  const StringRef Primaries("evwqom0ztul");
+  const StringRef Primaries("evwqohm0ztul");
   while (!Prototypes.empty()) {
     size_t Idx = 0;
     // Skip over complex prototype because it could contain primitive type
     // character.
     if (Prototypes[0] == '(')
       Idx = Prototypes.find_first_of(')');
     Idx = Prototypes.find_first_of(Primaries, Idx);
     assert(Idx != StringRef::npos);

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xtheadvdot-vmaqa-overloaded.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1,
+                                  vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1,
+                                  vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1,
+                                  vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                  vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                  vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqa(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    vuint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    uint8_t op1, vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc,
+                                    vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc,
+                                    vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc,
+                                    vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                    vint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                    vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc,
+                                    vint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc,
+                                    vint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc,
+                                    vint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqasu(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1,
+                                    vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1,
+                                    vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1,
+                                    vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqaus(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1,
+                                    vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqaus(mask, acc, op1, op2, vl);
+}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xtheadvdot-vmaqa.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvdot -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vv_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2(vint32mf2_t acc, int8_t op1, vint8mf2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1(vint32m1_t acc, int8_t op1, vint8m1_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2(vint32m2_t acc, int8_t op1, vint8m2_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4(vint32m4_t acc, int8_t op1, vint8m4_t op2,
+                                size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2(vuint32mf2_t acc, vuint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2(vuint32mf2_t acc, uint8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau_vx_u32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1(vuint32m1_t acc, vuint8m1_t op1,
+                                  vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1(vuint32m1_t acc, uint8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2(vuint32m2_t acc, vuint8m2_t op1,
+                                  vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2(vuint32m2_t acc, uint8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4(vuint32m4_t acc, vuint8m4_t op1,
+                                  vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4(vuint32m4_t acc, uint8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2(vint32mf2_t acc, vint8mf2_t op1,
+                                  vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2(vint32mf2_t acc, int8_t op1, vuint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1(vint32m1_t acc, vint8m1_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1(vint32m1_t acc, int8_t op1, vuint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2(vint32m2_t acc, vint8m2_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2(vint32m2_t acc, int8_t op1, vuint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4(vint32m4_t acc, vint8m4_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m4(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4(vint32m4_t acc, int8_t op1, vuint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2(vint32mf2_t acc, uint8_t op1, vint8mf2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32mf2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1(vint32m1_t acc, uint8_t op1, vint8m1_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m1(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2(vint32m2_t acc, uint8_t op1, vint8m2_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m2(acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4(vint32m4_t acc, uint8_t op1, vint8m4_t op2,
+                                  size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m4(acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                  vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vv_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqa_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                  vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vv_i32m1_m(vbool8_t mask, vint32m1_t acc, vint8m1_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqa_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                  vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vv_i32m2_m(vbool4_t mask, vint32m2_t acc, vint8m2_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqa_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                  vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vv_i32m4_m(vbool2_t mask, vint32m4_t acc, vint8m4_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vv_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqa_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqa_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                  vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqa_vx_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vv_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    vuint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return __riscv_th_vmaqau_vv_u32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_th_vmaqau_vx_u32mf2_m(vbool16_t mask, vuint32mf2_t acc,
+                                    uint8_t op1, vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vx_u32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vv_u32m1_m(vbool8_t mask, vuint32m1_t acc,
+                                    vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_th_vmaqau_vx_u32m1_m(vbool8_t mask, vuint32m1_t acc, uint8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vv_u32m2_m(vbool4_t mask, vuint32m2_t acc,
+                                    vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_th_vmaqau_vx_u32m2_m(vbool4_t mask, vuint32m2_t acc, uint8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vv_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vv_u32m4_m(vbool2_t mask, vuint32m4_t acc,
+                                    vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vv_u32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqau_vx_u32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_th_vmaqau_vx_u32m4_m(vbool2_t mask, vuint32m4_t acc, uint8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqau_vx_u32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vv_i32mf2_m(vbool16_t mask, vint32mf2_t acc,
+                                    vint8mf2_t op1, vuint8mf2_t op2,
+                                    size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqasu_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, int8_t op1,
+                                    vuint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vv_i32m1_m(vbool8_t mask, vint32m1_t acc,
+                                    vint8m1_t op1, vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqasu_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, int8_t op1,
+                                    vuint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vv_i32m2_m(vbool4_t mask, vint32m2_t acc,
+                                    vint8m2_t op1, vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqasu_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, int8_t op1,
+                                    vuint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vv_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vv_i32m4_m(vbool2_t mask, vint32m4_t acc,
+                                    vint8m4_t op1, vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vv_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqasu_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqasu_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, int8_t op1,
+                                    vuint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqasu_vx_i32m4_m(mask, acc, op1, op2, vl);
+}
+
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32mf2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8.nxv4i8.i64(<vscale x 1 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_th_vmaqaus_vx_i32mf2_m(vbool16_t mask, vint32mf2_t acc, uint8_t op1,
+                                    vint8mf2_t op2, size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32mf2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m1_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8.nxv8i8.i64(<vscale x 2 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_th_vmaqaus_vx_i32m1_m(vbool8_t mask, vint32m1_t acc, uint8_t op1,
+                                    vint8m1_t op2, size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m1_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m2_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8.nxv16i8.i64(<vscale x 4 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_th_vmaqaus_vx_i32m2_m(vbool4_t mask, vint32m2_t acc, uint8_t op1,
+                                    vint8m2_t op2, size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m2_m(mask, acc, op1, op2, vl);
+}
+
+// CHECK-LABEL: @test_th_vmaqaus_vx_i32m4_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8.nxv32i8.i64(<vscale x 8 x i32> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_th_vmaqaus_vx_i32m4_m(vbool2_t mask, vint32m4_t acc, uint8_t op1,
+                                    vint8m4_t op2, size_t vl) {
+  return __riscv_th_vmaqaus_vx_i32m4_m(mask, acc, op1, op2, vl);
+}

clang/utils/TableGen/RISCVVEmitter.cpp

for (auto *R : RV) {
 
     SR.Log2LMULMask = Log2LMULMask;
 
     SR.RequiredExtensions = 0;
     for (auto RequiredFeature : RequiredFeatures) {
       RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
                                   .Case("RV64", RVV_REQ_RV64)
                                   .Case("FullMultiply", RVV_REQ_FullMultiply)
+                                  .Case("THeadVdot", RVV_REQ_THeadVdot)
                                   .Default(RVV_REQ_None);
       assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
       SR.RequiredExtensions |= RequireExt;
     }
 
     SR.NF = NF;
     SR.HasMasked = HasMasked;
     SR.HasVL = HasVL;