This is an archive of the discontinued LLVM Phabricator instance.

[AArch64] Fold And/Or into CSel if possible
ClosedPublic

Authored by dmgreen on Jan 6 2023, 3:09 AM.

Details

Summary

If we have and x, (csel 0, 1, cc) and we know that x is 0/1, then we can emit a csel ZR, x, cc. Similarly for 'or x, (csel 0, 1, cc) we can emit csinc x, ZR, cc`. This can help where we can not otherwise general ccmp instructions.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 6 2023, 3:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2023, 3:09 AM
dmgreen requested review of this revision.Jan 6 2023, 3:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2023, 3:09 AM
samtebbs accepted this revision.Jan 6 2023, 3:23 AM

LGTM with one suggestion.

llvm/lib/Target/AArch64/AArch64InstrInfo.td
555

If I understand these PatLeafs right then they return true if the top bits are zero with the bottom bit being unknown. If so then I think the "known non-zero" part of the comment could be reworded.

This revision is now accepted and ready to land.Jan 6 2023, 3:23 AM
spatel added a comment.Jan 6 2023, 6:44 AM

I had not pushed the test files for D141086 until bd87b84a02252635cd, so this needs an update to regenerate the extra tests. Thanks for the fast update!

llvm/lib/Target/AArch64/AArch64InstrInfo.td
555

Yes, could be "is_zext_of_one_bit" or something like that.

This revision was landed with ongoing or failed builds.Jan 9 2023, 3:52 AM
This revision was automatically updated to reflect the committed changes.
Allen added a subscriber: Allen.Jan 9 2023, 4:10 AM