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Differential D141137

[ARM] Fold And/Or into CSel if possible
ClosedPublic

Authored by dmgreen on Jan 6 2023, 7:14 AM.

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Reviewers
samtebbs
bipmis
SjoerdMeijer
labrinea
Commits
rG90f24bef4722: [ARM] Fold And/Or into CSel if possible
Summary

This is the ARM equivalent of D141119, where we fold and x, (csel 0, 1, cc) to csel ZR, x, cc if we know that x is 0/1 and for or x, (csel 0, 1, cc) emit csinc x, ZR, cc. The or pattern gets recognized from a cmov under Arm.

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Event Timeline

dmgreen created this revision.Jan 6 2023, 7:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2023, 7:14 AM
Herald added subscribers: zzheng, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Jan 6 2023, 7:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2023, 7:14 AM
Harbormaster completed remote builds in B206117: Diff 486856.Jan 6 2023, 7:15 AM
samtebbs accepted this revision.Jan 6 2023, 7:18 AM

Looking good

This revision is now accepted and ready to land.Jan 6 2023, 7:18 AM
This revision was landed with ongoing or failed builds.Jan 9 2023, 5:29 AM
Closed by commit rG90f24bef4722: [ARM] Fold And/Or into CSel if possible (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG90f24bef4722: [ARM] Fold And/Or into CSel if possible.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
6 lines
5 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
26 lines
60 lines
66 lines
27 lines
51 lines
18 lines
20 lines
40 lines
72 lines
144 lines
144 lines
80 lines

Diff 487394

llvm/lib/Target/ARM/ARMInstrInfo.td

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}], hi16>; }], hi16>;
// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
def top16Zero: PatLeaf<(i32 GPR:$src), [{ def top16Zero: PatLeaf<(i32 GPR:$src), [{
return !SDValue(N,0)->getValueType(0).isVector() && return !SDValue(N,0)->getValueType(0).isVector() &&
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16)); CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
}]>; }]>;
// topbitsallzero - Return true if all bits except the lowest bit are known zero
def topbitsallzero32 : PatLeaf<(i32 GPRwithZR:$src), [{
return SDValue(N,0)->getValueType(0) == MVT::i32 &&
CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 31));
}]>;
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
// An 'and' node with a single use. // An 'and' node with a single use.
def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
return N->hasOneUse(); return N->hasOneUse();
}]>; }]>;
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llvm/lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 5,651 Lines • ▼ Show 20 Lines def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm), def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, (Insn GPRwithZR:$tval, GPRwithZR:$fval,
(i32 (inv_cond_XFORM imm:$imm)))>; (i32 (inv_cond_XFORM imm:$imm)))>;
} }
defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>; defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>; defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>; defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;
def : T2Pat<(ARMcmov (topbitsallzero32:$Rn), (i32 1), cmovpred:$imm),
(t2CSINC $Rn, ZR, $imm)>;
def : T2Pat<(and (topbitsallzero32:$Rn), (ARMcsinc (i32 0), (i32 0), cmovpred:$imm)),
(t2CSEL ZR, $Rn, $imm)>;
} }
// CS aliases. // CS aliases.
let Predicates = [HasV8_1MMainline] in { let Predicates = [HasV8_1MMainline] in {
def : InstAlias<"csetm\t$Rd, $fcond", def : InstAlias<"csetm\t$Rd, $fcond",
(t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>; (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
def : InstAlias<"cset\t$Rd, $fcond", def : InstAlias<"cset\t$Rd, $fcond",
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fullfp16 -tail-predication=enabled %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fullfp16 -tail-predication=enabled %s -o - | FileCheck %s
define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocapture readonly %b, float* nocapture readonly %c, i32 %N) { define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocapture readonly %b, float* nocapture readonly %c, i32 %N) {
; CHECK-LABEL: fast_float_mul: ; CHECK-LABEL: fast_float_mul:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB0_11 ; CHECK-NEXT: beq.w .LBB0_11
; CHECK-NEXT: @ %bb.1: @ %vector.memcheck ; CHECK-NEXT: @ %bb.1: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r0, r3, lsl #2
; CHECK-NEXT: add.w r4, r2, r3, lsl #2 ; CHECK-NEXT: add.w r4, r2, r3, lsl #2
; CHECK-NEXT: cmp r5, r2 ; CHECK-NEXT: add.w lr, r0, r3, lsl #2
; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r4, r0 ; CHECK-NEXT: cmp r4, r0
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp lr, r2
; CHECK-NEXT: csel r12, zr, r4, ls
; CHECK-NEXT: cmp lr, r1
; CHECK-NEXT: add.w r4, r1, r3, lsl #2
; CHECK-NEXT: cset lr, hi ; CHECK-NEXT: cset lr, hi
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: cmp r4, r0
; CHECK-NEXT: add.w r5, r1, r3, lsl #2
; CHECK-NEXT: cset r4, hi ; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: tst.w r4, lr
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: tst r5, r4
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r5, lr, r12 ; CHECK-NEXT: cmpeq.w r12, #0
; CHECK-NEXT: beq .LBB0_4 ; CHECK-NEXT: beq .LBB0_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader ; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: subs r5, r3, #1 ; CHECK-NEXT: subs r4, r3, #1
; CHECK-NEXT: and r12, r3, #3 ; CHECK-NEXT: and r12, r3, #3
; CHECK-NEXT: cmp r5, #3 ; CHECK-NEXT: cmp r4, #3
; CHECK-NEXT: bhs .LBB0_6 ; CHECK-NEXT: bhs .LBB0_6
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: b .LBB0_8 ; CHECK-NEXT: b .LBB0_8
; CHECK-NEXT: .LBB0_4: @ %vector.ph ; CHECK-NEXT: .LBB0_4: @ %vector.ph
; CHECK-NEXT: dlstp.32 lr, r3 ; CHECK-NEXT: dlstp.32 lr, r3
; CHECK-NEXT: .LBB0_5: @ %vector.body ; CHECK-NEXT: .LBB0_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vldrw.u32 q1, [r2], #16 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16
; CHECK-NEXT: vmul.f32 q0, q1, q0 ; CHECK-NEXT: vmul.f32 q0, q1, q0
; CHECK-NEXT: vstrw.32 q0, [r0], #16 ; CHECK-NEXT: vstrw.32 q0, [r0], #16
; CHECK-NEXT: letp lr, .LBB0_5 ; CHECK-NEXT: letp lr, .LBB0_5
; CHECK-NEXT: b .LBB0_11 ; CHECK-NEXT: b .LBB0_11
; CHECK-NEXT: .LBB0_6: @ %for.body.preheader.new ; CHECK-NEXT: .LBB0_6: @ %for.body.preheader.new
; CHECK-NEXT: bic r3, r3, #3 ; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: movs r5, #1 ; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
; CHECK-NEXT: add.w lr, r4, r3, lsr #2
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: add.w lr, r5, r3, lsr #2
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: .LBB0_7: @ %for.body ; CHECK-NEXT: .LBB0_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: adds r5, r1, r4 ; CHECK-NEXT: adds r5, r1, r4
; CHECK-NEXT: adds r6, r2, r4 ; CHECK-NEXT: adds r6, r2, r4
; CHECK-NEXT: adds r7, r0, r4 ; CHECK-NEXT: adds r7, r0, r4
; CHECK-NEXT: adds r4, #16 ; CHECK-NEXT: adds r4, #16
; CHECK-NEXT: vldr s0, [r5] ; CHECK-NEXT: vldr s0, [r5]
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fullfp16 %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fullfp16 %s -o - | FileCheck %s
define arm_aapcs_vfpcc void @float_float_mul(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture %c, i32 %N) { define arm_aapcs_vfpcc void @float_float_mul(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture %c, i32 %N) {
; CHECK-LABEL: float_float_mul: ; CHECK-LABEL: float_float_mul:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq .LBB0_10 ; CHECK-NEXT: beq .LBB0_10
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #3 ; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB0_3 ; CHECK-NEXT: bhi .LBB0_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: b .LBB0_4 ; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3: @ %vector.memcheck ; CHECK-NEXT: .LBB0_3: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r2, r3, lsl #2 ; CHECK-NEXT: add.w r7, r1, r3, lsl #2
; CHECK-NEXT: add.w r6, r1, r3, lsl #2 ; CHECK-NEXT: add.w r6, r2, r3, lsl #2
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: cmp r7, r2
; CHECK-NEXT: add.w r4, r0, r3, lsl #2 ; CHECK-NEXT: add.w r5, r0, r3, lsl #2
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: cmp r6, r2 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi ; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r5, r2
; CHECK-NEXT: cset r5, hi ; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: tst r4, r5 ; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r7, r6 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB0_11 ; CHECK-NEXT: beq .LBB0_11
; CHECK-NEXT: .LBB0_4: @ %for.body.preheader22 ; CHECK-NEXT: .LBB0_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12 ; CHECK-NEXT: mvn.w r7, r12
; CHECK-NEXT: adds r4, r7, r3 ; CHECK-NEXT: adds r4, r7, r3
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r7, r3, #3
; CHECK-NEXT: wls lr, r7, .LBB0_7 ; CHECK-NEXT: wls lr, r7, .LBB0_7
; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader ; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader
; CHECK-NEXT: add.w r5, r0, r12, lsl #2 ; CHECK-NEXT: add.w r5, r0, r12, lsl #2
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; CHECK-NEXT: beq .LBB1_10 ; CHECK-NEXT: beq .LBB1_10
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #3 ; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB1_3 ; CHECK-NEXT: bhi .LBB1_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: b .LBB1_4 ; CHECK-NEXT: b .LBB1_4
; CHECK-NEXT: .LBB1_3: @ %vector.memcheck ; CHECK-NEXT: .LBB1_3: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r2, r3, lsl #2 ; CHECK-NEXT: add.w r7, r1, r3, lsl #2
; CHECK-NEXT: add.w r6, r1, r3, lsl #2 ; CHECK-NEXT: add.w r6, r2, r3, lsl #2
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: cmp r7, r2
; CHECK-NEXT: add.w r4, r0, r3, lsl #2 ; CHECK-NEXT: add.w r5, r0, r3, lsl #2
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: cmp r6, r2 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi ; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r5, r2
; CHECK-NEXT: cset r5, hi ; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: tst r4, r5 ; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r7, r6 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB1_11 ; CHECK-NEXT: beq .LBB1_11
; CHECK-NEXT: .LBB1_4: @ %for.body.preheader22 ; CHECK-NEXT: .LBB1_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12 ; CHECK-NEXT: mvn.w r7, r12
; CHECK-NEXT: adds r4, r7, r3 ; CHECK-NEXT: adds r4, r7, r3
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r7, r3, #3
; CHECK-NEXT: wls lr, r7, .LBB1_7 ; CHECK-NEXT: wls lr, r7, .LBB1_7
; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader ; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader
; CHECK-NEXT: add.w r5, r0, r12, lsl #2 ; CHECK-NEXT: add.w r5, r0, r12, lsl #2
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; CHECK-NEXT: beq .LBB2_10 ; CHECK-NEXT: beq .LBB2_10
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #3 ; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB2_3 ; CHECK-NEXT: bhi .LBB2_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: b .LBB2_4 ; CHECK-NEXT: b .LBB2_4
; CHECK-NEXT: .LBB2_3: @ %vector.memcheck ; CHECK-NEXT: .LBB2_3: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r2, r3, lsl #2 ; CHECK-NEXT: add.w r7, r1, r3, lsl #2
; CHECK-NEXT: add.w r6, r1, r3, lsl #2 ; CHECK-NEXT: add.w r6, r2, r3, lsl #2
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: cmp r7, r2
; CHECK-NEXT: add.w r4, r0, r3, lsl #2 ; CHECK-NEXT: add.w r5, r0, r3, lsl #2
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: cmp r6, r2 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi ; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r5, r2
; CHECK-NEXT: cset r5, hi ; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: tst r4, r5 ; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r7, r6 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB2_11 ; CHECK-NEXT: beq .LBB2_11
; CHECK-NEXT: .LBB2_4: @ %for.body.preheader22 ; CHECK-NEXT: .LBB2_4: @ %for.body.preheader22
; CHECK-NEXT: mvn.w r7, r12 ; CHECK-NEXT: mvn.w r7, r12
; CHECK-NEXT: adds r4, r7, r3 ; CHECK-NEXT: adds r4, r7, r3
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r7, r3, #3
; CHECK-NEXT: wls lr, r7, .LBB2_7 ; CHECK-NEXT: wls lr, r7, .LBB2_7
; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader ; CHECK-NEXT: @ %bb.5: @ %for.body.prol.preheader
; CHECK-NEXT: add.w r5, r0, r12, lsl #2 ; CHECK-NEXT: add.w r5, r0, r12, lsl #2
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly %a, i8* nocapture readonly %b, i8 zeroext %c, i32* nocapture %res, i32 %N) { define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly %a, i8* nocapture readonly %b, i8 zeroext %c, i32* nocapture %res, i32 %N) {
; CHECK-LABEL: test_vec_mul_scalar_add_char: ; CHECK-LABEL: test_vec_mul_scalar_add_char:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: ldr r4, [sp, #28] ; CHECK-NEXT: ldr r4, [sp, #28]
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: beq.w .LBB5_11 ; CHECK-NEXT: beq.w .LBB5_11
; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph ; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph
; CHECK-NEXT: add.w r5, r3, r4, lsl #2 ; CHECK-NEXT: adds r7, r1, r4
; CHECK-NEXT: adds r6, r1, r4 ; CHECK-NEXT: add.w r6, r3, r4, lsl #2
; CHECK-NEXT: cmp r5, r1
; CHECK-NEXT: add.w r7, r0, r4
; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r6, r3
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r7, r3 ; CHECK-NEXT: cmp r7, r3
; CHECK-NEXT: add.w r5, r0, r4
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: tst r7, r5 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r6, r12 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB5_4 ; CHECK-NEXT: beq .LBB5_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader ; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: subs r7, r4, #1 ; CHECK-NEXT: subs r7, r4, #1
; CHECK-NEXT: and r12, r4, #3 ; CHECK-NEXT: and r12, r4, #3
; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: cmp r7, #3
; CHECK-NEXT: bhs .LBB5_6 ; CHECK-NEXT: bhs .LBB5_6
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: mov.w r8, #0 ; CHECK-NEXT: mov.w r8, #0
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define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_uchar(i8* nocapture readonly %a, i8* nocapture readonly %b, i8 zeroext %c, i32* nocapture %res, i32 %N) { define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_uchar(i8* nocapture readonly %a, i8* nocapture readonly %b, i8 zeroext %c, i32* nocapture %res, i32 %N) {
; CHECK-LABEL: test_vec_mul_scalar_add_uchar: ; CHECK-LABEL: test_vec_mul_scalar_add_uchar:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: ldr r4, [sp, #28] ; CHECK-NEXT: ldr r4, [sp, #28]
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: beq.w .LBB7_11 ; CHECK-NEXT: beq.w .LBB7_11
; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph ; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph
; CHECK-NEXT: add.w r5, r3, r4, lsl #2 ; CHECK-NEXT: adds r7, r1, r4
; CHECK-NEXT: adds r6, r1, r4 ; CHECK-NEXT: add.w r6, r3, r4, lsl #2
; CHECK-NEXT: cmp r5, r1
; CHECK-NEXT: add.w r7, r0, r4
; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r6, r3
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r7, r3 ; CHECK-NEXT: cmp r7, r3
; CHECK-NEXT: add.w r5, r0, r4
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: tst r7, r5 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r6, r12 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB7_4 ; CHECK-NEXT: beq .LBB7_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader ; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: subs r7, r4, #1 ; CHECK-NEXT: subs r7, r4, #1
; CHECK-NEXT: and r12, r4, #3 ; CHECK-NEXT: and r12, r4, #3
; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: cmp r7, #3
; CHECK-NEXT: bhs .LBB7_6 ; CHECK-NEXT: bhs .LBB7_6
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: mov.w r8, #0 ; CHECK-NEXT: mov.w r8, #0
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define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_int(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %c, i32* nocapture %res, i32 %N) { define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_int(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %c, i32* nocapture %res, i32 %N) {
; CHECK-LABEL: test_vec_mul_scalar_add_int: ; CHECK-LABEL: test_vec_mul_scalar_add_int:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: ldr r4, [sp, #28] ; CHECK-NEXT: ldr r4, [sp, #28]
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: beq.w .LBB9_11 ; CHECK-NEXT: beq.w .LBB9_11
; CHECK-NEXT: @ %bb.1: @ %vector.memcheck ; CHECK-NEXT: @ %bb.1: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r3, r4, lsl #2 ; CHECK-NEXT: add.w r7, r1, r4, lsl #2
; CHECK-NEXT: add.w r6, r1, r4, lsl #2 ; CHECK-NEXT: add.w r6, r3, r4, lsl #2
; CHECK-NEXT: cmp r5, r1
; CHECK-NEXT: add.w r7, r0, r4, lsl #2
; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r6, r3
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r7, r3 ; CHECK-NEXT: cmp r7, r3
; CHECK-NEXT: add.w r5, r0, r4, lsl #2
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: tst r7, r5 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r6, r12 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB9_4 ; CHECK-NEXT: beq .LBB9_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader ; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
; CHECK-NEXT: subs r7, r4, #1 ; CHECK-NEXT: subs r7, r4, #1
; CHECK-NEXT: and r12, r4, #3 ; CHECK-NEXT: and r12, r4, #3
; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: cmp r7, #3
; CHECK-NEXT: bhs .LBB9_6 ; CHECK-NEXT: bhs .LBB9_6
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: mov.w r8, #0 ; CHECK-NEXT: mov.w r8, #0
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llvm/test/CodeGen/Thumb2/csel-andor-onebit.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=thumbv8.1m.main-none-eabi | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=thumbv8.1m.main-none-eabi | FileCheck %s
define i32 @ori32i32_eq(i32 %x, i32 %y) { define i32 @ori32i32_eq(i32 %x, i32 %y) {
; CHECK-LABEL: ori32i32_eq: ; CHECK-LABEL: ori32i32_eq:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: csinc r0, r0, zr, eq
; CHECK-NEXT: moveq r0, #1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xa = and i32 %x, 1 %xa = and i32 %x, 1
%c = icmp eq i32 %y, 0 %c = icmp eq i32 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = or i32 %xa, %cz %a = or i32 %xa, %cz
ret i32 %a ret i32 %a
} }
define i32 @ori32_eq_c(i32 %x, i32 %y) { define i32 @ori32_eq_c(i32 %x, i32 %y) {
; CHECK-LABEL: ori32_eq_c: ; CHECK-LABEL: ori32_eq_c:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: csinc r0, r0, zr, eq
; CHECK-NEXT: moveq r0, #1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xa = and i32 %x, 1 %xa = and i32 %x, 1
%c = icmp eq i32 %y, 0 %c = icmp eq i32 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = or i32 %cz, %xa %a = or i32 %cz, %xa
ret i32 %a ret i32 %a
} }
define i32 @ori32i64_eq(i32 %x, i64 %y) { define i32 @ori32i64_eq(i32 %x, i64 %y) {
; CHECK-LABEL: ori32i64_eq: ; CHECK-LABEL: ori32i64_eq:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: orrs.w r1, r2, r3 ; CHECK-NEXT: orrs.w r1, r2, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: moveq r0, #1 ; CHECK-NEXT: csinc r0, r0, zr, eq
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xa = and i32 %x, 1 %xa = and i32 %x, 1
%c = icmp eq i64 %y, 0 %c = icmp eq i64 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = or i32 %xa, %cz %a = or i32 %xa, %cz
ret i32 %a ret i32 %a
} }
define i32 @ori32_sgt(i32 %x, i32 %y) { define i32 @ori32_sgt(i32 %x, i32 %y) {
; CHECK-LABEL: ori32_sgt: ; CHECK-LABEL: ori32_sgt:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it gt ; CHECK-NEXT: csinc r0, r0, zr, gt
; CHECK-NEXT: movgt r0, #1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xa = and i32 %x, 1 %xa = and i32 %x, 1
%c = icmp sgt i32 %y, 0 %c = icmp sgt i32 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = or i32 %xa, %cz %a = or i32 %xa, %cz
ret i32 %a ret i32 %a
} }
Show All 11 Lines; CHECK-NEXT: bx lr
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = or i32 %xa, %cz %a = or i32 %xa, %cz
ret i32 %a ret i32 %a
} }
define i32 @andi32_ne(i8 %x, i8 %y) { define i32 @andi32_ne(i8 %x, i8 %y) {
; CHECK-LABEL: andi32_ne: ; CHECK-LABEL: andi32_ne:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: tst.w r1, #255
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: tst.w r0, #255 ; CHECK-NEXT: tst.w r0, #255
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: ands r0, r1 ; CHECK-NEXT: tst.w r1, #255
; CHECK-NEXT: csel r0, zr, r0, eq
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xc = icmp eq i8 %x, 0 %xc = icmp eq i8 %x, 0
%xa = zext i1 %xc to i32 %xa = zext i1 %xc to i32
%c = icmp ne i8 %y, 0 %c = icmp ne i8 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = and i32 %xa, %cz %a = and i32 %xa, %cz
ret i32 %a ret i32 %a
} }
define i32 @andi32_sgt(i8 %x, i8 %y) { define i32 @andi32_sgt(i8 %x, i8 %y) {
; CHECK-LABEL: andi32_sgt: ; CHECK-LABEL: andi32_sgt:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: tst.w r0, #255 ; CHECK-NEXT: tst.w r0, #255
; CHECK-NEXT: sxtb r1, r1 ; CHECK-NEXT: sxtb r1, r1
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, gt ; CHECK-NEXT: csel r0, zr, r0, le
; CHECK-NEXT: ands r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xc = icmp eq i8 %x, 0 %xc = icmp eq i8 %x, 0
%xa = zext i1 %xc to i32 %xa = zext i1 %xc to i32
%c = icmp sgt i8 %y, 0 %c = icmp sgt i8 %y, 0
%cz = zext i1 %c to i32 %cz = zext i1 %c to i32
%a = and i32 %xa, %cz %a = and i32 %xa, %cz
ret i32 %a ret i32 %a
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%cz = zext i1 %c to i64 %cz = zext i1 %c to i64
%a = or i64 %cz, %xa %a = or i64 %cz, %xa
ret i64 %a ret i64 %a
} }
define i64 @andi64_ne(i8 %x, i8 %y) { define i64 @andi64_ne(i8 %x, i8 %y) {
; CHECK-LABEL: andi64_ne: ; CHECK-LABEL: andi64_ne:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: tst.w r1, #255
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: tst.w r0, #255 ; CHECK-NEXT: tst.w r0, #255
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: ands r0, r1 ; CHECK-NEXT: tst.w r1, #255
; CHECK-NEXT: csel r0, zr, r0, eq
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%xc = icmp eq i8 %x, 0 %xc = icmp eq i8 %x, 0
%xa = zext i1 %xc to i64 %xa = zext i1 %xc to i64
%c = icmp ne i8 %y, 0 %c = icmp ne i8 %y, 0
%cz = zext i1 %c to i64 %cz = zext i1 %c to i64
%a = and i64 %xa, %cz %a = and i64 %xa, %cz
ret i64 %a ret i64 %a
} }

llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck --check-prefix=CHECK %s
define void @tailpred(ptr nocapture readonly %pSrcA, ptr nocapture readonly %pSrcB, ptr nocapture %pDst, i32 %blockSize) { define void @tailpred(ptr nocapture readonly %pSrcA, ptr nocapture readonly %pSrcB, ptr nocapture %pDst, i32 %blockSize) {
; CHECK-LABEL: tailpred: ; CHECK-LABEL: tailpred:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq .LBB0_6 ; CHECK-NEXT: it eq
; CHECK-NEXT: @ %bb.1: @ %vector.memcheck ; CHECK-NEXT: popeq {r4, pc}
; CHECK-NEXT: add.w r5, r2, r3, lsl #1 ; CHECK-NEXT: .LBB0_1: @ %vector.memcheck
; CHECK-NEXT: add.w r4, r1, r3, lsl #1 ; CHECK-NEXT: add.w r12, r1, r3, lsl #1
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: add.w lr, r2, r3, lsl #1
; CHECK-NEXT: cmp r12, r2
; CHECK-NEXT: add.w r4, r0, r3, lsl #1
; CHECK-NEXT: cset r12, hi ; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r4, r2 ; CHECK-NEXT: cmp lr, r1
; CHECK-NEXT: csel r12, zr, r12, ls
; CHECK-NEXT: cmp lr, r0
; CHECK-NEXT: cset lr, hi ; CHECK-NEXT: cset lr, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: add.w r5, r0, r3, lsl #1
; CHECK-NEXT: cset r4, hi ; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp r5, r2 ; CHECK-NEXT: tst.w r4, lr
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: tst r5, r4
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r5, lr, r12 ; CHECK-NEXT: cmpeq.w r12, #0
; CHECK-NEXT: beq .LBB0_4 ; CHECK-NEXT: beq .LBB0_4
; CHECK-NEXT: @ %bb.2: @ %while.body.preheader ; CHECK-NEXT: @ %bb.2: @ %while.body.preheader
; CHECK-NEXT: dls lr, r3 ; CHECK-NEXT: dls lr, r3
; CHECK-NEXT: .LBB0_3: @ %while.body ; CHECK-NEXT: .LBB0_3: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldr.16 s0, [r0] ; CHECK-NEXT: vldr.16 s0, [r0]
; CHECK-NEXT: vldr.16 s2, [r1] ; CHECK-NEXT: vldr.16 s2, [r1]
; CHECK-NEXT: adds r1, #2 ; CHECK-NEXT: adds r1, #2
; CHECK-NEXT: adds r0, #2 ; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: vadd.f16 s0, s2, s0 ; CHECK-NEXT: vadd.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r2] ; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: adds r2, #2 ; CHECK-NEXT: adds r2, #2
; CHECK-NEXT: le lr, .LBB0_3 ; CHECK-NEXT: le lr, .LBB0_3
; CHECK-NEXT: b .LBB0_6 ; CHECK-NEXT: b .LBB0_6
; CHECK-NEXT: .LBB0_4: @ %vector.ph ; CHECK-NEXT: .LBB0_4: @ %vector.ph
; CHECK-NEXT: dlstp.16 lr, r3 ; CHECK-NEXT: dlstp.16 lr, r3
; CHECK-NEXT: .LBB0_5: @ %vector.body ; CHECK-NEXT: .LBB0_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r0], #16 ; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16 ; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vstrh.16 q0, [r2], #16 ; CHECK-NEXT: vstrh.16 q0, [r2], #16
; CHECK-NEXT: letp lr, .LBB0_5 ; CHECK-NEXT: letp lr, .LBB0_5
; CHECK-NEXT: .LBB0_6: @ %while.end ; CHECK-NEXT: .LBB0_6: @ %while.end
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%cmp.not6 = icmp eq i32 %blockSize, 0 %cmp.not6 = icmp eq i32 %blockSize, 0
br i1 %cmp.not6, label %while.end, label %vector.memcheck br i1 %cmp.not6, label %while.end, label %vector.memcheck
vector.memcheck: ; preds = %entry vector.memcheck: ; preds = %entry
%scevgep = getelementptr half, ptr %pDst, i32 %blockSize %scevgep = getelementptr half, ptr %pDst, i32 %blockSize
%scevgep14 = getelementptr half, ptr %pSrcA, i32 %blockSize %scevgep14 = getelementptr half, ptr %pSrcA, i32 %blockSize
%scevgep17 = getelementptr half, ptr %pSrcB, i32 %blockSize %scevgep17 = getelementptr half, ptr %pSrcB, i32 %blockSize
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; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: cbz r3, .LBB1_6 ; CHECK-NEXT: cbz r3, .LBB1_6
; CHECK-NEXT: @ %bb.1: @ %while.body.preheader ; CHECK-NEXT: @ %bb.1: @ %while.body.preheader
; CHECK-NEXT: cmp r3, #8 ; CHECK-NEXT: cmp r3, #8
; CHECK-NEXT: blo .LBB1_3 ; CHECK-NEXT: blo .LBB1_3
; CHECK-NEXT: @ %bb.2: @ %vector.memcheck ; CHECK-NEXT: @ %bb.2: @ %vector.memcheck
; CHECK-NEXT: add.w r5, r2, r3, lsl #1 ; CHECK-NEXT: add.w r7, r1, r3, lsl #1
; CHECK-NEXT: add.w r6, r1, r3, lsl #1 ; CHECK-NEXT: add.w r6, r2, r3, lsl #1
; CHECK-NEXT: cmp r5, r1 ; CHECK-NEXT: cmp r7, r2
; CHECK-NEXT: add.w r4, r0, r3, lsl #1 ; CHECK-NEXT: add.w r5, r0, r3, lsl #1
; CHECK-NEXT: cset r7, hi ; CHECK-NEXT: cset r7, hi
; CHECK-NEXT: cmp r6, r2 ; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: csel r7, zr, r7, ls
; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi ; CHECK-NEXT: cset r6, hi
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r5, r2
; CHECK-NEXT: cset r5, hi ; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: cmp r4, r2 ; CHECK-NEXT: tst r5, r6
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: tst r4, r5
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: andseq.w r7, r7, r6 ; CHECK-NEXT: cmpeq r7, #0
; CHECK-NEXT: beq .LBB1_7 ; CHECK-NEXT: beq .LBB1_7
; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: mov r5, r3 ; CHECK-NEXT: mov r5, r3
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: mov r7, r2 ; CHECK-NEXT: mov r7, r2
; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: .LBB1_4: @ %while.body.preheader31 ; CHECK-NEXT: .LBB1_4: @ %while.body.preheader31
; CHECK-NEXT: dls lr, r5 ; CHECK-NEXT: dls lr, r5
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-pred-and.ll

Show First 20 Lines • Show All 599 Lines • ▼ Show 20 Lines
; CHECK-LABEL: cmpeq_v2i1: ; CHECK-LABEL: cmpeq_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d4 ; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: vmov r2, r3, d2 ; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: eors r1, r3 ; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r12, r2, d5 ; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: cset r1, eq ; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r0, r1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, zr, r1, ne
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #8 ; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r3, r0, d3 ; CHECK-NEXT: vmov r3, r0, d3
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: eor.w r2, r3, r12 ; CHECK-NEXT: eor.w r2, r3, r12
; CHECK-NEXT: orrs r0, r2 ; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: ands r0, r2 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, zr, r2, ne
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #8, #8 ; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, %c %c2 = icmp eq <2 x i64> %b, %c
%o = and <2 x i1> %c1, %c2 %o = and <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) { define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {
; CHECK-LABEL: cmpeqr_v2i1: ; CHECK-LABEL: cmpeqr_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r2, r3, d2 ; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: eors r3, r1 ; CHECK-NEXT: eors r3, r1
; CHECK-NEXT: eors r2, r0 ; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orr.w r12, r2, r3
; CHECK-NEXT: vmov r3, r2, d0 ; CHECK-NEXT: vmov r3, r2, d0
; CHECK-NEXT: cset r12, eq
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: cset r2, eq ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: and.w r2, r2, r12 ; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r2, zr, r2, ne
; CHECK-NEXT: rsbs r2, r2, #0 ; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: bfi r3, r2, #0, #8 ; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r12, r2, d3 ; CHECK-NEXT: vmov r12, r2, d3
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eor.w r0, r0, r12 ; CHECK-NEXT: eor.w r0, r0, r12
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r1, r2, d1
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq ; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r0, r1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, zr, r1, ne
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r3, r0, #8, #8 ; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: vmsr p0, r3 ; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%i = insertelement <2 x i64> undef, i64 %c, i32 0 %i = insertelement <2 x i64> undef, i64 %c, i32 0
%sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
%c2 = icmp eq <2 x i64> %b, %sp %c2 = icmp eq <2 x i64> %b, %sp
%o = and <2 x i1> %c1, %c2 %o = and <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }

llvm/test/CodeGen/Thumb2/mve-pred-or.ll

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
; CHECK-LABEL: cmpeqz_v2i1: ; CHECK-LABEL: cmpeqz_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d2 ; CHECK-NEXT: vmov r1, r2, d2
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq ; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: csinc r0, r1, zr, eq
; CHECK-NEXT: moveq r1, #1
; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #8 ; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1 ; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2 ; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d3 ; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: csinc r0, r2, zr, eq
; CHECK-NEXT: moveq r2, #1 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: rsbs r0, r2, #0
; CHECK-NEXT: bfi r1, r0, #8, #8 ; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, zeroinitializer %c2 = icmp eq <2 x i64> %b, zeroinitializer
%o = or <2 x i1> %c1, %c2 %o = or <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
; CHECK-LABEL: cmpeq_v2i1: ; CHECK-LABEL: cmpeq_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d4 ; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: vmov r2, r3, d2 ; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: eors r1, r3 ; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: it eq ; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: moveq r0, #1 ; CHECK-NEXT: csinc r0, r0, zr, eq
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #8 ; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: vmov r3, r0, d3 ; CHECK-NEXT: vmov r3, r0, d3
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: eor.w r2, r3, r12 ; CHECK-NEXT: eor.w r2, r3, r12
; CHECK-NEXT: orrs r0, r2 ; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: csinc r0, r0, zr, eq
; CHECK-NEXT: moveq r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #8, #8 ; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, %c %c2 = icmp eq <2 x i64> %b, %c
%o = or <2 x i1> %c1, %c2 %o = or <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmp.ll

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8 ; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1 ; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3 ; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8 ; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2 ; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vpsel q0, q0, q2 ; CHECK-NEXT: vpsel q0, q0, q2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #0, #8 ; CHECK-NEXT: bfi r0, r1, #0, #8
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #8, #8 ; CHECK-NEXT: bfi r0, r1, #8, #8
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q2, q0 ; CHECK-NEXT: vpsel q0, q2, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
%a7 = icmp slt <2 x i32> %a5, %c %a7 = icmp slt <2 x i32> %a5, %c
%a8 = icmp ne <2 x i32> %a5, zeroinitializer %a8 = icmp ne <2 x i32> %a5, zeroinitializer
%a9 = and <2 x i1> %a6, %a8 %a9 = and <2 x i1> %a6, %a8
%a10 = and <2 x i1> %a7, %a9 %a10 = and <2 x i1> %a7, %a9
%a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
ret <2 x i32> %a11 ret <2 x i32> %a11
} }

llvm/test/CodeGen/Thumb2/mve-vcmpf.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: cset r1, mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r1, r1, zr, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r2, mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r2, r2, zr, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r3, r3, zr, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: cset r1, eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r1, r1, zr, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r2, eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r2, r2, zr, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r3, r3, zr, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
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; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
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llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: cset r1, mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r1, r1, zr, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r2, mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r2, r2, zr, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r3, r3, zr, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
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; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: cset r1, eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r1, r1, zr, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r2, eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r2, r2, zr, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r3, r3, zr, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
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; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
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; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
▲ Show 20 Lines • Show All 566 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_r_one_v4f32: ; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: cset r1, mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r1, r1, zr, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r2, mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r2, r2, zr, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r3, r3, zr, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: cset r1, eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r1, r1, zr, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r2, eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r2, r2, zr, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r3, r3, zr, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
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; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
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llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: cset r1, mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r1, r1, zr, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r2, r2, zr, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r3, r3, zr, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
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; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: cset r1, eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r1, r1, zr, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r2, r2, zr, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r3, r3, zr, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
▲ Show 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
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; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
▲ Show 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_r_one_v4f32: ; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: cset r1, mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r1, r1, zr, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r2, r2, zr, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r3, r3, zr, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: cset r1, eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r1, r1, zr, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r2, r2, zr, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r3, r3, zr, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
▲ Show 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: csinc r0, r0, zr, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
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; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r0, eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: csinc r0, r0, zr, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
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llvm/test/CodeGen/Thumb2/mve-vcmpr.ll

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; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8 ; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1 ; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3 ; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8 ; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2 ; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vpsel q0, q0, q2 ; CHECK-NEXT: vpsel q0, q0, q2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #0, #8 ; CHECK-NEXT: bfi r0, r1, #0, #8
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #8, #8 ; CHECK-NEXT: bfi r0, r1, #8, #8
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q2, q0 ; CHECK-NEXT: vpsel q0, q2, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
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; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8 ; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1 ; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3 ; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8 ; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2 ; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vpsel q0, q0, q2 ; CHECK-NEXT: vpsel q0, q0, q2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #0, #8 ; CHECK-NEXT: bfi r0, r1, #0, #8
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs r2, r1, r3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: sbcs.w r2, r12, r3, asr #31
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, ne ; CHECK-NEXT: csel r12, zr, r2, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: asrs r3, r1, #31
; CHECK-NEXT: ands r1, r3 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: ands r1, r2 ; CHECK-NEXT: sbcs.w r1, r3, r2, asr #31
; CHECK-NEXT: csel r1, zr, r12, ge
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: bfi r0, r1, #8, #8 ; CHECK-NEXT: bfi r0, r1, #8, #8
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q2, q0 ; CHECK-NEXT: vpsel q0, q2, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
%a7 = icmp slt <2 x i32> %a5, %c %a7 = icmp slt <2 x i32> %a5, %c
%a8 = icmp ne <2 x i32> %a5, zeroinitializer %a8 = icmp ne <2 x i32> %a5, zeroinitializer
%a9 = and <2 x i1> %a6, %a8 %a9 = and <2 x i1> %a6, %a8
%a10 = and <2 x i1> %a7, %a9 %a10 = and <2 x i1> %a7, %a9
%a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
ret <2 x i32> %a11 ret <2 x i32> %a11
} }