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Allen (Allen zhong)
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Dec 25 2020, 11:39 PM (79 w, 2 d)

Recent Activity

Yesterday

Allen added a reviewer for D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast: xbolva00.
Sun, Jul 3, 6:12 PM · Restricted Project, Restricted Project
Allen updated the diff for D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast.
Sun, Jul 3, 6:09 PM · Restricted Project, Restricted Project

Fri, Jul 1

Allen abandoned D104679: [WIP][LoopUnrolling] Add flag to restrict the unroll with large loop size.

it seems fixed with https://reviews.llvm.org/D114650

Fri, Jul 1, 11:03 PM · Restricted Project, Restricted Project
Allen added inline comments to D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast.
Fri, Jul 1, 7:22 PM · Restricted Project, Restricted Project
Allen updated the diff for D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast.
Fri, Jul 1, 7:21 PM · Restricted Project, Restricted Project
Allen added a comment to D125774: [IndVars] Fold int->fp->int cast for small PHI node.

ping @nikic ?

Fri, Jul 1, 6:55 PM · Restricted Project, Restricted Project

Thu, Jun 30

Allen retitled D128606: [WIP][AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx from [AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx to [WIP][AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx.
Thu, Jun 30, 5:11 AM · Restricted Project, Restricted Project
Allen added a comment to D128606: [WIP][AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx.

Is this optimisation valid? The merging SVE intrinsics have strict rules about what happens to inactive lanes. For the llvm.aarch64.sve.and the inactive lanes are set to the matching lanes of the first operand. This means that the inactive lanes of the second operand play no role in the operation and thus the example in and_i64_zero_comm is not a zeroing and.

However, given the inactive lanes of the second operand play no role, this effectively means the select is redundant and can be optimised away as an instcombine before it gets to code generation. So I guess the question is whether you are seeing this issue in real code and thus it's worth implementing the instcombine.

Thu, Jun 30, 5:07 AM · Restricted Project, Restricted Project
Allen updated the summary of D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast.
Thu, Jun 30, 1:54 AM · Restricted Project, Restricted Project
Allen updated the summary of D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Thu, Jun 30, 1:54 AM · Restricted Project, Restricted Project
Allen requested review of D128895: [InstCombine] Make use of low zero bits to determine exact int->fp cast.
Thu, Jun 30, 1:52 AM · Restricted Project, Restricted Project

Wed, Jun 29

Allen committed rG404479b4b042: [InstCombine] Use known bits to determine exact int->fp cast (authored by Allen).
[InstCombine] Use known bits to determine exact int->fp cast
Wed, Jun 29, 6:48 PM · Restricted Project, Restricted Project
Allen closed D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Wed, Jun 29, 6:48 PM · Restricted Project, Restricted Project
Allen updated the diff for D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Wed, Jun 29, 6:35 PM · Restricted Project, Restricted Project

Sun, Jun 26

Allen added a comment to D127854: [InstCombine] Use known bits to determine exact int->fp cast.

ping @spatel @nikic ?

Sun, Jun 26, 5:59 PM · Restricted Project, Restricted Project
Allen abandoned D128283: [AArch64][SVE] Support optimized lowered selection with small SVE bits.
Sun, Jun 26, 5:50 PM · Restricted Project, Restricted Project
Allen requested review of D128606: [WIP][AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx.
Sun, Jun 26, 3:59 AM · Restricted Project, Restricted Project

Fri, Jun 24

Allen added a reviewer for D127854: [InstCombine] Use known bits to determine exact int->fp cast: RKSimon.
Fri, Jun 24, 1:03 AM · Restricted Project, Restricted Project
Allen updated the summary of D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Fri, Jun 24, 1:00 AM · Restricted Project, Restricted Project

Wed, Jun 22

Allen added a comment to D128283: [AArch64][SVE] Support optimized lowered selection with small SVE bits.

Hi @Allen, typically the SVE intrinsics only support legal types. This is a conscience choice because otherwise it will be very difficult to offer universal type support for all these target specific operations (i.e. where would we draw the line). Is there a reason not to use llvm.vector.reduce.and instead?

Wed, Jun 22, 4:55 AM · Restricted Project, Restricted Project

Tue, Jun 21

Allen updated the diff for D125774: [IndVars] Fold int->fp->int cast for small PHI node.

rebase to top

Tue, Jun 21, 6:02 PM · Restricted Project, Restricted Project
Allen added a reviewer for D125774: [IndVars] Fold int->fp->int cast for small PHI node: bsmith.
Tue, Jun 21, 5:52 PM · Restricted Project, Restricted Project
Allen requested review of D128283: [AArch64][SVE] Support optimized lowered selection with small SVE bits.
Tue, Jun 21, 7:58 AM · Restricted Project, Restricted Project
Allen added a comment to D127854: [InstCombine] Use known bits to determine exact int->fp cast.

ping ?

Tue, Jun 21, 6:12 AM · Restricted Project, Restricted Project
Allen added inline comments to D126201: [WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors..
Tue, Jun 21, 12:13 AM · Restricted Project, Restricted Project

Sat, Jun 18

Allen added inline comments to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
Sat, Jun 18, 10:42 PM · Restricted Project, Restricted Project
Allen updated the diff for D125774: [IndVars] Fold int->fp->int cast for small PHI node.

redo base in SCEV according comment

Sat, Jun 18, 5:39 AM · Restricted Project, Restricted Project

Fri, Jun 17

Allen added a comment to D127854: [InstCombine] Use known bits to determine exact int->fp cast.

rebase

I don't think this was updated correctly. There should be test diffs from the file fpcast.ll?

Fri, Jun 17, 8:14 AM · Restricted Project, Restricted Project
Allen updated the diff for D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Fri, Jun 17, 8:12 AM · Restricted Project, Restricted Project
Allen added inline comments to D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Fri, Jun 17, 6:49 AM · Restricted Project, Restricted Project
Allen updated the diff for D127854: [InstCombine] Use known bits to determine exact int->fp cast.

rebase

Fri, Jun 17, 6:48 AM · Restricted Project, Restricted Project
Allen committed rGb329156f4f14: [AArch64][LV] AArch64 does not prefer vectorized addressing (authored by TiehuZhang).
[AArch64][LV] AArch64 does not prefer vectorized addressing
Fri, Jun 17, 3:37 AM · Restricted Project, Restricted Project
Allen closed D124612: [AArch64][LV] AArch64 does not prefer vectorized addressing.
Fri, Jun 17, 3:37 AM · Restricted Project, Restricted Project

Thu, Jun 16

Allen added inline comments to D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Thu, Jun 16, 7:50 PM · Restricted Project, Restricted Project
Allen added inline comments to D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Thu, Jun 16, 3:21 AM · Restricted Project, Restricted Project
Allen updated the diff for D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Thu, Jun 16, 3:12 AM · Restricted Project, Restricted Project

Wed, Jun 15

Allen added inline comments to D125774: [IndVars] Fold int->fp->int cast for small PHI node.
Wed, Jun 15, 6:33 PM · Restricted Project, Restricted Project
Allen updated the diff for D127854: [InstCombine] Use known bits to determine exact int->fp cast.

Add more cases according https://reviews.llvm.org/D125774#inline-1222628

Wed, Jun 15, 6:26 PM · Restricted Project, Restricted Project
Allen requested review of D127854: [InstCombine] Use known bits to determine exact int->fp cast.
Wed, Jun 15, 6:34 AM · Restricted Project, Restricted Project
Allen added a comment to D125774: [IndVars] Fold int->fp->int cast for small PHI node.

I'm not strongly opposed to adding some basic IV reasoning to computeKnownBits(), but the implementation needs to be much more careful. I think there are at least three bugs here (missing check for predicate, no check whether this is a loop exit or continue condition, no reasoning about how the start value range relates to the end value). This requires much more extensive testing (and those tests should be simpler, not involving float operations).

Wed, Jun 15, 4:58 AM · Restricted Project, Restricted Project
Allen added inline comments to D125774: [IndVars] Fold int->fp->int cast for small PHI node.
Wed, Jun 15, 1:37 AM · Restricted Project, Restricted Project
Allen updated the diff for D125774: [IndVars] Fold int->fp->int cast for small PHI node.

Add checking the step is loop-invariant, and its loop's trip count is actually related to the PHI

Wed, Jun 15, 1:24 AM · Restricted Project, Restricted Project

Tue, Jun 14

Allen added inline comments to D126201: [WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors..
Tue, Jun 14, 1:45 AM · Restricted Project, Restricted Project
Allen retitled D127596: [WIP][AArch64][CodeGen] Support select address mode load/store from [AArch64][CodeGen] Support select address mode load/store to [WIP][AArch64][CodeGen] Support select address mode load/store.
Tue, Jun 14, 12:38 AM · Restricted Project, Restricted Project

Mon, Jun 13

Allen committed rG0cb33551ecd6: [AArch64][NFC] Fix a comment error (authored by Allen).
[AArch64][NFC] Fix a comment error
Mon, Jun 13, 10:59 PM · Restricted Project, Restricted Project
Allen closed D127708: [AArch64][NFC] Fix a comment error.
Mon, Jun 13, 10:58 PM · Restricted Project, Restricted Project
Allen added inline comments to D125774: [IndVars] Fold int->fp->int cast for small PHI node.
Mon, Jun 13, 8:28 PM · Restricted Project, Restricted Project
Allen added a comment to D127708: [AArch64][NFC] Fix a comment error.

@dmgreen

I'am sorry to missing apply your comment, https://reviews.llvm.org/D126700#inline-1223430
Mon, Jun 13, 7:47 PM · Restricted Project, Restricted Project
Allen requested review of D127708: [AArch64][NFC] Fix a comment error.
Mon, Jun 13, 7:44 PM · Restricted Project, Restricted Project
Allen added a comment to D127596: [WIP][AArch64][CodeGen] Support select address mode load/store.

I don't believe we want this functionality. We originally added it but then it got removed by D88994 as unsound because there's no instruction available to load/store predicates that are smaller than <vscale x 16 x i1>. At the C/C++ level we don't expose these "smaller" predicate types and so there shouldn't really be a route needed to load/store them. @Allen Do you have a real world use case where loading/storing them is required?

Mon, Jun 13, 7:35 AM · Restricted Project, Restricted Project
Herald added a project to D88994: Fix the default alignment of i1 vectors.: Restricted Project.
Mon, Jun 13, 7:17 AM · Restricted Project, Restricted Project, Restricted Project
Allen committed rG3cefcdb8c611: [test] Add test for D126700 NFC (authored by Allen).
[test] Add test for D126700 NFC
Mon, Jun 13, 3:38 AM · Restricted Project, Restricted Project
Allen committed rGc42a225545b4: [MachineScheduler] Order more stores by ascending address (authored by Allen).
[MachineScheduler] Order more stores by ascending address
Mon, Jun 13, 2:37 AM · Restricted Project, Restricted Project
Allen closed D126700: [MachineScheduler] Order more stores by ascending address.
Mon, Jun 13, 2:37 AM · Restricted Project, Restricted Project
Allen added inline comments to D126700: [MachineScheduler] Order more stores by ascending address.
Mon, Jun 13, 1:42 AM · Restricted Project, Restricted Project

Sun, Jun 12

Allen updated the diff for D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.

Add the check Level > AfterLegalizeVectorOps

Sun, Jun 12, 7:39 PM · Restricted Project, Restricted Project
Allen requested review of D127596: [WIP][AArch64][CodeGen] Support select address mode load/store.
Sun, Jun 12, 5:05 AM · Restricted Project, Restricted Project

Sat, Jun 11

Allen abandoned D127567: [CostModel] Fix the invalid cost for scalable vectors intrinsics.
Sat, Jun 11, 9:20 PM · Restricted Project, Restricted Project
Allen added a comment to D127567: [CostModel] Fix the invalid cost for scalable vectors intrinsics.

commit f85c5079b8d has fix this

Sat, Jun 11, 9:20 PM · Restricted Project, Restricted Project
Allen requested review of D127567: [CostModel] Fix the invalid cost for scalable vectors intrinsics.
Sat, Jun 11, 5:53 AM · Restricted Project, Restricted Project

Fri, Jun 10

Allen added inline comments to D125774: [IndVars] Fold int->fp->int cast for small PHI node.
Fri, Jun 10, 8:35 PM · Restricted Project, Restricted Project
Allen updated the diff for D126700: [MachineScheduler] Order more stores by ascending address.

update review comment

Fri, Jun 10, 3:01 AM · Restricted Project, Restricted Project
Allen added a comment to D125774: [IndVars] Fold int->fp->int cast for small PHI node.

Specifically detecting this exact case doesn't really seem very useful... we should be leveraging some sort of range analysis (known bits, CorrelatedValuePropagation, etc.)

Fri, Jun 10, 1:41 AM · Restricted Project, Restricted Project
Allen updated the diff for D125774: [IndVars] Fold int->fp->int cast for small PHI node.
Fri, Jun 10, 1:38 AM · Restricted Project, Restricted Project

Thu, Jun 9

Allen added a comment to D126700: [MachineScheduler] Order more stores by ascending address.

Also add subtarget feature ascend-store-address to control the aggressive order.

Thu, Jun 9, 1:29 AM · Restricted Project, Restricted Project
Allen updated the diff for D126700: [MachineScheduler] Order more stores by ascending address.
Thu, Jun 9, 1:27 AM · Restricted Project, Restricted Project

Tue, Jun 7

Allen added a comment to D126700: [MachineScheduler] Order more stores by ascending address.

OK I see, thanks. In this version on godbolt I only see ordered STPQ's, perhaps you have some downstream differences that would alter the codegen?
So - do you have any other benchmark results, on any other cpus? Or as an alternative, do you think that adding a subtarget feature is an OK solution?

Tue, Jun 7, 7:16 PM · Restricted Project, Restricted Project

Mon, Jun 6

Allen updated the diff for D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
Mon, Jun 6, 6:15 PM · Restricted Project, Restricted Project
Allen added a comment to D126700: [MachineScheduler] Order more stores by ascending address.

Do you have more details on where and when you expect this to be beneficial? It may not look like it from the review, but we did a fair amount of testing and benchmarking was done on D125377 on all kinds of CPUs (in-order vs out-of-order, little vs big, etc) to make sure that it was an improvement or benign on the cases we tried. I don't think I would be against this - so long as we had a decent reason to do so. It does constrain the scheduling graph though, so we shouldn't do so unnecessarily.

Mon, Jun 6, 5:53 AM · Restricted Project, Restricted Project

Sun, Jun 5

Herald added a project to D40306: [AArch64] Add patterns to replace fsub fmul with fma fneg.: Restricted Project.
Sun, Jun 5, 8:27 PM · Restricted Project

Jun 3 2022

Allen added a comment to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.

ping ?

Jun 3 2022, 6:28 PM · Restricted Project, Restricted Project

Jun 1 2022

Allen added a comment to D125377: [AArch64] Order STP Q's by ascending address.

Thanks @avieira for your detailed explanation, and according your idea, I extend more stores in D126700, can you help me review, thanks.

Jun 1 2022, 6:54 PM · Restricted Project, Restricted Project
Allen updated the diff for D126700: [MachineScheduler] Order more stores by ascending address.
Jun 1 2022, 6:48 PM · Restricted Project, Restricted Project
Allen abandoned D116309: [WIP][LoopVectorize] Convert switch blocks into branch sequence.
Jun 1 2022, 6:09 PM · Restricted Project, Restricted Project
Allen abandoned D121355: [WIP][SelectionDAG] Fold shift constants into cmp.
Jun 1 2022, 6:08 PM · Restricted Project, Restricted Project
Allen abandoned D125601: [DAGCombiner][AArch64] Reorder the bitcast of scalable vector.
Jun 1 2022, 6:08 PM · Restricted Project, Restricted Project
Allen added a comment to D126700: [MachineScheduler] Order more stores by ascending address.
Jun 1 2022, 9:08 AM · Restricted Project, Restricted Project

May 31 2022

Allen added a reviewer for D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate: paulwalker-arm.
May 31 2022, 6:12 PM · Restricted Project, Restricted Project
Allen updated the summary of D126700: [MachineScheduler] Order more stores by ascending address.
May 31 2022, 5:56 PM · Restricted Project, Restricted Project
Allen requested review of D126700: [MachineScheduler] Order more stores by ascending address.
May 31 2022, 7:01 AM · Restricted Project, Restricted Project

May 30 2022

Allen committed rG3e6ba89055c8: [InstCombine] Fold a mul with bool value into and (authored by Allen).
[InstCombine] Fold a mul with bool value into and
May 30 2022, 6:08 AM · Restricted Project, Restricted Project
Allen closed D126040: [InstCombine] Fold a mul with bool value into and.
May 30 2022, 6:08 AM · Restricted Project, Restricted Project

May 29 2022

Allen updated the diff for D126040: [InstCombine] Fold a mul with bool value into and.

Address comment and add a new test case scalar_mul_bit_x0_y0_uses

May 29 2022, 9:28 PM · Restricted Project, Restricted Project
Allen added inline comments to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
May 29 2022, 8:48 AM · Restricted Project, Restricted Project

May 28 2022

Allen updated the diff for D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.

Add new condtion to check that both vscales have the same types

May 28 2022, 4:56 PM · Restricted Project, Restricted Project
Allen added inline comments to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
May 28 2022, 3:59 PM · Restricted Project, Restricted Project
Allen added a comment to D126040: [InstCombine] Fold a mul with bool value into and.

hi @spatel , I'm sorry to trouble you again.

Now I already address all your comment before, should we wait another reviewer to also agree with this direction?
May 28 2022, 3:24 PM · Restricted Project, Restricted Project
Allen added a comment to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.

I don't claim to fully understand this, so my comment here might be off base.

I suspect your fold can be generalized as: fold a+truncate(vscale(c1))+truncate(vscale(c2)) to a+truncate(vscale(c1)+vscale(c2))

The vscale(c1)+vscale(c2) to vscale(C1 + C2) is handled separately above already.

If this is true, that your transform reduces to proving that it's legal to common the truncate. However, as a far as I known trunc(x) + trunc(y) is always equal to trunc(x+y). So why do we need this transform at all? Shouldn't this be covered by generic trunc folds and the existing rule?

Anyways, I'm clearly missing something here. Any idea what?

May 28 2022, 3:00 PM · Restricted Project, Restricted Project

May 27 2022

Allen updated the diff for D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
May 27 2022, 6:33 PM · Restricted Project, Restricted Project
Allen requested review of D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
May 27 2022, 5:40 AM · Restricted Project, Restricted Project

May 26 2022

Allen added a comment to D126040: [InstCombine] Fold a mul with bool value into and.

hi @nikic, would you please help me check this change ? thanks!

May 26 2022, 5:06 AM · Restricted Project, Restricted Project
Allen updated the diff for D126040: [InstCombine] Fold a mul with bool value into and.

address a missing comment

May 26 2022, 5:03 AM · Restricted Project, Restricted Project

May 25 2022

Allen added inline comments to D126040: [InstCombine] Fold a mul with bool value into and.
May 25 2022, 6:09 AM · Restricted Project, Restricted Project
Allen updated the diff for D126040: [InstCombine] Fold a mul with bool value into and.

leave the capture empty according comment

May 25 2022, 6:07 AM · Restricted Project, Restricted Project
Allen updated the diff for D126040: [InstCombine] Fold a mul with bool value into and.

rebase to the top after precommit the test cases

May 25 2022, 6:04 AM · Restricted Project, Restricted Project
Allen committed rG58b76492c1fe: [tests] precommit tests for D126040 (authored by Allen).
[tests] precommit tests for D126040
May 25 2022, 5:41 AM · Restricted Project, Restricted Project
Allen closed D126356: [tests] precommit tests for D126040.
May 25 2022, 5:41 AM · Restricted Project, Restricted Project
Allen added inline comments to D126040: [InstCombine] Fold a mul with bool value into and.
May 25 2022, 1:00 AM · Restricted Project, Restricted Project
Allen requested review of D126356: [tests] precommit tests for D126040.
May 25 2022, 12:56 AM · Restricted Project, Restricted Project
Allen added inline comments to D126040: [InstCombine] Fold a mul with bool value into and.
May 25 2022, 12:37 AM · Restricted Project, Restricted Project