[Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

[gonglingqin]

Summary

__cpucfg is required by Linux [1].

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h#n59

[xen0n]

Linux only requires __cpucfg among the ones you just added. Please amend the patch summary so it's more accurate.

Otherwise LGTM, thanks!

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

799

#undef ASRT_LE_GT_CASE afterwards?

[gonglingqin]

In D139915#3991089, @xen0n wrote:

Linux only requires __cpucfg among the ones you just added. Please amend the patch summary so it's more accurate.

Otherwise LGTM, thanks!

Thanks for your review, I will modify the summary.

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

799

Thanks! I will modify it. And there are other similar problems in this file, which I will modify later.

[gonglingqin]

Address @xen0n's comments.

[SixWeining]

LGTM except a small nit.

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

91

Better to leave some comment like line 82?

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

91

Thanks, I'll add comments.

[gonglingqin]

Add comment.

clang/include/clang/Basic/BuiltinsLoongArch.def

 #endif
 
 // TODO: Support more builtins.
 // TODO: Added feature constraints.
 TARGET_BUILTIN(__builtin_loongarch_dbar, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_ibar, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_break, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_syscall, "vIUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_cpucfg, "UiUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_asrtle_d, "vLiLi", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_asrtgt_d, "vLiLi", "nc", "64bit")
 
 TARGET_BUILTIN(__builtin_loongarch_crc_w_b_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crc_w_h_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crc_w_w_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crc_w_d_w, "iLii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crcc_w_b_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crcc_w_h_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crcc_w_w_w, "iii", "nc", "64bit")

 TARGET_BUILTIN(__builtin_loongarch_iocsrrd_h, "UiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_iocsrrd_w, "UiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_iocsrrd_d, "ULiUi", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_iocsrwr_b, "vUiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_iocsrwr_h, "vUiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_iocsrwr_w, "vUiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_iocsrwr_d, "vULiUi", "nc", "64bit")
 
+TARGET_BUILTIN(__builtin_loongarch_lddir_d, "LiLiIULi", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_ldpte_d, "vLiIULi", "nc", "64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

case LoongArch::BI__builtin_loongarch_iocsrwr_h:
     ID = Intrinsic::loongarch_iocsrwr_h;
     break;
   case LoongArch::BI__builtin_loongarch_iocsrwr_w:
     ID = Intrinsic::loongarch_iocsrwr_w;
     break;
   case LoongArch::BI__builtin_loongarch_iocsrwr_d:
     ID = Intrinsic::loongarch_iocsrwr_d;
     break;
+  case LoongArch::BI__builtin_loongarch_cpucfg:
+    ID = Intrinsic::loongarch_cpucfg;
+    break;
+  case LoongArch::BI__builtin_loongarch_asrtle_d:
+    ID = Intrinsic::loongarch_asrtle_d;
+    break;
+  case LoongArch::BI__builtin_loongarch_asrtgt_d:
+    ID = Intrinsic::loongarch_asrtgt_d;
+    break;
+  case LoongArch::BI__builtin_loongarch_lddir_d:
+    ID = Intrinsic::loongarch_lddir_d;
+    break;
+  case LoongArch::BI__builtin_loongarch_ldpte_d:
+    ID = Intrinsic::loongarch_ldpte_d;
+    break;
     // TODO: Support more Intrinsics.
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID);
   return Builder.CreateCall(F, Ops);
 }

clang/lib/Headers/larchintrin.h

 }
 
 extern __inline void
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     __iocsrwr_w(unsigned int _1, unsigned int _2) {
   __builtin_loongarch_iocsrwr_w((unsigned int)_1, (unsigned int)_2);
 }
 
+extern __inline unsigned int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __cpucfg(unsigned int _1) {
+  return (unsigned int)__builtin_loongarch_cpucfg((unsigned int)_1);
+}
+
 #if __loongarch_grlen == 64
 extern __inline void
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     __iocsrwr_d(unsigned long int _1, unsigned int _2) {
   __builtin_loongarch_iocsrwr_d((unsigned long int)_1, (unsigned int)_2);
 }
+
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __asrtgt_d(long int _1, long int _2) {
+  __builtin_loongarch_asrtgt_d((long int)_1, (long int)_2);
+}
+
+extern __inline void
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __asrtle_d(long int _1, long int _2) {
+  __builtin_loongarch_asrtle_d((long int)_1, (long int)_2);
+}
+#endif
+
+#if __loongarch_grlen == 64
+#define __lddir_d(/*long int*/ _1, /*ui5*/ _2)                                 \
+  ((long int)__builtin_loongarch_lddir_d((long int)(_1), (_2)))
+
+#define __ldpte_d(/*long int*/ _1, /*ui5*/ _2)                                 \
+  ((void)__builtin_loongarch_ldpte_d((long int)(_1), (_2)))
 #endif
 
 #ifdef __cplusplus
 }
 #endif
 #endif /* _LOONGARCH_BASE_INTRIN_H */

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
   case LoongArch::BI__builtin_loongarch_crc_w_w_w:
   case LoongArch::BI__builtin_loongarch_crc_w_d_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_b_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_h_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_w_w:
   case LoongArch::BI__builtin_loongarch_crcc_w_d_w:
   case LoongArch::BI__builtin_loongarch_iocsrrd_d:
   case LoongArch::BI__builtin_loongarch_iocsrwr_d:
+  case LoongArch::BI__builtin_loongarch_asrtle_d:
+  case LoongArch::BI__builtin_loongarch_asrtgt_d:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)
              << TheCall->getSourceRange();
     break;
   case LoongArch::BI__builtin_loongarch_break:
   case LoongArch::BI__builtin_loongarch_dbar:
   case LoongArch::BI__builtin_loongarch_ibar:
if (!TI.hasFeature("64bit"))
              << TheCall->getSourceRange();
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 16383);
   case LoongArch::BI__builtin_loongarch_csrxchg_d:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)
              << TheCall->getSourceRange();
     return SemaBuiltinConstantArgRange(TheCall, 2, 0, 16383);
+  case LoongArch::BI__builtin_loongarch_lddir_d:
+  case LoongArch::BI__builtin_loongarch_ldpte_d:
+    if (!TI.hasFeature("64bit"))
+      return Diag(TheCall->getBeginLoc(),
+                  diag::err_loongarch_builtin_requires_la64)
+             << TheCall->getSourceRange();
+    return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
   }
 
   return false;
 }
 
 bool Sema::CheckMipsBuiltinFunctionCall(const TargetInfo &TI,
                                         unsigned BuiltinID, CallExpr *TheCall) {
   return CheckMipsBuiltinCpu(TI, BuiltinID, TheCall) ||

clang/test/CodeGen/LoongArch/intrinsic-la32-error.c

 
 unsigned long int iocsrrd_d(unsigned int a) {
   return __builtin_loongarch_iocsrrd_d(a); // expected-error {{this builtin requires target: loongarch64}}
 }
 
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __builtin_loongarch_iocsrwr_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void asrtle_d(long int a, long int b) {
+  __builtin_loongarch_asrtle_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+void asrtgt_d(long int a, long int b) {
+  __builtin_loongarch_asrtgt_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+void lddir_d(long int a, int b) {
+  __builtin_loongarch_lddir_d(a, 1); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+void ldpte_d(long int a, int b) {
+  __builtin_loongarch_ldpte_d(a, 1); // expected-error {{this builtin requires target: loongarch64}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la32.c

 // LA32-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A:%.*]], i32 [[B:%.*]])
 // LA32-NEXT:    tail call void @llvm.loongarch.iocsrwr.w(i32 [[A]], i32 [[B]])
 // LA32-NEXT:    ret void
 //
 void iocsrwr_w(unsigned int a, unsigned int b) {
   __iocsrwr_w(a, b);
   __builtin_loongarch_iocsrwr_w(a, b);
 }
+
+// LA32-LABEL: @cpucfg(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.cpucfg(i32 [[A:%.*]])
+// LA32-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.cpucfg(i32 [[A]])
+// LA32-NEXT:    ret i32 0
+//
+unsigned int cpucfg(unsigned int a) {
+  unsigned int b = __cpucfg(a);
+  unsigned int c = __builtin_loongarch_cpucfg(a);
+  return 0;
+}

clang/test/CodeGen/LoongArch/intrinsic-la64-error.c

void csrwr_d(unsigned long int a) {
   __builtin_loongarch_csrwr_d(a, a); // expected-error {{argument to '__builtin_loongarch_csrwr_d' must be a constant integer}}
 }
 
 void csrxchg_d(unsigned long int a, unsigned long int b) {
   __builtin_loongarch_csrxchg_d(a, b, 16384); // expected-error {{argument value 16384 is outside the valid range [0, 16383]}}
   __builtin_loongarch_csrxchg_d(a, b, -1); // expected-error {{argument value 4294967295 is outside the valid range [0, 16383]}}
   __builtin_loongarch_csrxchg_d(a, b, b); // expected-error {{argument to '__builtin_loongarch_csrxchg_d' must be a constant integer}}
 }
+
+void lddir_d(long int a, int b) {
+  __builtin_loongarch_lddir_d(a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}}
+  __builtin_loongarch_lddir_d(a, -1); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 31]}}
+  __builtin_loongarch_lddir_d(a, b); // expected-error {{argument to '__builtin_loongarch_lddir_d' must be a constant integer}}
+}
+
+void ldpte_d(long int a, int b) {
+  __builtin_loongarch_ldpte_d(a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}}
+  __builtin_loongarch_ldpte_d(a, -1); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 31]}}
+  __builtin_loongarch_ldpte_d(a, b); // expected-error {{argument to '__builtin_loongarch_ldpte_d' must be a constant integer}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la64.c

 // CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A:%.*]], i32 [[B:%.*]])
 // CHECK-NEXT:    tail call void @llvm.loongarch.iocsrwr.d(i64 [[A]], i32 [[B]])
 // CHECK-NEXT:    ret void
 //
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __iocsrwr_d(a, b);
   __builtin_loongarch_iocsrwr_d(a, b);
 }
+
+// CHECK-LABEL: @asrtle_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.asrtle.d(i64 [[A:%.*]], i64 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.asrtle.d(i64 [[A]], i64 [[B]])
+// CHECK-NEXT:    ret void
+//
+void asrtle_d(long int a, long int b) {
+  __asrtle_d(a, b);
+  __builtin_loongarch_asrtle_d(a, b);
+}
+
+// CHECK-LABEL: @asrtgt_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.asrtgt.d(i64 [[A:%.*]], i64 [[B:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.asrtgt.d(i64 [[A]], i64 [[B]])
+// CHECK-NEXT:    ret void
+//
+void asrtgt_d(long int a, long int b) {
+  __asrtgt_d(a, b);
+  __builtin_loongarch_asrtgt_d(a, b);
+}
+
+// CHECK-LABEL: @lddir_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.loongarch.lddir.d(i64 [[A:%.*]], i64 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.loongarch.lddir.d(i64 [[A]], i64 1)
+// CHECK-NEXT:    ret i64 0
+//
+long int lddir_d(long int a) {
+  long int b = __lddir_d(a, 1);
+  long int c = __builtin_loongarch_lddir_d(a, 1);
+  return 0;
+}
+
+// CHECK-LABEL: @ldpte_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.ldpte.d(i64 [[A:%.*]], i64 1)
+// CHECK-NEXT:    tail call void @llvm.loongarch.ldpte.d(i64 [[A]], i64 1)
+// CHECK-NEXT:    ret void
+//
+void ldpte_d(long int a) {
+  __ldpte_d(a, 1);
+  __builtin_loongarch_ldpte_d(a, 1);
+}
+
+// CHECK-LABEL: @cpucfg(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.cpucfg(i32 [[A:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.cpucfg(i32 [[A]])
+// CHECK-NEXT:    ret i32 0
+//
+unsigned int cpucfg(unsigned int a) {
+  unsigned int b = __cpucfg(a);
+  unsigned int c = __builtin_loongarch_cpucfg(a);
+  return 0;
+}

llvm/include/llvm/IR/IntrinsicsLoongArch.td

 def int_loongarch_iocsrrd_h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
 def int_loongarch_iocsrrd_w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
 def int_loongarch_iocsrrd_d : Intrinsic<[llvm_i64_ty], [llvm_i32_ty]>;
 
 def int_loongarch_iocsrwr_b : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_iocsrwr_h : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_iocsrwr_w : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_iocsrwr_d : Intrinsic<[], [llvm_i64_ty, llvm_i32_ty]>;
+
+def int_loongarch_cpucfg : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>;
+
+def int_loongarch_asrtle_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>;
+def int_loongarch_asrtgt_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty]>;
+
+def int_loongarch_lddir_d : Intrinsic<[llvm_i64_ty],
+                                      [llvm_i64_ty, llvm_i64_ty],
+                                      [ImmArg<ArgIndex<1>>]>;
+def int_loongarch_ldpte_d : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty],
+                                          [ImmArg<ArgIndex<1>>]>;
 } // TargetPrefix = "loongarch"

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

enum NodeType : unsigned {
   IOCSRRD_B,
   IOCSRRD_W,
   IOCSRRD_H,
   IOCSRRD_D,
   IOCSRWR_B,
   IOCSRWR_H,
   IOCSRWR_W,
   IOCSRWR_D,
+
+  // Read CPU configuration information operation
+  CPUCFG,
 };
 } // end namespace LoongArchISD
 
 class LoongArchTargetLowering : public TargetLowering {
   const LoongArchSubtarget &Subtarget;
 
 public:
   explicit LoongArchTargetLowering(const TargetMachine &TM,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
     setOperationAction(ISD::ROTR, MVT::i32, Custom);
     setOperationAction(ISD::ROTL, MVT::i32, Custom);
     setOperationAction(ISD::CTTZ, MVT::i32, Custom);
     setOperationAction(ISD::CTLZ, MVT::i32, Custom);
     setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
+    setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
     setOperationAction(ISD::READ_REGISTER, MVT::i32, Custom);
     setOperationAction(ISD::WRITE_REGISTER, MVT::i32, Custom);
     if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     if (Subtarget.hasBasicF())
       setOperationAction(ISD::FRINT, MVT::f32, Legal);
     if (Subtarget.hasBasicD())
       setOperationAction(ISD::FRINT, MVT::f64, Legal);
return DAG.getMergeValues(                                                 \
         {DAG.getNode(LoongArchISD::NODE, DL, GRLenVT, Op0, Op.getOperand(2)),  \
          Op0},                                                                 \
         DL);                                                                   \
   }
     IOCSRRD_CASE(iocsrrd_b, IOCSRRD_B);
     IOCSRRD_CASE(iocsrrd_h, IOCSRRD_H);
     IOCSRRD_CASE(iocsrrd_w, IOCSRRD_W);
 #undef IOCSRRD_CASE
+  case Intrinsic::loongarch_cpucfg: {
+    return DAG.getMergeValues(
+        {DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT, Op0, Op.getOperand(2)),
+         Op0},
+        DL);
+  }
+  case Intrinsic::loongarch_lddir_d: {
+    unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
+    if (!isUInt<8>(Imm)) {
+      DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) +
+                                  "' out of range");
+      return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL);
+    }
+
+    return Op;
+  }
   }
 }
 
 // Helper function that emits error message for intrinsics with void return
 // value.
 static SDValue emitIntrinsicErrorMessage(SDValue Op, StringRef ErrorMsg,
                                          SelectionDAG &DAG) {
 
if (Subtarget.is64Bit())
           LoongArchISD::IOCSRWR_D, DL, MVT::Other, Op0, Op2,
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(3)));
     else {
       DAG.getContext()->emitError(
           "llvm.loongarch.iocsrwr.d requires target: loongarch64");
       return Op.getOperand(0);
     }
   }
+#define ASRT_LE_GT_CASE(NAME)                                                  \
+  case Intrinsic::loongarch_##NAME: {                                          \
+    if (!Subtarget.is64Bit()) {                                                \
+      DAG.getContext()->emitError(Op->getOperationName(0) +                    \
+                                  " requires target: loongarch64");            \
+      return Op.getOperand(0);                                                 \
+    }                                                                          \
+    return Op;                                                                 \
+  }
+    ASRT_LE_GT_CASE(asrtle_d)
+    ASRT_LE_GT_CASE(asrtgt_d)
+#undef ASRT_LE_GT_CASE
+  case Intrinsic::loongarch_ldpte_d: {
+    unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
+    if (!isUInt<8>(Imm))
+      return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
+    if (!Subtarget.is64Bit()) {
+      DAG.getContext()->emitError(Op->getOperationName(0) +
+                                  " requires target: loongarch64");
+      return Op.getOperand(0);
+    }
+    return Op;
+  }
   }
 }
 
 SDValue LoongArchTargetLowering::lowerShiftLeftParts(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Lo = Op.getOperand(0);
   SDValue Hi = Op.getOperand(1);
Results.push_back(DAG.getNode(                                             \
                     DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2))));        \
     Results.push_back(N->getOperand(0));                                       \
     break;                                                                     \
   }
       IOCSRRD_CASE(iocsrrd_b, IOCSRRD_B);
       IOCSRRD_CASE(iocsrrd_h, IOCSRRD_H);
       IOCSRRD_CASE(iocsrrd_w, IOCSRRD_W);
 #undef IOCSRRD_CASE
+    case Intrinsic::loongarch_cpucfg: {
+      Results.push_back(DAG.getNode(
+          ISD::TRUNCATE, DL, VT,
+          DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT, Op0,
+                      DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2))));
+      Results.push_back(Op0);
+      break;
+    }
+    case Intrinsic::loongarch_lddir_d: {
+      if (!Subtarget.is64Bit()) {
+        DAG.getContext()->emitError(N->getOperationName(0) +
+                                    " requires target: loongarch64");
+        Results.push_back(DAG.getUNDEF(VT));
+        Results.push_back(Op0);
+        break;
+      }
+      break;
+    }
     }
     break;
   }
   case ISD::READ_REGISTER: {
     if (Subtarget.is64Bit())
       DAG.getContext()->emitError(
           "On LA64, only 64-bit registers can be read.");
     else
case LoongArchISD::node:                                                     \
     NODE_NAME_CASE(IOCSRRD_B)
     NODE_NAME_CASE(IOCSRRD_H)
     NODE_NAME_CASE(IOCSRRD_W)
     NODE_NAME_CASE(IOCSRRD_D)
     NODE_NAME_CASE(IOCSRWR_B)
     NODE_NAME_CASE(IOCSRWR_H)
     NODE_NAME_CASE(IOCSRWR_W)
     NODE_NAME_CASE(IOCSRWR_D)
+    NODE_NAME_CASE(CPUCFG)
   }
 #undef NODE_NAME_CASE
   return nullptr;
 }
 
 //===----------------------------------------------------------------------===//
 //                     Calling Convention Implementation
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

def loongarch_iocsrwr_h : SDNode<"LoongArchISD::IOCSRWR_H",
                                   SDT_LoongArchIocsrwr,
                                   [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_iocsrwr_w : SDNode<"LoongArchISD::IOCSRWR_W",
                                   SDT_LoongArchIocsrwr,
                                   [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_iocsrwr_d : SDNode<"LoongArchISD::IOCSRWR_D",
                                   SDT_LoongArchIocsrwr,
                                   [SDNPHasChain, SDNPSideEffect]>;
+def loongarch_cpucfg : SDNode<"LoongArchISD::CPUCFG", SDTUnaryOp,
+                               [SDNPHasChain, SDNPSideEffect]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
 class ImmAsmOperand<string prefix, int width, string suffix>
     : AsmOperandClass {
   let Name = prefix # "Imm" # width # suffix;

 def uimm5 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5>;
 }
 
 def uimm6 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<6>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<6>;
 }
 
-def uimm8 : Operand<GRLenVT> {
+def uimm8 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<8>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<8>;
 }
 
 class UImm12Operand : Operand<GRLenVT>,
                       ImmLeaf <GRLenVT, [{return isUInt<12>(Imm);}]> {
   let DecoderMethod = "decodeUImmOperand<12>";
 }
 

 def : Pat<(loongarch_iocsrrd_b GPR:$rj), (IOCSRRD_B GPR:$rj)>;
 def : Pat<(loongarch_iocsrrd_h GPR:$rj), (IOCSRRD_H GPR:$rj)>;
 def : Pat<(loongarch_iocsrrd_w GPR:$rj), (IOCSRRD_W GPR:$rj)>;
 
 def : Pat<(loongarch_iocsrwr_b GPR:$rd, GPR:$rj), (IOCSRWR_B GPR:$rd, GPR:$rj)>;
 def : Pat<(loongarch_iocsrwr_h GPR:$rd, GPR:$rj), (IOCSRWR_H GPR:$rd, GPR:$rj)>;
 def : Pat<(loongarch_iocsrwr_w GPR:$rd, GPR:$rj), (IOCSRWR_W GPR:$rd, GPR:$rj)>;
 
+def : Pat<(loongarch_cpucfg GPR:$rj), (CPUCFG GPR:$rj)>;
+
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_iocsrrd_d GPR:$rj), (IOCSRRD_D GPR:$rj)>;
 def : Pat<(loongarch_iocsrwr_d GPR:$rd, GPR:$rj), (IOCSRWR_D GPR:$rd, GPR:$rj)>;
+def : Pat<(int_loongarch_asrtle_d GPR:$rj, GPR:$rk),
+          (ASRTLE_D GPR:$rj, GPR:$rk)>;
+def : Pat<(int_loongarch_asrtgt_d GPR:$rj, GPR:$rk),
+          (ASRTGT_D GPR:$rj, GPR:$rk)>;
+def : Pat<(int_loongarch_lddir_d GPR:$rj, timm:$imm8),
+          (LDDIR GPR:$rj, uimm8:$imm8)>;
+def : Pat<(int_loongarch_ldpte_d GPR:$rj, timm:$imm8),
+          (LDPTE GPR:$rj, uimm8:$imm8)>;
 } // Predicates = [IsLA64]

llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll

 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
 declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i32)
+declare void @llvm.loongarch.ldpte.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
 entry:
   %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
   ret i32 %res
 }
 

 }
 
 define void @iocsrwr_d(i64 %a, i32 signext %b) {
 ; CHECK: llvm.loongarch.iocsrwr.d requires target: loongarch64
 entry:
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK: llvm.loongarch.lddir.d requires target: loongarch64
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK: llvm.loongarch.ldpte.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i32 1)
+  ret void
+}

llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
 declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i64)
+declare void @llvm.loongarch.ldpte.d(i64, i64)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    crc.w.b.w $a0, $a0, $a1
 ; CHECK-NEXT:    ret
   %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
   ret i32 %res

 ; CHECK-LABEL: iocsrwr_d:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    iocsrwr.d $a0, $a1
 ; CHECK-NEXT:    ret
 entry:
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtle_d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    asrtle.d $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtgt_d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    asrtgt.d $a0, $a1
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK-LABEL: lddir_d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lddir $a0, $a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK-LABEL: ldpte_d:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ldpte $a0, 1
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
+  ret void
+}

llvm/test/CodeGen/LoongArch/intrinsic.ll

 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 declare i32 @llvm.loongarch.iocsrrd.b(i32)
 declare i32 @llvm.loongarch.iocsrrd.h(i32)
 declare i32 @llvm.loongarch.iocsrrd.w(i32)
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)
 declare void @llvm.loongarch.iocsrwr.h(i32, i32)
 declare void @llvm.loongarch.iocsrwr.w(i32, i32)
+declare i32 @llvm.loongarch.cpucfg(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    dbar 0
 ; CHECK-NEXT:    ret
 entry:
   call void @llvm.loongarch.dbar(i32 0)

 ; CHECK-LABEL: iocsrwr_w:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    iocsrwr.w $a0, $a1
 ; CHECK-NEXT:    ret
 entry:
   tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
   ret void
 }
+
+define i32 @cpucfg(i32 %a) {
+; CHECK-LABEL: cpucfg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cpucfg $a0, $a0
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.cpucfg(i32 %a)
+  ret i32 %0
+}