InstSimplify: Add basic folding of llvm.is.fpclass intrinsic

[arsenm]

Summary

Copied from the existing llvm.amdgcn.class handling; eventually I will
fold that to the generic intrinsic when legal. The tests should
probably move into an instsimplify only test.

[tschuett]

Are there any plans for a Mask2Enum function such that your code could become a switch statement?

[arsenm]

In D139772#3986454, @tschuett wrote:

Are there any plans for a Mask2Enum function such that your code could become a switch statement?

I don't see how that would help here. Each bit test needs to be performed in sequence, it's not a simple enum mapping

[arsenm]

d647e252b82f6b2cca291449ab9c18b441bb4f95

llvm/lib/Analysis/ConstantFolding.cpp

bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
   case Intrinsic::x86_avx512_cvttsd2usi:
   case Intrinsic::x86_avx512_cvttsd2usi64:
     return !Call->isStrictFP();
 
   // Sign operations are actually bitwise operations, they do not raise
   // exceptions even for SNANs.
   case Intrinsic::fabs:
   case Intrinsic::copysign:
+  case Intrinsic::is_fpclass:
   // Non-constrained variants of rounding operations means default FP
   // environment, they can be folded in any case.
   case Intrinsic::ceil:
   case Intrinsic::floor:
   case Intrinsic::round:
   case Intrinsic::roundeven:
   case Intrinsic::trunc:
   case Intrinsic::nearbyint:
if (const auto *Op2 = dyn_cast<ConstantFP>(Operands[1])) {
         [[fallthrough]];
       case LibFunc_atan2_finite:
       case LibFunc_atan2f_finite:
         if (TLI->has(Func))
           return ConstantFoldBinaryFP(atan2, Op1V, Op2V, Ty);
         break;
       }
     } else if (auto *Op2C = dyn_cast<ConstantInt>(Operands[1])) {
+      switch (IntrinsicID) {
+      case Intrinsic::is_fpclass: {
+        uint32_t Mask = Op2C->getZExtValue();
+        bool Result =
+          ((Mask & fcSNan) && Op1V.isNaN() && Op1V.isSignaling()) ||
+          ((Mask & fcQNan) && Op1V.isNaN() && !Op1V.isSignaling()) ||
+          ((Mask & fcNegInf) && Op1V.isInfinity() && Op1V.isNegative()) ||
+          ((Mask & fcNegNormal) && Op1V.isNormal() && Op1V.isNegative()) ||
+          ((Mask & fcNegSubnormal) && Op1V.isDenormal() && Op1V.isNegative()) ||
+          ((Mask & fcNegZero) && Op1V.isZero() && Op1V.isNegative()) ||
+          ((Mask & fcPosZero) && Op1V.isZero() && !Op1V.isNegative()) ||
+          ((Mask & fcPosSubnormal) && Op1V.isDenormal() && !Op1V.isNegative()) ||
+          ((Mask & fcPosNormal) && Op1V.isNormal() && !Op1V.isNegative()) ||
+          ((Mask & fcPosInf) && Op1V.isInfinity() && !Op1V.isNegative());
+        return ConstantInt::get(Ty, Result);
+      }
+      default:
+        break;
+      }
+
       if (!Ty->isHalfTy() && !Ty->isFloatTy() && !Ty->isDoubleTy())
         return nullptr;
       if (IntrinsicID == Intrinsic::powi && Ty->isHalfTy())
         return ConstantFP::get(
             Ty->getContext(),
             APFloat((float)std::pow((float)Op1V.convertToDouble(),
                                     (int)Op2C->getZExtValue())));
       if (IntrinsicID == Intrinsic::powi && Ty->isFloatTy())

llvm/lib/Analysis/InstructionSimplify.cpp

case Intrinsic::copysign:
     if (Op0 == Op1)
       return Op0;
     // copysign -X, X --> X
     // copysign X, -X --> -X
     if (match(Op0, m_FNeg(m_Specific(Op1))) ||
         match(Op1, m_FNeg(m_Specific(Op0))))
       return Op1;
     break;
+  case Intrinsic::is_fpclass: {
+    if (isa<PoisonValue>(Op0))
+      return PoisonValue::get(ReturnType);
+
+    uint64_t Mask = cast<ConstantInt>(Op1)->getZExtValue();
+    // If all tests are made, it doesn't matter what the value is.
+    if ((Mask & fcAllFlags) == fcAllFlags)
+      return ConstantInt::get(ReturnType, true);
+    if ((Mask & fcAllFlags) == 0)
+      return ConstantInt::get(ReturnType, false);
+    if (Q.isUndefValue(Op0))
+      return UndefValue::get(ReturnType);
+    break;
+  }
   case Intrinsic::maxnum:
   case Intrinsic::minnum:
   case Intrinsic::maximum:
   case Intrinsic::minimum: {
     // If the arguments are the same, this is a no-op.
     if (Op0 == Op1)
       return Op0;
 

llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll

 ; GFX7CHECK:       ; %bb.0:
 ; GFX7CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX7CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8CHECK-LABEL: zeromask_f16:
 ; GFX8CHECK:       ; %bb.0:
 ; GFX8CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT:    v_cmp_class_f16_e64 s[4:5], v0, 0
-; GFX8CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX8CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX8CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9CHECK-LABEL: zeromask_f16:
 ; GFX9CHECK:       ; %bb.0:
 ; GFX9CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT:    v_cmp_class_f16_e64 s[4:5], v0, 0
-; GFX9CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10CHECK-LABEL: zeromask_f16:
 ; GFX10CHECK:       ; %bb.0:
 ; GFX10CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10CHECK-NEXT:    v_cmp_class_f16_e64 s4, v0, 0
-; GFX10CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11CHECK-LABEL: zeromask_f16:
 ; GFX11CHECK:       ; %bb.0:
 ; GFX11CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11CHECK-NEXT:    v_cmp_class_f16_e64 s0, v0, 0
-; GFX11CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX11CHECK-NEXT:    s_setpc_b64 s[30:31]
   %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 0)
   ret i1 %1
 }
 
+; FIXME: DAG and GlobalISel return different values for i1 true
 define i1 @allflags_f16(half %x) nounwind {
 ; GFX7SELDAG-LABEL: allflags_f16:
 ; GFX7SELDAG:       ; %bb.0:
 ; GFX7SELDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7SELDAG-NEXT:    v_mov_b32_e32 v0, 1
 ; GFX7SELDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7GLISEL-LABEL: allflags_f16:
 ; GFX7GLISEL:       ; %bb.0:
 ; GFX7GLISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7GLISEL-NEXT:    v_mov_b32_e32 v0, -1
 ; GFX7GLISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8CHECK-LABEL: allflags_f16:
 ; GFX8CHECK:       ; %bb.0:
 ; GFX8CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT:    v_mov_b32_e32 v1, 0x3ff
-; GFX8CHECK-NEXT:    v_cmp_class_f16_e32 vcc, v0, v1
-; GFX8CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8CHECK-NEXT:    v_mov_b32_e32 v0, {{(-)?}}1
 ; GFX8CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9CHECK-LABEL: allflags_f16:
 ; GFX9CHECK:       ; %bb.0:
 ; GFX9CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT:    v_mov_b32_e32 v1, 0x3ff
-; GFX9CHECK-NEXT:    v_cmp_class_f16_e32 vcc, v0, v1
-; GFX9CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9CHECK-NEXT:    v_mov_b32_e32 v0, {{(-)?}}1
 ; GFX9CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10CHECK-LABEL: allflags_f16:
 ; GFX10CHECK:       ; %bb.0:
 ; GFX10CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10CHECK-NEXT:    v_cmp_class_f16_e64 s4, v0, 0x3ff
-; GFX10CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10CHECK-NEXT:    v_mov_b32_e32 v0, {{(-)?}}1
 ; GFX10CHECK-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11CHECK-LABEL: allflags_f16:
 ; GFX11CHECK:       ; %bb.0:
 ; GFX11CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11CHECK-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x3ff
-; GFX11CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11CHECK-NEXT:    v_mov_b32_e32 v0, {{(-)?}}1
 ; GFX11CHECK-NEXT:    s_setpc_b64 s[30:31]
   %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1023) ; 0x3ff
   ret i1 %1
 }
 
 define i1 @snan_f16(half %x) nounwind {
 ; GFX7SELDAG-LABEL: snan_f16:
 ; GFX7SELDAG:       ; %bb.0:

llvm/test/Transforms/InstCombine/is_fpclass.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
 
 ; --------------------------------------------------------------------
 ; llvm.is.fpclass
 ; --------------------------------------------------------------------
 
 ; FIXME: Should this really be immarg?
 ; define i1 @test_class_undef_mask_f32(float %x) {
 ;   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 undef)
 ;   ret i1 %val
 ; }
 
 define i1 @test_class_no_mask_f32(float %x) {
 ; CHECK-LABEL: @test_class_no_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 0)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 0)
   ret i1 %val
 }
 
 define i1 @test_class_full_mask_f32(float %x) {
 ; CHECK-LABEL: @test_class_full_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1023)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
   ret i1 %val
 }
 
 define i1 @test_class_undef_no_mask_f32() {
 ; CHECK-LABEL: @test_class_undef_no_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
   ret i1 %val
 }
 
 define i1 @test_class_undef_full_mask_f32() {
 ; CHECK-LABEL: @test_class_undef_full_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 1023)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f32(float undef, i32 1023)
   ret i1 %val
 }
 
 define i1 @test_class_poison_no_mask_f32() {
 ; CHECK-LABEL: @test_class_poison_no_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 0)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 poison
 ;
   %val = call i1 @llvm.is.fpclass.f32(float poison, i32 0)
   ret i1 %val
 }
 
 define i1 @test_class_poison_full_mask_f32() {
 ; CHECK-LABEL: @test_class_poison_full_mask_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 1023)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 poison
 ;
   %val = call i1 @llvm.is.fpclass.f32(float poison, i32 1023)
   ret i1 %val
 }
 
 define i1 @test_class_undef_val_f32() {
 ; CHECK-LABEL: @test_class_undef_val_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 undef
 ;
   %val = call i1 @llvm.is.fpclass.f32(float undef, i32 4)
   ret i1 %val
 }
 
 define i1 @test_class_poison_val_f32() {
 ; CHECK-LABEL: @test_class_poison_val_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 poison
 ;
   %val = call i1 @llvm.is.fpclass.f32(float poison, i32 4)
   ret i1 %val
 }
 
 ; FIXME: Should this really be immarg?
 ; define i1 @test_class_undef_undef_f32() {
 ;   %val = call i1 @llvm.is.fpclass.f32(float undef, i32 undef)

 ; CHECK-NEXT:    ret i1 [[VAL]]
 ;
   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp
   ret i1 %val
 }
 
 define i1 @test_constant_class_snan_test_snan_f64() {
 ; CHECK-LABEL: @test_constant_class_snan_test_snan_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 1)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 1)
   ret i1 %val
 }
 
 define i1 @test_constant_class_qnan_test_qnan_f64() {
 ; CHECK-LABEL: @test_constant_class_qnan_test_qnan_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 2)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 2)
   ret i1 %val
 }
 
 define i1 @test_constant_class_qnan_test_snan_f64() {
 ; CHECK-LABEL: @test_constant_class_qnan_test_snan_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 1)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 1)
   ret i1 %val
 }
 
 define i1 @test_constant_class_ninf_test_ninf_f64() {
 ; CHECK-LABEL: @test_constant_class_ninf_test_ninf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 4)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pinf_test_ninf_f64() {
 ; CHECK-LABEL: @test_constant_class_pinf_test_ninf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 4)
   ret i1 %val
 }
 
 define i1 @test_constant_class_qnan_test_ninf_f64() {
 ; CHECK-LABEL: @test_constant_class_qnan_test_ninf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 4)
   ret i1 %val
 }
 
 define i1 @test_constant_class_snan_test_ninf_f64() {
 ; CHECK-LABEL: @test_constant_class_snan_test_ninf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 4)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 4)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nnormal_test_nnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_nnormal_test_nnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -1.000000e+00, i32 8)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double -1.0, i32 8)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pnormal_test_nnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_pnormal_test_nnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 1.000000e+00, i32 8)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 1.0, i32 8)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nsubnormal_test_nsubnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_nsubnormal_test_nsubnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x800FFFFFFFFFFFFF, i32 16)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x800fffffffffffff, i32 16)
   ret i1 %val
 }
 
 define i1 @test_constant_class_psubnormal_test_nsubnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_psubnormal_test_nsubnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFFFFFFFFFFFF, i32 16)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x000fffffffffffff, i32 16)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nzero_test_nzero_f64() {
 ; CHECK-LABEL: @test_constant_class_nzero_test_nzero_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -0.000000e+00, i32 32)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double -0.0, i32 32)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pzero_test_nzero_f64() {
 ; CHECK-LABEL: @test_constant_class_pzero_test_nzero_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0.000000e+00, i32 32)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0.0, i32 32)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pzero_test_pzero_f64() {
 ; CHECK-LABEL: @test_constant_class_pzero_test_pzero_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0.000000e+00, i32 64)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0.0, i32 64)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nzero_test_pzero_f64() {
 ; CHECK-LABEL: @test_constant_class_nzero_test_pzero_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -0.000000e+00, i32 64)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double -0.0, i32 64)
   ret i1 %val
 }
 
 define i1 @test_constant_class_psubnormal_test_psubnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_psubnormal_test_psubnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFFFFFFFFFFFF, i32 128)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x000fffffffffffff, i32 128)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nsubnormal_test_psubnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_nsubnormal_test_psubnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x800FFFFFFFFFFFFF, i32 128)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x800fffffffffffff, i32 128)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pnormal_test_pnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_pnormal_test_pnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 1.000000e+00, i32 256)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 1.0, i32 256)
   ret i1 %val
 }
 
 define i1 @test_constant_class_nnormal_test_pnormal_f64() {
 ; CHECK-LABEL: @test_constant_class_nnormal_test_pnormal_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -1.000000e+00, i32 256)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double -1.0, i32 256)
   ret i1 %val
 }
 
 define i1 @test_constant_class_pinf_test_pinf_f64() {
 ; CHECK-LABEL: @test_constant_class_pinf_test_pinf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 512)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 true
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 512)
   ret i1 %val
 }
 
 define i1 @test_constant_class_ninf_test_pinf_f64() {
 ; CHECK-LABEL: @test_constant_class_ninf_test_pinf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 512)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 512)
   ret i1 %val
 }
 
 define i1 @test_constant_class_qnan_test_pinf_f64() {
 ; CHECK-LABEL: @test_constant_class_qnan_test_pinf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 512)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 512)
   ret i1 %val
 }
 
 define i1 @test_constant_class_snan_test_pinf_f64() {
 ; CHECK-LABEL: @test_constant_class_snan_test_pinf_f64(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 512)
-; CHECK-NEXT:    ret i1 [[VAL]]
+; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 512)
   ret i1 %val
 }
 
 define i1 @test_class_is_snan_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_snan_nnan_src(
 ; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00