[Arm][AArch64] Add support for v8.9-A/v9.4-A base extensions

[pratlucas]

Summary

This implements the base extensions that are part of the v8.9-A and
v9.4-A architecture versions, including:

• The Clear BHB Instruction (FEAT_CLRBHB)
• The Speculation Restriction Instruction (FEAT_SPECRES2)
• The SLC target for the PRFM instruction
• New system registers:
  • ID_AA64PFR2_EL1
  • ID_AA64MMFR3_EL1
  • HFGITR2_EL2
  • SCTLR2_EL3

More information on the new extensions can be found on:

• https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
• https://developer.arm.com/downloads/-/exploration-tools

Contributors: Sam Elliott, Tomas Matheson and Son Tuan Vu.

llvm/include/llvm/Support/AArch64TargetParser.h

enum ArchExtKind : uint64_t {
   AEK_SME2p1 =      1ULL << 45, // FEAT_SME2p1
   AEK_B16B16 =      1ULL << 46, // FEAT_B16B16
   AEK_SMEF16F16 =   1ULL << 47, // FEAT_SMEF16F16
   AEK_CSSC =        1ULL << 48, // FEAT_CSSC
   AEK_RCPC3 =       1ULL << 49, // FEAT_LRCPC3
   AEK_THE =         1ULL << 50, // FEAT_THE
   AEK_D128 =        1ULL << 51, // FEAT_D128
   AEK_LSE128 =      1ULL << 52, // FEAT_LSE128
+  AEK_SPECRES2 =    1ULL << 53, // FEAT_SPECRES2
 };
 // clang-format on
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 

llvm/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("sme-f64f64",   AArch64::AEK_SMEF64F64,   "+sme-f64f64",   "-sme-f64f64")
 AARCH64_ARCH_EXT_NAME("sme-i16i64",   AArch64::AEK_SMEI16I64,   "+sme-i16i64",   "-sme-i16i64")
 AARCH64_ARCH_EXT_NAME("sme-f16f16",   AArch64::AEK_SMEF16F16,   "+sme-f16f16",   "-sme-f16f16")
 AARCH64_ARCH_EXT_NAME("sme2",         AArch64::AEK_SME2,        "+sme2",         "-sme2")
 AARCH64_ARCH_EXT_NAME("sme2p1",       AArch64::AEK_SME2p1,      "+sme2p1",       "-sme2p1")
 AARCH64_ARCH_EXT_NAME("hbc",          AArch64::AEK_HBC,         "+hbc",          "-hbc")
 AARCH64_ARCH_EXT_NAME("mops",         AArch64::AEK_MOPS,        "+mops",         "-mops")
 AARCH64_ARCH_EXT_NAME("pmuv3",        AArch64::AEK_PERFMON,     "+perfmon",      "-perfmon")
+AARCH64_ARCH_EXT_NAME("predres2",     AArch64::AEK_SPECRES2,    "+specres2",     "-specres2")
 AARCH64_ARCH_EXT_NAME("cssc",         AArch64::AEK_CSSC,        "+cssc",         "-cssc")
 AARCH64_ARCH_EXT_NAME("rcpc3",        AArch64::AEK_RCPC3,       "+rcpc3",        "-rcpc3")
 AARCH64_ARCH_EXT_NAME("the",          AArch64::AEK_THE,         "+the",          "-the")
 AARCH64_ARCH_EXT_NAME("d128",         AArch64::AEK_D128,        "+d128",         "-d128")
 AARCH64_ARCH_EXT_NAME("lse128",       AArch64::AEK_LSE128,      "+lse128",       "-lse128")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME

llvm/lib/Target/AArch64/AArch64.td

 def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
   "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
 
 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
                                                  "NoBTIAtReturnTwice", "true",
                                                  "Don't place a BTI instruction "
                                                  "after a return-twice">;
 
+def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
+    "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">;
+
+def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
+    "true", "Enable SLC target for PRFM instruction">;
+
+def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2",
+    "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
+    [FeaturePredRes]>;
+
 def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
     "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
 
 def FeatureITE : SubtargetFeature<"ite", "HasITE",
     "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
     FeatureTRBE]>;
 
 def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3",
def HasV8_7aOps : SubtargetFeature<
   [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
   [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
 
 def HasV8_9aOps : SubtargetFeature<
   "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
-  [HasV8_8aOps, FeatureCSSC]>;
+  [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
+   FeatureCSSC]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
   [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
 
 def HasV9_1aOps : SubtargetFeature<
   "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
   [HasV8_6aOps, HasV9_0aOps]>;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def HasBRBE          : Predicate<"Subtarget->hasBRBE()">,
                        AssemblerPredicateWithAll<(all_of FeatureBRBE), "brbe">;
 def HasSPE_EEF       : Predicate<"Subtarget->hasSPE_EEF()">,
                        AssemblerPredicateWithAll<(all_of FeatureSPE_EEF), "spe-eef">;
 def HasHBC           : Predicate<"Subtarget->hasHBC()">,
                        AssemblerPredicateWithAll<(all_of FeatureHBC), "hbc">;
 def HasMOPS          : Predicate<"Subtarget->hasMOPS()">,
                        AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;
+def HasCLRBHB        : Predicate<"Subtarget->hasCLRBHB()">,
+                       AssemblerPredicateWithAll<(all_of FeatureCLRBHB), "clrbhb">;
+def HasSPECRES2      : Predicate<"Subtarget->hasSPECRES2()">,
+                       AssemblerPredicateWithAll<(all_of FeatureSPECRES2), "specres2">;
 def HasITE           : Predicate<"Subtarget->hasITE()">,
                        AssemblerPredicateWithAll<(all_of FeatureITE), "ite">;
 def HasTHE           : Predicate<"Subtarget->hasTHE()">,
                        AssemblerPredicateWithAll<(all_of FeatureTHE), "the">;
 def HasRCPC3         : Predicate<"Subtarget->hasRCPC3()">,
                        AssemblerPredicateWithAll<(all_of FeatureRCPC3), "rcpc3">;
 def HasLSE128        : Predicate<"Subtarget->hasLSE128()">,
                        AssemblerPredicateWithAll<(all_of FeatureLSE128), "lse128">;

 
 def AArch64AssertZExtBool : SDNode<"AArch64ISD::ASSERT_ZEXT_BOOL", SDT_assert>;
 def : Pat<(AArch64AssertZExtBool GPR32:$op),
           (i32 GPR32:$op)>;
 
 //===----------------------------===//
 // 2022 Architecture Extensions:
 //===----------------------------===//
+def : InstAlias<"clrbhb",  (HINT 22), 0>;
+let Predicates = [HasCLRBHB] in {
+  def : InstAlias<"clrbhb",  (HINT 22), 1>;
+}
+
 defm RCW     : ReadCheckWriteCompareAndSwap;
 
 defm RCWCLR  : ReadCheckWriteOperation<0b001, "clr">;
 defm RCWSET  : ReadCheckWriteOperation<0b011, "set">;
 defm RCWSWP  : ReadCheckWriteOperation<0b010, "swp">;
 
 //===----------------------------------------------------------------------===//
 // General Data-Processing Instructions (FEAT_V94_DP)

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 }
 
 def : TSB<"csync", 0>;
 
 //===----------------------------------------------------------------------===//
 // PRFM (prefetch) instruction options.
 //===----------------------------------------------------------------------===//
 
-class PRFM<string name, bits<5> encoding> : SearchableTable {
+class PRFM<string type,   bits<2> type_encoding,
+           string target, bits<2> target_encoding,
+           string policy, bits<1> policy_encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
-  string Name = name;
+  string Name = type # target # policy;
   bits<5> Encoding;
-  let Encoding = encoding;
+  let Encoding{4-3} = type_encoding;
+  let Encoding{2-1} = target_encoding;
+  let Encoding{0} = policy_encoding;
+
+  code Requires = [{ {} }];
 }
 
-def : PRFM<"pldl1keep", 0x00>;
-def : PRFM<"pldl1strm", 0x01>;
-def : PRFM<"pldl2keep", 0x02>;
-def : PRFM<"pldl2strm", 0x03>;
-def : PRFM<"pldl3keep", 0x04>;
-def : PRFM<"pldl3strm", 0x05>;
-def : PRFM<"plil1keep", 0x08>;
-def : PRFM<"plil1strm", 0x09>;
-def : PRFM<"plil2keep", 0x0a>;
-def : PRFM<"plil2strm", 0x0b>;
-def : PRFM<"plil3keep", 0x0c>;
-def : PRFM<"plil3strm", 0x0d>;
-def : PRFM<"pstl1keep", 0x10>;
-def : PRFM<"pstl1strm", 0x11>;
-def : PRFM<"pstl2keep", 0x12>;
-def : PRFM<"pstl2strm", 0x13>;
-def : PRFM<"pstl3keep", 0x14>;
-def : PRFM<"pstl3strm", 0x15>;
+def : PRFM<"pld", 0b00, "l1",  0b00, "keep", 0b0>;
+def : PRFM<"pld", 0b00, "l1",  0b00, "strm", 0b1>;
+def : PRFM<"pld", 0b00, "l2",  0b01, "keep", 0b0>;
+def : PRFM<"pld", 0b00, "l2",  0b01, "strm", 0b1>;
+def : PRFM<"pld", 0b00, "l3",  0b10, "keep", 0b0>;
+def : PRFM<"pld", 0b00, "l3",  0b10, "strm", 0b1>;
+let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
+def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>;
+def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>;
+}
+def : PRFM<"pli", 0b01, "l1",  0b00, "keep", 0b0>;
+def : PRFM<"pli", 0b01, "l1",  0b00, "strm", 0b1>;
+def : PRFM<"pli", 0b01, "l2",  0b01, "keep", 0b0>;
+def : PRFM<"pli", 0b01, "l2",  0b01, "strm", 0b1>;
+def : PRFM<"pli", 0b01, "l3",  0b10, "keep", 0b0>;
+def : PRFM<"pli", 0b01, "l3",  0b10, "strm", 0b1>;
+let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
+def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>;
+def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>;
+}
+def : PRFM<"pst", 0b10, "l1",  0b00, "keep", 0b0>;
+def : PRFM<"pst", 0b10, "l1",  0b00, "strm", 0b1>;
+def : PRFM<"pst", 0b10, "l2",  0b01, "keep", 0b0>;
+def : PRFM<"pst", 0b10, "l2",  0b01, "strm", 0b1>;
+def : PRFM<"pst", 0b10, "l3",  0b10, "keep", 0b0>;
+def : PRFM<"pst", 0b10, "l3",  0b10, "strm", 0b1>;
+let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
+def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>;
+def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>;
+}
 
 //===----------------------------------------------------------------------===//
 // SVE Prefetch instruction options.
 //===----------------------------------------------------------------------===//
 
 class SVEPRFM<string name, bits<4> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";

 // Armv9-A Realm Management Extention TLBI Instructions
 let Requires = ["AArch64::FeatureRME"] in {
 defm : TLBI<"RPAOS",        0b110, 0b1000, 0b0100, 0b011>;
 defm : TLBI<"RPALOS",       0b110, 0b1000, 0b0100, 0b111>;
 defm : TLBI<"PAALLOS",      0b110, 0b1000, 0b0001, 0b100, 0>;
 defm : TLBI<"PAALL",        0b110, 0b1000, 0b0111, 0b100, 0>;
 }
 
-// Armv8.5-A Prediction Restriction by Context instruction options:
-class PRCTX<string name, bits<4> crm> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
-  string Name = name;
-  bits<11> Encoding;
-  let Encoding{10-4} = 0b0110111;
-  let Encoding{3-0} = crm;
-  bit NeedsReg = 1;
-  code Requires = [{ {} }];
-}
-
-let Requires = [{ {AArch64::FeaturePredRes} }] in {
-def : PRCTX<"RCTX", 0b0011>;
-}
-
 //===----------------------------------------------------------------------===//
 // MRS/MSR (system register read/write) instruction options.
 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";

 def : ROSysReg<"ID_ISAR3_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b011>;
 def : ROSysReg<"ID_ISAR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b100>;
 def : ROSysReg<"ID_ISAR5_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b101>;
 def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111> {
   let Requires = [{ {AArch64::HasV8_2aOps} }];
 }
 def : ROSysReg<"ID_AA64PFR0_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b000>;
 def : ROSysReg<"ID_AA64PFR1_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b001>;
+def : ROSysReg<"ID_AA64PFR2_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b010>;
 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;
 def : ROSysReg<"ID_AA64DFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b001>;
 def : ROSysReg<"ID_AA64AFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b100>;
 def : ROSysReg<"ID_AA64AFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b101>;
 def : ROSysReg<"ID_AA64ISAR0_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b000>;
 def : ROSysReg<"ID_AA64ISAR1_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b001>;
 def : ROSysReg<"ID_AA64ISAR2_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b010>;
 def : ROSysReg<"ID_AA64MMFR0_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b000>;
 def : ROSysReg<"ID_AA64MMFR1_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b001>;
 def : ROSysReg<"ID_AA64MMFR2_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b010>;
-def : ROSysReg<"MVFR0_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b000>;
-def : ROSysReg<"MVFR1_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b001>;
-def : ROSysReg<"MVFR2_EL1",          0b11, 0b000, 0b0000, 0b0011, 0b010>;
-def : ROSysReg<"RVBAR_EL1",          0b11, 0b000, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL2",          0b11, 0b100, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL3",          0b11, 0b110, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"ISR_EL1",            0b11, 0b000, 0b1100, 0b0001, 0b000>;
-def : ROSysReg<"CNTPCT_EL0",         0b11, 0b011, 0b1110, 0b0000, 0b001>;
-def : ROSysReg<"CNTVCT_EL0",         0b11, 0b011, 0b1110, 0b0000, 0b010>;
-def : ROSysReg<"ID_MMFR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b110>;
-def : ROSysReg<"ID_MMFR5_EL1",       0b11, 0b000, 0b0000, 0b0011, 0b110>;
+def : ROSysReg<"ID_AA64MMFR3_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b011>;
+def : ROSysReg<"MVFR0_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b000>;
+def : ROSysReg<"MVFR1_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b001>;
+def : ROSysReg<"MVFR2_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b010>;
+def : ROSysReg<"RVBAR_EL1",           0b11, 0b000, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL2",           0b11, 0b100, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL3",           0b11, 0b110, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"ISR_EL1",             0b11, 0b000, 0b1100, 0b0001, 0b000>;
+def : ROSysReg<"CNTPCT_EL0",          0b11, 0b011, 0b1110, 0b0000, 0b001>;
+def : ROSysReg<"CNTVCT_EL0",          0b11, 0b011, 0b1110, 0b0000, 0b010>;
+def : ROSysReg<"ID_MMFR4_EL1",        0b11, 0b000, 0b0000, 0b0010, 0b110>;
+def : ROSysReg<"ID_MMFR5_EL1",        0b11, 0b000, 0b0000, 0b0011, 0b110>;
 
 // Trace registers
-//                                 Op0    Op1     CRn     CRm    Op2
+//                                   Op0    Op1     CRn     CRm    Op2
 def : ROSysReg<"TRCSTATR",           0b10, 0b001, 0b0000, 0b0011, 0b000>;
 def : ROSysReg<"TRCIDR8",            0b10, 0b001, 0b0000, 0b0000, 0b110>;
 def : ROSysReg<"TRCIDR9",            0b10, 0b001, 0b0000, 0b0001, 0b110>;
 def : ROSysReg<"TRCIDR10",           0b10, 0b001, 0b0000, 0b0010, 0b110>;
 def : ROSysReg<"TRCIDR11",           0b10, 0b001, 0b0000, 0b0011, 0b110>;
 def : ROSysReg<"TRCIDR12",           0b10, 0b001, 0b0000, 0b0100, 0b110>;
 def : ROSysReg<"TRCIDR13",           0b10, 0b001, 0b0000, 0b0101, 0b110>;
 def : ROSysReg<"TRCIDR0",            0b10, 0b001, 0b0000, 0b1000, 0b111>;

 def : RWSysReg<"HAFGRTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b110>;
 
 // v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2)
 //                                 Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"HDFGRTR2_EL2",     0b11, 0b100, 0b0011, 0b0001, 0b000>;
 def : RWSysReg<"HDFGWTR2_EL2",     0b11, 0b100, 0b0011, 0b0001, 0b001>;
 def : RWSysReg<"HFGRTR2_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b010>;
 def : RWSysReg<"HFGWTR2_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b011>;
+def : RWSysReg<"HFGITR2_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b111>;
 }
 
 // v8.6a Enhanced Counter Virtualization
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {
 def : RWSysReg<"CNTSCALE_EL2",     0b11, 0b100, 0b1110, 0b0000, 0b100>;
 def : RWSysReg<"CNTISCALE_EL2",    0b11, 0b100, 0b1110, 0b0000, 0b101>;
 def : RWSysReg<"CNTPOFF_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b110>;

 //                            Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"S2POR_EL1",   0b11, 0b000, 0b1010, 0b0010, 0b101>;
 
 // v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2)
 //                            Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"SCTLR2_EL1",  0b11, 0b000, 0b0001, 0b0000, 0b011>;
 def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>;
 def : RWSysReg<"SCTLR2_EL2",  0b11, 0b100, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL3",  0b11, 0b110, 0b0001, 0b0000, 0b011>;
 
 // v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2)
 //                            Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"TCR2_EL1",    0b11, 0b000, 0b0010, 0b0000, 0b011>;
 def : RWSysReg<"TCR2_EL12",   0b11, 0b101, 0b0010, 0b0000, 0b011>;
 def : RWSysReg<"TCR2_EL2",    0b11, 0b100, 0b0010, 0b0000, 0b011>;
 
 // v8.9a/9.4a Translation Hardening Extension (FEAT_THE)

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64InstrInfo.h"
const FeatureBitset Features;
     {"sha2", {AArch64::FeatureSHA2}},
     {"aes", {AArch64::FeatureAES}},
     {"crypto", {AArch64::FeatureCrypto}},
     {"fp", {AArch64::FeatureFPARMv8}},
     {"simd", {AArch64::FeatureNEON}},
     {"ras", {AArch64::FeatureRAS}},
     {"lse", {AArch64::FeatureLSE}},
     {"predres", {AArch64::FeaturePredRes}},
+    {"predres2", {AArch64::FeatureSPECRES2}},
     {"ccdp", {AArch64::FeatureCacheDeepPersist}},
     {"mte", {AArch64::FeatureMTE}},
     {"memtag", {AArch64::FeatureMTE}},
     {"tlb-rmi", {AArch64::FeatureTLB_RMI}},
     {"pan", {AArch64::FeaturePAN}},
     {"pan-rwv", {AArch64::FeaturePAN_RWV}},
     {"ccpp", {AArch64::FeatureCCPP}},
     {"rcpc", {AArch64::FeatureRCPC}},
if (Mnemonic == "ic") {
     if (!TLBI)
       return TokError("invalid operand for TLBI instruction");
     else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
       std::string Str("TLBI " + std::string(TLBI->Name) + " requires: ");
       setRequiredFeatureString(TLBI->getRequiredFeatures(), Str);
       return TokError(Str);
     }
     createSysAlias(TLBI->Encoding, Operands, S);
-  } else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp") {
-    const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByName(Op);
-    if (!PRCTX)
+  } else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" || Mnemonic == "cosp") {
+
+    if (Op.lower() != "rctx")
       return TokError("invalid operand for prediction restriction instruction");
-    else if (!PRCTX->haveFeatures(getSTI().getFeatureBits())) {
-      std::string Str(
-          Mnemonic.upper() + std::string(PRCTX->Name) + " requires: ");
-      setRequiredFeatureString(PRCTX->getRequiredFeatures(), Str);
-      return TokError(Str);
-    }
-    uint16_t PRCTX_Op2 =
-      Mnemonic == "cfp" ? 4 :
-      Mnemonic == "dvp" ? 5 :
-      Mnemonic == "cpp" ? 7 :
-      0;
-    assert(PRCTX_Op2 && "Invalid mnemonic for prediction restriction instruction");
-    createSysAlias(PRCTX->Encoding << 3 | PRCTX_Op2 , Operands, S);
+
+    bool hasAll = getSTI().hasFeature(AArch64::FeatureAll);
+    bool hasPredres = hasAll || getSTI().hasFeature(AArch64::FeaturePredRes);
+    bool hasSpecres2 = hasAll || getSTI().hasFeature(AArch64::FeatureSPECRES2);
+
+    if (Mnemonic == "cosp" && !hasSpecres2)
+      return TokError("COSP requires: predres2");
+    if (!hasPredres)
+      return TokError(Mnemonic.upper() + "RCTX requires: predres");
+
+    uint16_t PRCTX_Op2 = Mnemonic == "cfp"    ? 0b100
+                         : Mnemonic == "dvp"  ? 0b101
+                         : Mnemonic == "cosp" ? 0b110
+                         : Mnemonic == "cpp"  ? 0b111
+                                              : 0;
+    assert(PRCTX_Op2 &&
+           "Invalid mnemonic for prediction restriction instruction");
+    const auto SYS_3_7_3 = 0b01101110011; // op=3, CRn=7, CRm=3
+    const auto Encoding = SYS_3_7_3 << 3 | PRCTX_Op2;
+
+    createSysAlias(Encoding, Operands, S);
   }
 
   Lex(); // Eat operand.
 
   bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
   bool HasRegister = false;
 
   // Check for the optional register operand.
bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
 
   // Create the leading tokens for the mnemonic, split by '.' characters.
   size_t Start = 0, Next = Name.find('.');
   StringRef Head = Name.slice(Start, Next);
 
   // IC, DC, AT, TLBI and Prediction invalidation instructions are aliases for
   // the SYS instruction.
   if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi" ||
-      Head == "cfp" || Head == "dvp" || Head == "cpp")
+      Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp")
     return parseSysAlias(Head, NameLoc, Operands);
 
   // TLBIP instructions are aliases for the SYSP instruction.
   if (Head == "tlbip")
     return parseSyspAlias(Head, NameLoc, Operands);
 
   Operands.push_back(AArch64Operand::CreateToken(Head, NameLoc, getContext()));
   Mnemonic = Head;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints an AArch64 MCInst to a .s file.
case 1:
       switch (Op1Val) {
       default: return false;
       case 0: goto Search_IC;
       case 3: goto Search_PRCTX;
       }
     // Prediction Restriction aliases
     case 3: {
       Search_PRCTX:
-      const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByEncoding(Encoding >> 3);
-      if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits()))
+      if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
         return false;
 
-      NeedsReg = PRCTX->NeedsReg;
+      const auto Requires =
+          Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
+      if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
+        return false;
+
+      NeedsReg = true;
       switch (Op2Val) {
       default: return false;
       case 4: Ins = "cfp\t"; break;
       case 5: Ins = "dvp\t"; break;
+      case 6: Ins = "cosp\t"; break;
       case 7: Ins = "cpp\t"; break;
       }
-      Name = std::string(PRCTX->Name);
+      Name = "RCTX";
     }
     break;
     // IC aliases
     case 5: {
       Search_IC:
       const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
       if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
         return false;
void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   unsigned prfop = MI->getOperand(OpNum).getImm();
   if (IsSVEPrefetch) {
     if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
       O << PRFM->Name;
       return;
     }
-  } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
+  } else {
+    auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
+    if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
       O << PRFM->Name;
       return;
     }
+  }
 
   O << markup("<imm:") << '#' << formatImm(prfop) << markup(">");
 }
 
 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   unsigned psbhintop = MI->getOperand(OpNum).getImm();

llvm/lib/Target/ARM/ARM.td

def FeaturePACBTI         : SubtargetFeature<"pacbti", "HasPACBTI", "true",
                                              "Target Identification">;
 
 /// Don't place a BTI instruction after return-twice constructs (setjmp).
 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
                                                  "NoBTIAtReturnTwice", "true",
                                                  "Don't place a BTI instruction "
                                                  "after a return-twice">;
 
+// Armv8.9-A/Armv9.4-A 2022 Architecture Extensions
+def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", "true",
+                                     "Enable Clear BHB instruction">;
+
+
 def FeatureFixCortexA57AES1742098 : SubtargetFeature<"fix-cortex-a57-aes-1742098",
   "FixCortexA57AES1742098", "true",
   "Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
 
 def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
                                               "CreateAAPCSFrameChain", "true",
                                               "Create an AAPCS compliant frame chain">;
 
def HasV8_7aOps   : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
                                    [HasV8_6aOps]>;
 
 def HasV8_8aOps   : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true",
                                    "Support ARM v8.8a instructions",
                                    [HasV8_7aOps]>;
 
 def HasV8_9aOps   : SubtargetFeature<"v8.9a", "HasV8_9aOps", "true",
                                    "Support ARM v8.9a instructions",
-                                   [HasV8_8aOps]>;
+                                   [HasV8_8aOps, FeatureCLRBHB]>;
 
 def HasV9_0aOps   : SubtargetFeature<"v9a", "HasV9_0aOps", "true",
                                    "Support ARM v9a instructions",
                                    [HasV8_5aOps]>;
 
 def HasV9_1aOps   : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true",
                                    "Support ARM v9.1a instructions",
                                    [HasV8_6aOps, HasV9_0aOps]>;

llvm/lib/Target/ARM/ARMInstrInfo.td

 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
 def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
 def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>;
 
+// Clear BHB instruction
+def : InstAlias<"clrbhb$p", (HINT 22, pred:$p), 0>, Requires<[IsARM, HasV8]>;
+def : InstAlias<"clrbhb$p", (HINT 22, pred:$p), 1>, Requires<[IsARM, HasV8, HasCLRBHB]>;
+
 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
              "\t$Rd, $Rn, $Rm",
              [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
              Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rm;
   let Inst{3-0} = Rm;

llvm/lib/Target/ARM/ARMInstrThumb2.td

 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
 def : t2InstAlias<"csdb$p",   (t2HINT 20, pred:$p), 1>;
 
 def : t2InstAlias<"pacbti$p r12,lr,sp", (t2HINT 13, pred:$p), 1>;
 def : t2InstAlias<"bti$p", (t2HINT 15, pred:$p), 1>;
 def : t2InstAlias<"pac$p r12,lr,sp", (t2HINT 29, pred:$p), 1>;
 def : t2InstAlias<"aut$p r12,lr,sp", (t2HINT 45, pred:$p), 1>;
 
+// Clear BHB instruction
+def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 0>, Requires<[IsThumb2, HasV8]>;
+def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 1>, Requires<[IsThumb2, HasV8, HasCLRBHB]>;
+
 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
                 [(int_arm_dbg imm0_15:$opt)]> {
   bits<4> opt;
   let Inst{31-20} = 0b111100111010;
   let Inst{19-16} = 0b1111;
   let Inst{15-8} = 0b10000000;
   let Inst{7-4} = 0b1111;
   let Inst{3-0} = opt;

llvm/lib/Target/ARM/ARMPredicates.td

let RecomputePerFunction = 1 in {
   def IsBE             : Predicate<"MF->getDataLayout().isBigEndian()">;
 }
 
 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
 
 // Armv8.5-A extensions
 def HasSB            : Predicate<"Subtarget->hasSB()">,
                        AssemblerPredicate<(all_of FeatureSB), "sb">;
+
+// Armv8.9-A/9.4-A 2022 Architecture extensions
+def HasCLRBHB        : Predicate<"Subtarget->hasCLRBHB()">,
+                       AssemblerPredicate<(all_of FeatureCLRBHB), "clrbhb">;

llvm/test/MC/AArch64/arm64-system-encoding.s

;-----------------------------------------------------------------------------
   msr POR_EL1, x3
   msr POR_EL12, x3
   msr POR_EL2, x3
   msr POR_EL3, x3
   msr S2POR_EL1, x3
   msr SCTLR2_EL1, x3
   msr SCTLR2_EL12, x3
   msr SCTLR2_EL2, x3
+  msr SCTLR2_EL3, x3
   msr TCR2_EL1, x3
   msr TCR2_EL12, x3
   msr TCR2_EL2, x3
   msr S3_2_C11_C6_4, x1
   msr  S0_0_C0_C0_0, x0
   msr  S1_2_C3_C4_5, x2
 ; CHECK: msr ACTLR_EL1, x3              ; encoding: [0x23,0x10,0x18,0xd5]
 ; CHECK: msr ACTLR_EL2, x3              ; encoding: [0x23,0x10,0x1c,0xd5]

 ; CHECK: msr POR_EL1, x3                ; encoding: [0x83,0xa2,0x18,0xd5]
 ; CHECK: msr POR_EL12, x3               ; encoding: [0x83,0xa2,0x1d,0xd5]
 ; CHECK: msr POR_EL2, x3                ; encoding: [0x83,0xa2,0x1c,0xd5]
 ; CHECK: msr POR_EL3, x3                ; encoding: [0x83,0xa2,0x1e,0xd5]
 ; CHECK: msr S2POR_EL1, x3              ; encoding: [0xa3,0xa2,0x18,0xd5]
 ; CHECK: msr SCTLR2_EL1, x3             ; encoding: [0x63,0x10,0x18,0xd5]
 ; CHECK: msr SCTLR2_EL12, x3            ; encoding: [0x63,0x10,0x1d,0xd5]
 ; CHECK: msr SCTLR2_EL2, x3             ; encoding: [0x63,0x10,0x1c,0xd5]
+; CHECK: msr SCTLR2_EL3, x3             ; encoding: [0x63,0x10,0x1e,0xd5]
 ; CHECK: msr TCR2_EL1, x3               ; encoding: [0x63,0x20,0x18,0xd5]
 ; CHECK: msr TCR2_EL12, x3              ; encoding: [0x63,0x20,0x1d,0xd5]
 ; CHECK: msr TCR2_EL2, x3               ; encoding: [0x63,0x20,0x1c,0xd5]
 ; CHECK: msr  S3_2_C11_C6_4, x1         ; encoding: [0x81,0xb6,0x1a,0xd5]
 ; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]
 ; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]
 
 // Readonly system registers: writing to them gives an error
; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
   mrs x3, HSTR_EL2
   mrs x3, ID_AA64DFR0_EL1
   mrs x3, ID_AA64DFR1_EL1
   mrs x3, ID_AA64ISAR0_EL1
   mrs x3, ID_AA64ISAR1_EL1
   mrs x3, ID_AA64ISAR2_EL1
   mrs x3, ID_AA64MMFR0_EL1
   mrs x3, ID_AA64MMFR1_EL1
+  mrs x3, ID_AA64MMFR2_EL1
+  mrs x3, ID_AA64MMFR3_EL1
   mrs x3, ID_AA64PFR0_EL1
   mrs x3, ID_AA64PFR1_EL1
+  mrs x3, ID_AA64PFR2_EL1
   mrs x3, IFSR32_EL2
   mrs x3, ISR_EL1
   mrs x3, MAIR_EL1
   mrs x3, MAIR_EL2
   mrs x3, MAIR_EL3
   mrs x3, MDCR_EL2
   mrs x3, MDCR_EL3
   mrs x3, MIDR_EL1
; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
   mrs x3, POR_EL1
   mrs x3, POR_EL12
   mrs x3, POR_EL2
   mrs x3, POR_EL3
   mrs x3, S2POR_EL1
   mrs x3, SCTLR2_EL1
   mrs x3, SCTLR2_EL12
   mrs x3, SCTLR2_EL2
+  mrs x3, SCTLR2_EL3
   mrs x3, TCR2_EL1
   mrs x3, TCR2_EL12
   mrs x3, TCR2_EL2
   mrs x1, S3_2_C15_C6_4
   mrs x3, s3_3_c11_c1_4
   mrs x3, S3_3_c11_c1_4
 
 ; CHECK: mrs x3, ACTLR_EL1              ; encoding: [0x23,0x10,0x38,0xd5]

 ; CHECK: mrs x3, HSTR_EL2               ; encoding: [0x63,0x11,0x3c,0xd5]
 ; CHECK: mrs x3, ID_AA64DFR0_EL1        ; encoding: [0x03,0x05,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64DFR1_EL1        ; encoding: [0x23,0x05,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR0_EL1       ; encoding: [0x03,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR1_EL1       ; encoding: [0x23,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR2_EL1       ; encoding: [0x43,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR0_EL1       ; encoding: [0x03,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR1_EL1       ; encoding: [0x23,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR2_EL1       ; encoding: [0x43,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR3_EL1       ; encoding: [0x63,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR0_EL1        ; encoding: [0x03,0x04,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR1_EL1        ; encoding: [0x23,0x04,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64PFR2_EL1        ; encoding: [0x43,0x04,0x38,0xd5]
 ; CHECK: mrs x3, IFSR32_EL2             ; encoding: [0x23,0x50,0x3c,0xd5]
 ; CHECK: mrs x3, ISR_EL1                ; encoding: [0x03,0xc1,0x38,0xd5]
 ; CHECK: mrs x3, MAIR_EL1               ; encoding: [0x03,0xa2,0x38,0xd5]
 ; CHECK: mrs x3, MAIR_EL2               ; encoding: [0x03,0xa2,0x3c,0xd5]
 ; CHECK: mrs x3, MAIR_EL3               ; encoding: [0x03,0xa2,0x3e,0xd5]
 ; CHECK: mrs x3, MDCR_EL2               ; encoding: [0x23,0x11,0x3c,0xd5]
 ; CHECK: mrs x3, MDCR_EL3               ; encoding: [0x23,0x13,0x3e,0xd5]
 ; CHECK: mrs x3, MIDR_EL1               ; encoding: [0x03,0x00,0x38,0xd5]

 ; CHECK: mrs x3, POR_EL1              ; encoding: [0x83,0xa2,0x38,0xd5]
 ; CHECK: mrs x3, POR_EL12             ; encoding: [0x83,0xa2,0x3d,0xd5]
 ; CHECK: mrs x3, POR_EL2              ; encoding: [0x83,0xa2,0x3c,0xd5]
 ; CHECK: mrs x3, POR_EL3              ; encoding: [0x83,0xa2,0x3e,0xd5]
 ; CHECK: mrs x3, S2POR_EL1            ; encoding: [0xa3,0xa2,0x38,0xd5]
 ; CHECK: mrs x3, SCTLR2_EL1           ; encoding: [0x63,0x10,0x38,0xd5]
 ; CHECK: mrs x3, SCTLR2_EL12          ; encoding: [0x63,0x10,0x3d,0xd5]
 ; CHECK: mrs x3, SCTLR2_EL2           ; encoding: [0x63,0x10,0x3c,0xd5]
+; CHECK: mrs x3, SCTLR2_EL3           ; encoding: [0x63,0x10,0x3e,0xd5]
 ; CHECK: mrs x3, TCR2_EL1             ; encoding: [0x63,0x20,0x38,0xd5]
 ; CHECK: mrs x3, TCR2_EL12            ; encoding: [0x63,0x20,0x3d,0xd5]
 ; CHECK: mrs x3, TCR2_EL2             ; encoding: [0x63,0x20,0x3c,0xd5]
 ; CHECK: mrs    x1, S3_2_C15_C6_4       ; encoding: [0x81,0xf6,0x3a,0xd5]
 ; CHECK: mrs  x3, S3_3_C11_C1_4       ; encoding: [0x83,0xb1,0x3b,0xd5]
 ; CHECK: mrs  x3, S3_3_C11_C1_4       ; encoding: [0x83,0xb1,0x3b,0xd5]
 
   msr RMR_EL3, x0

llvm/test/MC/AArch64/armv8.6a-fgt.s

 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 
 
 mrs x3, HDFGRTR2_EL2
 mrs x3, HDFGWTR2_EL2
 mrs x3, HFGRTR2_EL2
 mrs x3, HFGWTR2_EL2
+mrs x3, HFGITR2_EL2
 // CHECK: mrs     x3, HDFGRTR2_EL2                // encoding: [0x03,0x31,0x3c,0xd5]
 // CHECK: mrs     x3, HDFGWTR2_EL2                // encoding: [0x23,0x31,0x3c,0xd5]
 // CHECK: mrs     x3, HFGRTR2_EL2                 // encoding: [0x43,0x31,0x3c,0xd5]
 // CHECK: mrs     x3, HFGWTR2_EL2                 // encoding: [0x63,0x31,0x3c,0xd5]
+// CHECK: mrs     x3, HFGITR2_EL2                 // encoding: [0xe3,0x31,0x3c,0xd5]
+// NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 
 
 msr HDFGRTR2_EL2, x3
 msr HDFGWTR2_EL2, x3
 msr HFGRTR2_EL2, x3
 msr HFGWTR2_EL2, x3
+msr HFGITR2_EL2, x3
 // CHECK: msr     HDFGRTR2_EL2, x3                // encoding: [0x03,0x31,0x1c,0xd5]
 // CHECK: msr     HDFGWTR2_EL2, x3                // encoding: [0x23,0x31,0x1c,0xd5]
 // CHECK: msr     HFGRTR2_EL2, x3                 // encoding: [0x43,0x31,0x1c,0xd5]
 // CHECK: msr     HFGWTR2_EL2, x3                 // encoding: [0x63,0x31,0x1c,0xd5]
+// CHECK: msr     HFGITR2_EL2, x3                 // encoding: [0xe3,0x31,0x1c,0xd5]
+// NOFGT: error: expected writable system register
 // NOFGT: error: expected writable system register
 // NOFGT: error: expected writable system register
 // NOFGT: error: expected writable system register
 // NOFGT: error: expected writable system register

llvm/test/MC/AArch64/armv8.9a-clrbhb.s

+// CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+// Assembly is always permitted for instructions in the hint space.
+
+// Optional, off by default
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8a < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.8a < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9a < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.3a < %s | FileCheck %s --check-prefix=HINT_22
+
+// Optional, off by default, doubly disabled
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.3a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+
+// Optional, off by default, manually enabled
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+
+// Mandatory, enabled by default
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.9a < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.4a < %s | FileCheck %s --check-prefix=CLRBHB
+
+// Mandatory, on by default, doubly enabled
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.4a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB
+
+// Mandatory, can't prevent disabling in LLVM
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v8.9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+// RUN: llvm-mc -show-encoding -triple aarch64-none-none-eabi -mattr=+v9.4a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22
+
+        clrbhb
+        hint #22
+
+// CLRBHB: clrbhb    // encoding: [0xdf,0x22,0x03,0xd5]
+// CLRBHB: clrbhb    // encoding: [0xdf,0x22,0x03,0xd5]
+// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5]
+// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5]

llvm/test/MC/AArch64/armv8.9a-prfm-slc.s

+
+// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s --check-prefix=NO-SLC
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.9a < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v9.4a < %s | FileCheck %s
+
+prfm pldslckeep, [x3]
+// CHECK: prfm pldslckeep, [x3]  // encoding: [0x66,0x00,0x80,0xf9]
+// NO-SLC: prfm #6, [x3]
+prfm pldslcstrm, [x3]
+// CHECK: prfm pldslcstrm, [x3]  // encoding: [0x67,0x00,0x80,0xf9]
+// NO-SLC: prfm #7, [x3]
+prfm plislckeep, [x3]
+// CHECK: prfm plislckeep, [x3]  // encoding: [0x6e,0x00,0x80,0xf9]
+// NO-SLC: prfm #14, [x3]
+prfm plislcstrm, [x3]
+// CHECK: prfm plislcstrm, [x3]  // encoding: [0x6f,0x00,0x80,0xf9]
+// NO-SLC: prfm #15, [x3]
+prfm pstslckeep, [x3]
+// CHECK: prfm pstslckeep, [x3]  // encoding: [0x76,0x00,0x80,0xf9]
+// NO-SLC: prfm #22, [x3]
+prfm pstslcstrm, [x3]
+// CHECK: prfm pstslcstrm, [x3]  // encoding: [0x77,0x00,0x80,0xf9]
+// NO-SLC: prfm #23, [x3]
+
+self:
+prfm pldslckeep, self
+// CHECK: prfm pldslckeep, self // encoding: [0bAAA00110,A,A,0xd8]
+// NO-SLC: prfm #6, self
+
+prfm pldslckeep, [x3, x5]
+// CHECK: prfm pldslckeep, [x3, x5] // encoding: [0x66,0x68,0xa5,0xf8]
+// NO-SLC: prfm #6, [x3, x5]

llvm/test/MC/AArch64/armv8.9a-specres2-error.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specres2 < %s 2>&1| FileCheck %s
+
+cosp rctx
+
+// CHECK: specified cosp op requires a register
+
+cosp x0, x1
+
+// CHECK:      invalid operand for prediction restriction instruction
+// CHECK-NEXT: cosp

llvm/test/MC/AArch64/armv8.9a-specres2.s

+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specres2 < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a    < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a    < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specres2 < %s 2>&1 | FileCheck %s --check-prefix=NOSPECRES2
+
+cosp rctx, x0
+sys #3, c7, c3, #6, x0
+
+// CHECK: cosp rctx, x0          // encoding: [0xc0,0x73,0x0b,0xd5]
+// CHECK: cosp rctx, x0          // encoding: [0xc0,0x73,0x0b,0xd5]
+
+// NOSPECRES2: COSP requires: predres2
+// NOSPECRES2-NEXT: cosp

llvm/test/MC/AArch64/basic-a64-diagnostics.s

// write-only registers actually are.
         msr ID_ISAR3_EL1, x12
         msr ID_ISAR4_EL1, x12
         msr ID_ISAR5_EL1, x12
         msr MVFR0_EL1, x12
         msr MVFR1_EL1, x12
         msr MVFR2_EL1, x12
         msr ID_AA64PFR0_EL1, x12
         msr ID_AA64PFR1_EL1, x12
+        msr ID_AA64PFR2_EL1, x12
         msr ID_AA64DFR0_EL1, x12
         msr ID_AA64DFR1_EL1, x12
         msr ID_AA64AFR0_EL1, x12
         msr ID_AA64AFR1_EL1, x12
         msr ID_AA64ISAR0_EL1, x12
         msr ID_AA64ISAR1_EL1, x12
         msr ID_AA64MMFR0_EL1, x12
         msr ID_AA64MMFR1_EL1, x12
+        msr ID_AA64MMFR2_EL1, x12
+        msr ID_AA64MMFR3_EL1, x12
         msr PMCEID0_EL0, x12
         msr PMCEID1_EL0, x12
         msr PMMIR_EL1, x12
         msr RVBAR_EL1, x12
         msr RVBAR_EL2, x12
         msr RVBAR_EL3, x12
         msr ISR_EL1, x12
         msr CNTPCT_EL0, x12

 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64PFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64PFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_AA64PFR2_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64DFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64DFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64AFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64AFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64ISAR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64ISAR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64MMFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64MMFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_AA64MMFR2_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_AA64MMFR3_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMCEID0_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMCEID1_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMMIR_EL1, x12
 // CHECK-ERROR-NEXT:             ^

llvm/test/MC/AArch64/basic-a64-instructions.s

msr PMEVTYPER30_EL0, x12
         msr POR_EL1, x12
         msr POR_EL12, x12
         msr POR_EL2, x12
         msr POR_EL3, x12
         msr S2POR_EL1, x12
         msr SCTLR2_EL1, x12
         msr SCTLR2_EL12, x12
         msr SCTLR2_EL2, x12
+        msr SCTLR2_EL3, x12
         msr TCR2_EL1, x12
         msr TCR2_EL12, x12
         msr TCR2_EL2, x12
 // CHECK: msr      {{teecr32_el1|TEECR32_EL1}}, x12           // encoding: [0x0c,0x00,0x12,0xd5]
 // CHECK: msr      {{osdtrrx_el1|OSDTRRX_EL1}}, x12           // encoding: [0x4c,0x00,0x10,0xd5]
 // CHECK: msr      {{mdccint_el1|MDCCINT_EL1}}, x12           // encoding: [0x0c,0x02,0x10,0xd5]
 // CHECK: msr      {{mdscr_el1|MDSCR_EL1}}, x12             // encoding: [0x4c,0x02,0x10,0xd5]
 // CHECK: msr      {{osdtrtx_el1|OSDTRTX_EL1}}, x12           // encoding: [0x4c,0x03,0x10,0xd5]

 // CHECK: msr      {{por_el1|POR_EL1}}, x12       // encoding: [0x8c,0xa2,0x18,0xd5]
 // CHECK: msr      {{por_el12|POR_EL12}}, x12       // encoding: [0x8c,0xa2,0x1d,0xd5]
 // CHECK: msr      {{por_el2|POR_EL2}}, x12       // encoding: [0x8c,0xa2,0x1c,0xd5]
 // CHECK: msr      {{por_el3|POR_EL3}}, x12       // encoding: [0x8c,0xa2,0x1e,0xd5]
 // CHECK: msr      {{s2por_el1|S2POR_EL1}}, x12       // encoding: [0xac,0xa2,0x18,0xd5]
 // CHECK: msr      {{sctlr2_el1|SCTLR2_EL1}}, x12       // encoding: [0x6c,0x10,0x18,0xd5]
 // CHECK: msr      {{sctlr2_el12|SCTLR2_EL12}}, x12       // encoding: [0x6c,0x10,0x1d,0xd5]
 // CHECK: msr      {{sctlr2_el2|SCTLR2_EL2}}, x12       // encoding: [0x6c,0x10,0x1c,0xd5]
+// CHECK: msr      {{sctlr2_el3|SCTLR2_EL3}}, x12       // encoding: [0x6c,0x10,0x1e,0xd5]
 // CHECK: msr      {{tcr2_el1|TCR2_EL1}}, x12       // encoding: [0x6c,0x20,0x18,0xd5]
 // CHECK: msr      {{tcr2_el12|TCR2_EL12}}, x12       // encoding: [0x6c,0x20,0x1d,0xd5]
 // CHECK: msr      {{tcr2_el2|TCR2_EL2}}, x12       // encoding: [0x6c,0x20,0x1c,0xd5]
 
   mrs x9, TEECR32_EL1
   mrs x9, OSDTRRX_EL1
   mrs x9, MDCCSR_EL0
   mrs x9, MDCCINT_EL1
// CHECK: msr      {{tcr2_el2|TCR2_EL2}}, x12       // encoding: [0x6c,0x20,0x1c,0xd5]
   mrs x9, ID_ISAR3_EL1
   mrs x9, ID_ISAR4_EL1
   mrs x9, ID_ISAR5_EL1
   mrs x9, MVFR0_EL1
   mrs x9, MVFR1_EL1
   mrs x9, MVFR2_EL1
   mrs x9, ID_AA64PFR0_EL1
   mrs x9, ID_AA64PFR1_EL1
+  mrs x9, ID_AA64PFR2_EL1
   mrs x9, ID_AA64DFR0_EL1
   mrs x9, ID_AA64DFR1_EL1
   mrs x9, ID_AA64AFR0_EL1
   mrs x9, ID_AA64AFR1_EL1
   mrs x9, ID_AA64ISAR0_EL1
   mrs x9, ID_AA64ISAR1_EL1
   mrs x9, ID_AA64MMFR0_EL1
   mrs x9, ID_AA64MMFR1_EL1
+  mrs x9, ID_AA64MMFR2_EL1
+  mrs x9, ID_AA64MMFR3_EL1
   mrs x9, SCTLR_EL1
   mrs x9, SCTLR_EL2
   mrs x9, SCTLR_EL3
   mrs x9, ACTLR_EL1
   mrs x9, ACTLR_EL2
   mrs x9, ACTLR_EL3
   mrs x9, CPACR_EL1
   mrs x9, HCR_EL2
mrs x9, PMEVTYPER30_EL0
         mrs x9, POR_EL1
         mrs x9, POR_EL12
         mrs x9, POR_EL2
         mrs x9, POR_EL3
         mrs x9, S2POR_EL1
         mrs x9, SCTLR2_EL1
         mrs x9, SCTLR2_EL12
         mrs x9, SCTLR2_EL2
+        mrs x9, SCTLR2_EL3
         mrs x9, TCR2_EL1
         mrs x9, TCR2_EL12
         mrs x9, TCR2_EL2
 // CHECK: mrs      x9, {{teecr32_el1|TEECR32_EL1}}            // encoding: [0x09,0x00,0x32,0xd5]
 // CHECK: mrs      x9, {{osdtrrx_el1|OSDTRRX_EL1}}            // encoding: [0x49,0x00,0x30,0xd5]
 // CHECK: mrs      x9, {{mdccsr_el0|MDCCSR_EL0}}             // encoding: [0x09,0x01,0x33,0xd5]
 // CHECK: mrs      x9, {{mdccint_el1|MDCCINT_EL1}}            // encoding: [0x09,0x02,0x30,0xd5]
 // CHECK: mrs      x9, {{mdscr_el1|MDSCR_EL1}}              // encoding: [0x49,0x02,0x30,0xd5]

 // CHECK: mrs      x9, {{id_isar3_el1|ID_ISAR3_EL1}}           // encoding: [0x69,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar4_el1|ID_ISAR4_EL1}}           // encoding: [0x89,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar5_el1|ID_ISAR5_EL1}}           // encoding: [0xa9,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{mvfr0_el1|MVFR0_EL1}}              // encoding: [0x09,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{mvfr1_el1|MVFR1_EL1}}              // encoding: [0x29,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{mvfr2_el1|MVFR2_EL1}}              // encoding: [0x49,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}        // encoding: [0x09,0x04,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}        // encoding: [0x29,0x04,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64pfr2_el1|ID_AA64PFR2_EL1}}        // encoding: [0x49,0x04,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}        // encoding: [0x09,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}        // encoding: [0x29,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}        // encoding: [0x89,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}        // encoding: [0xa9,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}       // encoding: [0x09,0x06,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}       // encoding: [0x29,0x06,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}       // encoding: [0x09,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}       // encoding: [0x29,0x07,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}       // encoding: [0x49,0x07,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}       // encoding: [0x69,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr_el1|SCTLR_EL1}}              // encoding: [0x09,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr_el2|SCTLR_EL2}}              // encoding: [0x09,0x10,0x3c,0xd5]
 // CHECK: mrs      x9, {{sctlr_el3|SCTLR_EL3}}              // encoding: [0x09,0x10,0x3e,0xd5]
 // CHECK: mrs      x9, {{actlr_el1|ACTLR_EL1}}              // encoding: [0x29,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{actlr_el2|ACTLR_EL2}}              // encoding: [0x29,0x10,0x3c,0xd5]
 // CHECK: mrs      x9, {{actlr_el3|ACTLR_EL3}}              // encoding: [0x29,0x10,0x3e,0xd5]
 // CHECK: mrs      x9, {{cpacr_el1|CPACR_EL1}}              // encoding: [0x49,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{hcr_el2|HCR_EL2}}                // encoding: [0x09,0x11,0x3c,0xd5]

 // CHECK: mrs      x9, {{por_el1|POR_EL1}}        // encoding: [0x89,0xa2,0x38,0xd5]
 // CHECK: mrs      x9, {{por_el12|POR_EL12}}        // encoding: [0x89,0xa2,0x3d,0xd5]
 // CHECK: mrs      x9, {{por_el2|POR_EL2}}        // encoding: [0x89,0xa2,0x3c,0xd5]
 // CHECK: mrs      x9, {{por_el3|POR_EL3}}        // encoding: [0x89,0xa2,0x3e,0xd5]
 // CHECK: mrs      x9, {{s2por_el1|S2POR_EL1}}        // encoding: [0xa9,0xa2,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr2_el1|SCTLR2_EL1}}        // encoding: [0x69,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr2_el12|SCTLR2_EL12}}        // encoding: [0x69,0x10,0x3d,0xd5]
 // CHECK: mrs      x9, {{sctlr2_el2|SCTLR2_EL2}}        // encoding: [0x69,0x10,0x3c,0xd5]
+// CHECK: mrs      x9, {{sctlr2_el3|SCTLR2_EL3}}        // encoding: [0x69,0x10,0x3e,0xd5]
 // CHECK: mrs      x9, {{tcr2_el1|TCR2_EL1}}        // encoding: [0x69,0x20,0x38,0xd5]
 // CHECK: mrs      x9, {{tcr2_el12|TCR2_EL12}}        // encoding: [0x69,0x20,0x3d,0xd5]
 // CHECK: mrs      x9, {{tcr2_el2|TCR2_EL2}}        // encoding: [0x69,0x20,0x3c,0xd5]
 
         mrs x12, s3_7_c15_c1_5
         mrs x13, s3_2_c11_c15_7
         mrs x14, s1_3_c9_c2_1
         msr s3_0_c15_c0_0, x12

llvm/test/MC/ARM/armv8.9a-clrbhb.s

+// CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+// Assembly is always permitted for instructions in the hint space.
+
+// Invalid before v8
+// RUN: not llvm-mc -show-encoding -triple armv7-none-none-eabi < %s 2>&1 | FileCheck %s --check-prefix=INVALID
+// RUN: not llvm-mc -show-encoding -triple armv7-none-none-eabi -mattr=-clrbhb < %s 2>&1 | FileCheck %s --check-prefix=INVALID
+// RUN: not llvm-mc -show-encoding -triple armv7-none-none-eabi -mattr=+clrbhb < %s 2>&1 | FileCheck %s --check-prefix=REQUIRESV8
+
+// Optional, off by default
+// RUN: llvm-mc -show-encoding -triple armv8-none-none-eabi < %s | FileCheck %s --check-prefix=A32_HINT
+// RUN: llvm-mc -show-encoding -triple armv8.8a-none-none-eabi < %s | FileCheck %s --check-prefix=A32_HINT
+// RUN: llvm-mc -show-encoding -triple thumbv8-none-none-eabi < %s | FileCheck %s --check-prefix=T32_HINT
+// RUN: llvm-mc -show-encoding -triple thumbv8.8a-none-none-eabi < %s | FileCheck %s --check-prefix=T32_HINT
+
+// Optional, off by default, doubly disabled
+// RUN: llvm-mc -show-encoding -triple armv8-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=A32_HINT
+// RUN: llvm-mc -show-encoding -triple armv8.8a-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=A32_HINT
+// RUN: llvm-mc -show-encoding -triple thumbv8-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=T32_HINT
+// RUN: llvm-mc -show-encoding -triple thumbv8.8a-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=T32_HINT
+
+// Optional, off by default, manually enabled
+// RUN: llvm-mc -show-encoding -triple armv8-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=A32_CLRBHB
+// RUN: llvm-mc -show-encoding -triple armv8.8a-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=A32_CLRBHB
+// RUN: llvm-mc -show-encoding -triple thumbv8-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=T32_CLRBHB
+// RUN: llvm-mc -show-encoding -triple thumbv8.8a-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=T32_CLRBHB
+
+// Mandatory, enabled by default
+// RUN: llvm-mc -show-encoding -triple armv8.9a-none-none-eabi < %s | FileCheck %s --check-prefix=A32_CLRBHB
+// RUN: llvm-mc -show-encoding -triple thumbv8.9a-none-none-eabi < %s | FileCheck %s --check-prefix=T32_CLRBHB
+
+// Mandatory, on by default, doubly enabled
+// RUN: llvm-mc -show-encoding -triple armv8.9a-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=A32_CLRBHB
+// RUN: llvm-mc -show-encoding -triple thumbv8.9a-none-none-eabi -mattr=+clrbhb < %s | FileCheck %s --check-prefix=T32_CLRBHB
+
+// Mandatory, can't prevent disabling in LLVM
+// RUN: llvm-mc -show-encoding -triple armv8.9a-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=A32_HINT
+// RUN: llvm-mc -show-encoding -triple thumbv8.9a-none-none-eabi -mattr=-clrbhb < %s | FileCheck %s --check-prefix=T32_HINT
+
+        clrbhb
+        hint #22
+
+// INVALID: <stdin>:[[@LINE-3]]:9: error: invalid instruction
+// INVALID-NOT: <stdin>:[[@LINE-3]]:9: error: invalid instruction
+// REQUIRESV8: <stdin>:[[@LINE-5]]:9: error: instruction requires: armv8
+// REQUIRESV8-NOT: <stdin>:[[@LINE-5]]:9: error: instruction requires: armv8
+// A32_CLRBHB: clrbhb   @ encoding: [0x16,0xf0,0x20,0xe3]
+// A32_CLRBHB: clrbhb   @ encoding: [0x16,0xf0,0x20,0xe3]
+// A32_HINT: hint #22   @ encoding: [0x16,0xf0,0x20,0xe3]
+// A32_HINT: hint #22   @ encoding: [0x16,0xf0,0x20,0xe3]
+// T32_CLRBHB: clrbhb   @ encoding: [0xaf,0xf3,0x16,0x80]
+// T32_CLRBHB: clrbhb   @ encoding: [0xaf,0xf3,0x16,0x80]
+// T32_HINT: hint.w #22 @ encoding: [0xaf,0xf3,0x16,0x80]
+// T32_HINT: hint.w #22 @ encoding: [0xaf,0xf3,0x16,0x80]

llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt

 # NOFGT: mrs x0, S3_4_C3_C1_4
 # NOFGT: mrs x0, S3_4_C3_C1_5
 # NOFGT: mrs x0, S3_4_C3_C1_6
 
 [0x03,0x31,0x3c,0xd5]
 [0x23,0x31,0x3c,0xd5]
 [0x43,0x31,0x3c,0xd5]
 [0x63,0x31,0x3c,0xd5]
+[0xe3,0x31,0x3c,0xd5]
 # CHECK: mrs x3, HDFGRTR2_EL2
 # CHECK: mrs x3, HDFGWTR2_EL2
 # CHECK: mrs x3, HFGRTR2_EL2
 # CHECK: mrs x3, HFGWTR2_EL2
+# CHECK: mrs x3, HFGITR2_EL2
 # NOFGT: mrs x3, S3_4_C3_C1_0
 # NOFGT: mrs x3, S3_4_C3_C1_1
 # NOFGT: mrs x3, S3_4_C3_C1_2
 # NOFGT: mrs x3, S3_4_C3_C1_3
+# NOFGT: mrs x3, S3_4_C3_C1_7
 
 
 [0x03,0x31,0x1c,0xd5]
 [0x23,0x31,0x1c,0xd5]
 [0x43,0x31,0x1c,0xd5]
 [0x63,0x31,0x1c,0xd5]
+[0xe3,0x31,0x1c,0xd5]
 # CHECK: msr HDFGRTR2_EL2, x3
 # CHECK: msr HDFGWTR2_EL2, x3
 # CHECK: msr HFGRTR2_EL2, x3
 # CHECK: msr HFGWTR2_EL2, x3
+# CHECK: msr HFGITR2_EL2, x3
 # NOFGT: msr S3_4_C3_C1_0, x3
 # NOFGT: msr S3_4_C3_C1_1, x3
 # NOFGT: msr S3_4_C3_C1_2, x3
 # NOFGT: msr S3_4_C3_C1_3, x3
+# NOFGT: msr S3_4_C3_C1_7, x3

llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt

+# CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+# Should disassemble to hint #22 if the feature is not present.
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a,-clrbhb %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a,-clrbhb %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+clrbhb %s | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a,+clrbhb %s | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a %s | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a,+clrbhb %s | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a %s | FileCheck %s --check-prefix=CLRBHB
+
+[0xdf,0x22,0x03,0xd5]
+# CLRBHB: clrbhb
+# HINT_22: hint #22

llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt

+// RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s --check-prefix=NO-SLC
+// RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v8.9a < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v9.4a < %s | FileCheck %s
+
+[0x66,0x00,0x80,0xf9]
+// CHECK: prfm pldslckeep, [x3]
+// NO-SLC: prfm #6, [x3]
+
+[0x67,0x00,0x80,0xf9]
+// CHECK: prfm pldslcstrm, [x3]
+// NO-SLC: prfm #7, [x3]
+
+[0x6e,0x00,0x80,0xf9]
+// CHECK: prfm plislckeep, [x3]
+// NO-SLC: prfm #14, [x3]
+
+[0x6f,0x00,0x80,0xf9]
+// CHECK: prfm plislcstrm, [x3]
+// NO-SLC: prfm #15, [x3]
+
+[0x76,0x00,0x80,0xf9]
+// CHECK: prfm pstslckeep, [x3]
+// NO-SLC: prfm #22, [x3]
+
+[0x06,0x00,0x00,0xd8]
+// CHECK: prfm pldslckeep, #0
+// NO-SLC: prfm #6, #0
+
+[0x66,0x68,0xa5,0xf8]
+// CHECK: prfm pldslckeep, [x3, x5]
+// NO-SLC: prfm #6, [x3, x5]

llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt

+# FEAT_SPECRES2 is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+# Should disassemble to hint #22 if the feature is not present.
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a -mattr=-specres2 %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a -mattr=-specres2 %s | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a %s | FileCheck %s --check-prefix=FEAT_SPECRES2
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2
+# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a %s | FileCheck %s --check-prefix=FEAT_SPECRES2
+
+[0xc0,0x73,0x0b,0xd5]
+# FEAT_SPECRES2: cosp rctx, x0
+# HINT_22: sys #3, c7, c3, #6, x0

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: mrs      x9, {{id_isar3_el1|ID_ISAR3_EL1}}
 # CHECK: mrs      x9, {{id_isar4_el1|ID_ISAR4_EL1}}
 # CHECK: mrs      x9, {{id_isar5_el1|ID_ISAR5_EL1}}
 # CHECK: mrs      x9, {{mvfr0_el1|MVFR0_EL1}}
 # CHECK: mrs      x9, {{mvfr1_el1|MVFR1_EL1}}
 # CHECK: mrs      x9, {{mvfr2_el1|MVFR2_EL1}}
 # CHECK: mrs      x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}
+# CHECK: mrs      x9, {{id_aa64pfr2_el1|ID_AA64PFR2_EL1}}
 # CHECK: mrs      x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar2_el1|ID_AA64ISAR2_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
+# CHECK: mrs      x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}
+# CHECK: mrs      x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}
 # CHECK: mrs      x9, {{sctlr_el1|SCTLR_EL1}}
 # CHECK: mrs      x9, {{sctlr_el2|SCTLR_EL2}}
 # CHECK: mrs      x9, {{sctlr_el3|SCTLR_EL3}}
 # CHECK: mrs      x9, {{actlr_el1|ACTLR_EL1}}
 # CHECK: mrs      x9, {{actlr_el2|ACTLR_EL2}}
 # CHECK: mrs      x9, {{actlr_el3|ACTLR_EL3}}
 # CHECK: mrs      x9, {{cpacr_el1|CPACR_EL1}}
 # CHECK: mrs      x9, {{hcr_el2|HCR_EL2}}

 # CHECK: mrs      x9, {{por_el1|POR_EL1}}
 # CHECK: mrs      x9, {{por_el12|POR_EL12}}
 # CHECK: mrs      x9, {{por_el2|POR_EL2}}
 # CHECK: mrs      x9, {{por_el3|POR_EL3}}
 # CHECK: mrs      x9, {{s2por_el1|S2POR_EL1}}
 # CHECK: mrs      x9, {{sctlr2_el1|SCTLR2_EL1}}
 # CHECK: mrs      x9, {{sctlr2_el12|SCTLR2_EL12}}
 # CHECK: mrs      x9, {{sctlr2_el2|SCTLR2_EL2}}
+# CHECK: mrs      x9, {{sctlr2_el3|SCTLR2_EL3}}
 # CHECK: mrs      x9, {{tcr2_el1|TCR2_EL1}}
 # CHECK: mrs      x9, {{tcr2_el12|TCR2_EL12}}
 # CHECK: mrs      x9, {{tcr2_el2|TCR2_EL2}}
 
 0xc 0x0 0x12 0xd5
 0x4c 0x0 0x10 0xd5
 0xc 0x2 0x10 0xd5
 0x4c 0x2 0x10 0xd5

 0x8c 0xa2 0x18 0xd5
 0x8c 0xa2 0x1d 0xd5
 0x8c 0xa2 0x1c 0xd5
 0x8c 0xa2 0x1e 0xd5
 0xac 0xa2 0x18 0xd5
 0x6c 0x10 0x18 0xd5
 0x6c 0x10 0x1d 0xd5
 0x6c 0x10 0x1c 0xd5
+0x6c 0x10 0x1e 0xd5
 0x6c 0x20 0x18 0xd5
 0x6c 0x20 0x1d 0xd5
 0x6c 0x20 0x1c 0xd5
 0x9 0x0 0x32 0xd5
 0x49 0x0 0x30 0xd5
 0x9 0x1 0x33 0xd5
 0x9 0x2 0x30 0xd5
 0x49 0x2 0x30 0xd5

 0x69 0x2 0x38 0xd5
 0x89 0x2 0x38 0xd5
 0xa9 0x2 0x38 0xd5
 0x9 0x3 0x38 0xd5
 0x29 0x3 0x38 0xd5
 0x49 0x3 0x38 0xd5
 0x9 0x4 0x38 0xd5
 0x29 0x4 0x38 0xd5
+0x49 0x4 0x38 0xd5
 0x9 0x5 0x38 0xd5
 0x29 0x5 0x38 0xd5
 0x89 0x5 0x38 0xd5
 0xa9 0x5 0x38 0xd5
 0x9 0x6 0x38 0xd5
 0x29 0x6 0x38 0xd5
 0x49 0x06 0x38 0xd5
 0x9 0x7 0x38 0xd5
 0x29 0x7 0x38 0xd5
+0x49 0x7 0x38 0xd5
+0x69 0x7 0x38 0xd5
 0x9 0x10 0x38 0xd5
 0x9 0x10 0x3c 0xd5
 0x9 0x10 0x3e 0xd5
 0x29 0x10 0x38 0xd5
 0x29 0x10 0x3c 0xd5
 0x29 0x10 0x3e 0xd5
 0x49 0x10 0x38 0xd5
 0x9 0x11 0x3c 0xd5

 0x89 0xa2 0x38 0xd5
 0x89 0xa2 0x3d 0xd5
 0x89 0xa2 0x3c 0xd5
 0x89 0xa2 0x3e 0xd5
 0xa9 0xa2 0x38 0xd5
 0x69 0x10 0x38 0xd5
 0x69 0x10 0x3d 0xd5
 0x69 0x10 0x3c 0xd5
+0x69 0x10 0x3e 0xd5
 0x69 0x20 0x38 0xd5
 0x69 0x20 0x3d 0xd5
 0x69 0x20 0x3c 0xd5
 
 # CHECK: mrs     x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
 # CHECK: mrs     x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
 # CHECK: mrs     xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}}
 # CHECK: msr     {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12

llvm/test/MC/Disassembler/AArch64/mattr-all.txt

 ## armv9a rme
 # CHECK: mrs x0, MFAR_EL3
 [0xa0,0x60,0x3e,0xd5]
 
 ## predres (to make sure sysreg aliases work)
 # CHECK: cfp rctx, x0
 [0x80,0x73,0x0b,0xd5]
 
+## predres2 (sysreg alias implementation is different from predres)
+# CHECK: cosp rctx, x0
+[0xc0,0x73,0x0b,0xd5]
+
 ## sme
 # CHECK: addha za0.s, p0/m, p0/m, z0.s
 [0x00,0x00,0x90,0xc0]
 
 ## smef64
 # CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
 [0x00,0x00,0xc0,0x80]
 
 ## smei64
 # CHECK: addha za0.d, p0/m, p0/m, z0.d
 [0x00,0x00,0xd0,0xc0]
 
 ## sme2
 # CHECK: add { z0.h, z1.h }, { z0.h, z1.h }, z0.h
 [0x00,0xa3,0x60,0xc1]
-

llvm/test/MC/Disassembler/ARM/armv8.9a-clrbhb-arm.txt

+# CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+# Should disassemble to hint #22 if the feature is not present.
+# RUN: llvm-mc %s -disassemble -triple=armv8 2>&1 | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc %s -disassemble -triple=armv8 -mattr=+clrbhb | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc %s -disassemble -triple=armv8.9a | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc %s -disassemble -triple=armv8.9a -mattr=-clrbhb | FileCheck %s --check-prefix=HINT_22
+
+[0x16,0xf0,0x20,0xe3]
+# CLRBHB: clrbhb
+# HINT_22: hint #22

llvm/test/MC/Disassembler/ARM/armv8.9a-clrbhb-thumb.txt

+# CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a.
+# Should disassemble to hint #22 if the feature is not present.
+# RUN: llvm-mc %s -disassemble -triple=thumbv8a | FileCheck %s --check-prefix=HINT_22
+# RUN: llvm-mc %s -disassemble -triple=thumbv8a -mattr=+clrbhb | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc %s -disassemble -triple=thumbv8.9a | FileCheck %s --check-prefix=CLRBHB
+# RUN: llvm-mc %s -disassemble -triple=thumbv8.9a -mattr=-clrbhb | FileCheck %s --check-prefix=HINT_22
+
+[0xaf,0xf3,0x16,0x80]
+# CLRBHB: clrbhb
+# HINT_22: hint.w #22

llvm/unittests/Support/TargetParserTest.cpp

std::vector<uint64_t> Extensions = {
       AArch64::AEK_BF16,    AArch64::AEK_I8MM,      AArch64::AEK_F32MM,
       AArch64::AEK_F64MM,   AArch64::AEK_TME,       AArch64::AEK_LS64,
       AArch64::AEK_BRBE,    AArch64::AEK_PAUTH,     AArch64::AEK_FLAGM,
       AArch64::AEK_SME,     AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
       AArch64::AEK_SME2,    AArch64::AEK_HBC,       AArch64::AEK_MOPS,
       AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,    AArch64::AEK_SME2p1,
       AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
       AArch64::AEK_RCPC3,   AArch64::AEK_THE,       AArch64::AEK_D128,
-      AArch64::AEK_LSE128,
+      AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,
   };
 
   std::vector<StringRef> Features;
 
   uint64_t ExtVal = 0;
   for (auto Ext : Extensions)
     ExtVal |= Ext;
 
TEST(TargetParserTest, AArch64ExtensionFeatures) {
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
   EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+rcpc3"));
   EXPECT_TRUE(llvm::is_contained(Features, "+the"));
   EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
   EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
   // result despite its bit being set)
   std::vector<StringRef> AllFeatures;
   EXPECT_TRUE(AArch64::getExtensionFeatures(-1, AllFeatures));
   EXPECT_THAT(Features, ::testing::ContainerEq(AllFeatures));
 }
const char *ArchExt[][4] = {
       {"sme-f64f64", "nosme-f64f64", "+sme-f64f64", "-sme-f64f64"},
       {"sme-i16i64", "nosme-i16i64", "+sme-i16i64", "-sme-i16i64"},
       {"sme-f16f16", "nosme-f16f16", "+sme-f16f16", "-sme-f16f16"},
       {"sme2", "nosme2", "+sme2", "-sme2"},
       {"sme2p1", "nosme2p1", "+sme2p1", "-sme2p1"},
       {"hbc", "nohbc", "+hbc", "-hbc"},
       {"mops", "nomops", "+mops", "-mops"},
       {"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
+      {"predres2", "nopredres2", "+specres2", "-specres2"},
   };
 
   for (unsigned i = 0; i < std::size(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
               AArch64::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]),
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
 
 } // namespace