This is an archive of the discontinued LLVM Phabricator instance.

[AMDGPU] Add support for new LLVM vector types

Authored by matejam on Nov 17 2022, 6:27 AM.



Add support on AMDGPU for vector types (v9i32, v10i32, v11i32, v12i32, and all those for f32).
Also add register types VReg, AReg and SReg with bit widths: 288, 320, 352, 384.

Diff Detail

Event Timeline

matejam created this revision.Nov 17 2022, 6:27 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 17 2022, 6:27 AM
matejam requested review of this revision.Nov 17 2022, 6:27 AM

Missing codegen tests for the loads/stores and the various vector operations, plus undef

matejam updated this revision to Diff 477134.Nov 22 2022, 4:25 AM

Added codegen tests for loads/stores, inserting elements into an empty vector and other vector operations.

matejam updated this revision to Diff 477499.Nov 23 2022, 7:27 AM

Minor change in insert_vector_elt.ll test.

arsenm accepted this revision.Nov 28 2022, 1:46 PM

LGTM. Tests may conflict with opaque pointer patches


New tests should use opaque pointers

This revision is now accepted and ready to land.Nov 28 2022, 1:46 PM
matejam updated this revision to Diff 478565.Nov 29 2022, 6:39 AM

Rebase + updated tests (use opaque pointers).

This revision was landed with ongoing or failed builds.Nov 29 2022, 8:02 AM
This revision was automatically updated to reflect the committed changes.