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mbrkusanin (Mirko Brkusanin)
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User Since
Feb 19 2019, 1:58 AM (83 w, 5 d)

Recent Activity

Fri, Sep 25

mbrkusanin requested review of D88315: [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer.
Fri, Sep 25, 9:10 AM · Restricted Project
mbrkusanin updated the diff for D87140: [GlobalISel] Avoid making G_PTR_ADD with nullptr.
Fri, Sep 25, 9:04 AM · Restricted Project

Fri, Sep 18

mbrkusanin committed rGae36c02ad0cb: [AMDGPU] Set DS alignment requirements to be more strict (authored by mbrkusanin).
[AMDGPU] Set DS alignment requirements to be more strict
Fri, Sep 18, 6:28 AM
mbrkusanin closed D87821: [AMDGPU] Set DS alignment requirements to be more strict.
Fri, Sep 18, 6:28 AM · Restricted Project
mbrkusanin updated the diff for D87821: [AMDGPU] Set DS alignment requirements to be more strict.
Fri, Sep 18, 5:07 AM · Restricted Project

Thu, Sep 17

mbrkusanin updated the diff for D87821: [AMDGPU] Set DS alignment requirements to be more strict.
  • Added run line with -mattr=+unaligned-access-mode to test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
Thu, Sep 17, 7:40 AM · Restricted Project
mbrkusanin updated the diff for D87821: [AMDGPU] Set DS alignment requirements to be more strict.
  • Removed dword-access-mode from tests.
Thu, Sep 17, 6:48 AM · Restricted Project
mbrkusanin added inline comments to D87821: [AMDGPU] Set DS alignment requirements to be more strict.
Thu, Sep 17, 6:47 AM · Restricted Project
mbrkusanin added a comment to D87821: [AMDGPU] Set DS alignment requirements to be more strict.

This helps vulkan gfx9 windows tests.

Thu, Sep 17, 2:54 AM · Restricted Project
mbrkusanin requested review of D87821: [AMDGPU] Set DS alignment requirements to be more strict.
Thu, Sep 17, 2:53 AM · Restricted Project

Wed, Sep 16

mbrkusanin updated the diff for D87140: [GlobalISel] Avoid making G_PTR_ADD with nullptr.
  • Reimplemented as a AMDGPU GICombineRule.
Wed, Sep 16, 5:40 AM · Restricted Project

Wed, Sep 9

mbrkusanin closed D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.

43af2a6faa272565cde4e3eec7dfeac593d29701

Wed, Sep 9, 2:53 AM · Restricted Project
mbrkusanin committed rG43af2a6faa27: [AMDGPU] Workaround for LDS Misalignment bug on GFX10 (authored by mbrkusanin).
[AMDGPU] Workaround for LDS Misalignment bug on GFX10
Wed, Sep 9, 2:48 AM

Tue, Sep 8

mbrkusanin updated the diff for D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.
  • Added FeatureLdsMisalignedBug to GFX 10.1.1
Tue, Sep 8, 2:55 AM · Restricted Project

Fri, Sep 4

mbrkusanin requested review of D87140: [GlobalISel] Avoid making G_PTR_ADD with nullptr.
Fri, Sep 4, 6:04 AM · Restricted Project
mbrkusanin added a comment to D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.

Can you add a comment to hasLDSMisalignedBug with what specifically is broken? Is b64 broken too?

Fri, Sep 4, 5:23 AM · Restricted Project
mbrkusanin updated the diff for D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.
  • Updated description of FeatureLdsMisalignedBug to match what is covered by tests.
Fri, Sep 4, 5:22 AM · Restricted Project

Thu, Sep 3

mbrkusanin added a comment to D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.

Note that tests with flat instructions are not copied to GlobalISel/lds-misaligned-bug.ll. While we can put similar check in allowsMisalignedMemoryAccessesImpl for flat address space as well it will cause SDag to produce less optimal code. For some reason it will break down a load 16, align 8 into four flat_load_dword instead of two flat_load_dwordx2 instructions (but not similar stores). This patch should fix problems mentioned in D84403 while I look into this.

Thu, Sep 3, 7:56 AM · Restricted Project
mbrkusanin requested review of D87093: [AMDGPU] Workaround for LDS Misalignment bug on GFX10.
Thu, Sep 3, 7:54 AM · Restricted Project

Wed, Sep 2

mbrkusanin added a comment to D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.

This breaks LDS. LLVMSetAlignment(inst, 4) on loads and stores has no effect. The IR says "align 4", yet the backend still selects b128.

On what subtargets? GFX9 and 10 should select b128 for align 4. That is the purpose of the patch. Are you saying it selects it for SI, CI or VI?

On GFX10. Apparently b128 with align 4 doesn't work there.

Wed, Sep 2, 2:21 AM · Restricted Project

Tue, Sep 1

mbrkusanin added a comment to D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.

This breaks LDS. LLVMSetAlignment(inst, 4) on loads and stores has no effect. The IR says "align 4", yet the backend still selects b128.

Tue, Sep 1, 1:50 AM · Restricted Project

Aug 21 2020

mbrkusanin committed rG0654ff703d4e: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag (authored by mbrkusanin).
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
Aug 21 2020, 3:31 AM
mbrkusanin committed rGd17ea67b92f6: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores (authored by mbrkusanin).
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
Aug 21 2020, 3:31 AM
mbrkusanin committed rGf5cd7ec9f3fc: [AMDGPU] Reorganize GCN subtarget features for unaligned access (authored by mbrkusanin).
[AMDGPU] Reorganize GCN subtarget features for unaligned access
Aug 21 2020, 3:31 AM
mbrkusanin committed rG5bd1febe214f: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores (authored by mbrkusanin).
[AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores
Aug 21 2020, 3:31 AM
mbrkusanin closed D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
Aug 21 2020, 3:31 AM · Restricted Project
mbrkusanin closed D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Aug 21 2020, 3:31 AM · Restricted Project
mbrkusanin closed D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
Aug 21 2020, 3:31 AM · Restricted Project
mbrkusanin closed D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Aug 21 2020, 3:31 AM · Restricted Project

Aug 20 2020

mbrkusanin added inline comments to D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
Aug 20 2020, 4:46 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
  • Updated llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
Aug 20 2020, 4:04 AM · Restricted Project
mbrkusanin updated the diff for D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
  • Removed FeatureDoesNot* ones.
Aug 20 2020, 4:03 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.

Issue was in (load 16, align 4, addrspace 3) which should not be legal for gfx7 but because of -global-isel-abort=0 if it crashes it would just give the same MIR as input.
I've changed those to align 8. D81638 will update it again to pick DS_READ_B128 or DS_READ2_B64.

Aug 20 2020, 4:02 AM · Restricted Project

Aug 18 2020

mbrkusanin updated the diff for D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
Aug 18 2020, 9:26 AM · Restricted Project
mbrkusanin added a comment to D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.

Sorry, unfortunate timing. I removed your "accept revision".

Aug 18 2020, 9:14 AM · Restricted Project
mbrkusanin added a comment to D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
Aug 18 2020, 9:12 AM · Restricted Project
mbrkusanin requested review of D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
Aug 18 2020, 9:12 AM · Restricted Project
mbrkusanin updated the diff for D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
  • Addressed comments
Aug 18 2020, 9:12 AM · Restricted Project
mbrkusanin added inline comments to D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Aug 18 2020, 9:10 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Aug 18 2020, 9:08 AM · Restricted Project
mbrkusanin added a comment to D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
  • Addressed comments.
Aug 18 2020, 9:07 AM · Restricted Project
mbrkusanin updated the diff for D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
Aug 18 2020, 9:04 AM · Restricted Project
mbrkusanin added inline comments to D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Aug 18 2020, 9:02 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
  • Rebase
Aug 18 2020, 9:02 AM · Restricted Project

Aug 10 2020

mbrkusanin updated the diff for D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
  • Rebase
  • Ping
Aug 10 2020, 3:20 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
  • Rebase
  • Ping
Aug 10 2020, 3:20 AM · Restricted Project
mbrkusanin updated the diff for D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
  • Rebase
Aug 10 2020, 3:19 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
  • Rebase
  • Ping
Aug 10 2020, 3:19 AM · Restricted Project

Jul 24 2020

mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Moved tests from here to parent revision (mistakenly put them in wrong patch):

  • llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
  • llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
Jul 24 2020, 6:35 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.

Moved tests from child revision to here (mistakenly put them in wrong patch):

  • llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
  • llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
Jul 24 2020, 6:34 AM · Restricted Project
mbrkusanin retitled D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores from AMDGPU: Fix alignment requirements for 96bit and 128bit local loads and stores to [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jul 24 2020, 6:05 AM · Restricted Project
mbrkusanin added a comment to D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
  • Addressed comments.
Jul 24 2020, 6:04 AM · Restricted Project
mbrkusanin updated the diff for D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
  • Rebase
Jul 24 2020, 6:01 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
  • Rebase
Jul 24 2020, 6:00 AM · Restricted Project
mbrkusanin created D84522: [AMDGPU] Reorganize GCN subtarget features for unaligned access.
Jul 24 2020, 5:58 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jul 24 2020, 5:57 AM · Restricted Project

Jul 23 2020

mbrkusanin added a comment to D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.

Also added another child revision that selects these instructions for SDag the same way as for GlobalISel https://reviews.llvm.org/D84403 so the tests will make more sense.

Jul 23 2020, 7:01 AM · Restricted Project
mbrkusanin created D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag.
Jul 23 2020, 6:59 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
  • Rebase
  • Updated to reflect the changes in parent revision.
Jul 23 2020, 6:54 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.

This is the way these requirements and options make sense to me and match the docs.
As for a feature that turns unalingned access for both buffer and ds instructions, I guess it could be something that just acts like -mattr=+unaligned-buffer-access,+unaligned-ds-access but I'm not sure if it's really necessary.

Jul 23 2020, 6:52 AM · Restricted Project

Jul 14 2020

mbrkusanin added inline comments to D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jul 14 2020, 3:00 AM · Restricted Project

Jul 13 2020

mbrkusanin committed rG38998cfa9c1e: [AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot. (authored by mbrkusanin).
[AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
Jul 13 2020, 4:38 AM
mbrkusanin committed rGce23e54162ed: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot (authored by mbrkusanin).
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
Jul 13 2020, 3:17 AM
mbrkusanin closed D83214: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot.
Jul 13 2020, 3:17 AM · Restricted Project

Jul 10 2020

mbrkusanin added inline comments to D83214: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot.
Jul 10 2020, 4:58 AM · Restricted Project
mbrkusanin updated the diff for D83214: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot.
  • Also renamed and updated SDag tests.
Jul 10 2020, 4:57 AM · Restricted Project
mbrkusanin committed rGcf40db21af48: [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping (authored by mbrkusanin).
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
Jul 10 2020, 2:37 AM
mbrkusanin closed D83240: [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping.
Jul 10 2020, 2:37 AM · Restricted Project

Jul 9 2020

mbrkusanin updated the diff for D83240: [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping.
  • Updated tests.
  • Added tests with waterfall loops.
  • Changed them to -stop-after=instruction-select like others for GlobalISel.
Jul 9 2020, 2:44 AM · Restricted Project

Jul 7 2020

mbrkusanin updated the diff for D83214: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot.
  • Addressed comments
  • Also renamed and updated tests for SDag. Let me know if you would rather have this as a separate patch.
Jul 7 2020, 5:55 AM · Restricted Project

Jul 6 2020

mbrkusanin created D83240: [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping.
Jul 6 2020, 9:41 AM · Restricted Project
mbrkusanin created D83214: [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot.
Jul 6 2020, 4:52 AM · Restricted Project

Jul 2 2020

mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Reduced duplicated code for SelectDS64Bit4ByteAligned and SelectDS128Bit8ByteAligned.

Jul 2 2020, 8:05 AM · Restricted Project
mbrkusanin added inline comments to D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jul 2 2020, 7:31 AM · Restricted Project
mbrkusanin updated the diff for D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jul 2 2020, 7:31 AM · Restricted Project

Jun 29 2020

mbrkusanin added inline comments to D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Jun 29 2020, 10:48 AM · Restricted Project
mbrkusanin added inline comments to D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Jun 29 2020, 10:48 AM · Restricted Project
mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Code that was changing alignment requirements from SITargetLowering::allowsMisalignedMemoryAccessesImpl in now in D82788.

Jun 29 2020, 10:15 AM · Restricted Project
mbrkusanin created D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores.
Jun 29 2020, 10:15 AM · Restricted Project

Jun 22 2020

mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Sorry, I was away for a few days.

Jun 22 2020, 8:35 AM · Restricted Project

Jun 16 2020

mbrkusanin updated the diff for D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Looking at ISA .pdf docs for SI (gfx6) and onward I have not found any requirements for alignments on local loads and stores. There are mentions of dword alignment for reads and writes of dword and larger for buffer instructions but nothing more specific for LDS or GDS. SDag likes to break down ds_read/write_b128 in certain cases but does not know about b96. It seems to me that the code was not updated since SI.
Now b96 and b128 will be picked for align 4 and larger (align 2 and 1 are broken down same way as before). Furthermore, there are several Vulkan conformance tests that have align 4 loads and stores (96 and 128) that will now pass.

Jun 16 2020, 9:54 AM · Restricted Project

Jun 12 2020

mbrkusanin added a comment to D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.

Yes, it basically avoids problems of not being able to select 3x32 for local address space. SDag was breaking these down to a ds_read_b64 and ds_read_b32 so I did the same thing for GlobalISel.

Jun 12 2020, 6:58 AM · Restricted Project

Jun 11 2020

mbrkusanin created D81638: [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores.
Jun 11 2020, 3:01 AM · Restricted Project

Jun 10 2020

mbrkusanin added a comment to D81524: AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads.

What about DS_READ? Following are also broken:

Jun 10 2020, 7:04 AM · Restricted Project

Feb 11 2020

mbrkusanin committed rG5ba931a84a34: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores. (authored by mbrkusanin).
[Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.
Feb 11 2020, 2:55 AM
mbrkusanin closed D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..
Feb 11 2020, 2:55 AM · Restricted Project, Restricted Project
mbrkusanin updated the diff for D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..
  • Rebase
  • Rename ldrq_w to ldr_w; Rename strq_w to str_w.
Feb 11 2020, 2:44 AM · Restricted Project, Restricted Project

Feb 7 2020

mbrkusanin added a comment to D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..

Not yet, a proposal was made to both GCC and LLVM and as far as I can tell no work was done on GCC yet. If we accept these names I'll let them know so we end up with matching names.

Feb 7 2020, 6:12 AM · Restricted Project, Restricted Project
mbrkusanin added a comment to D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..

Rebase.

Feb 7 2020, 6:03 AM · Restricted Project, Restricted Project
mbrkusanin updated the diff for D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..
Feb 7 2020, 6:03 AM · Restricted Project, Restricted Project

Jan 30 2020

mbrkusanin added a comment to D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..

We could do that for loads. For example on Mips32r5 (where we need most instructions) for intrinsic ldr_d instead of:

Jan 30 2020, 7:55 AM · Restricted Project, Restricted Project

Jan 29 2020

mbrkusanin added a comment to D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..

A few notes/questions:

Jan 29 2020, 10:16 AM · Restricted Project, Restricted Project
mbrkusanin created D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores..
Jan 29 2020, 10:07 AM · Restricted Project, Restricted Project

Dec 12 2019

mbrkusanin closed D71028: [Mips] Add support for min/max/umin/umax atomics.
Dec 12 2019, 3:02 AM · Restricted Project
mbrkusanin committed rGd7357c52a40a: [Mips] Add support for min/max/umin/umax atomics (authored by mbrkusanin).
[Mips] Add support for min/max/umin/umax atomics
Dec 12 2019, 2:44 AM

Dec 11 2019

mbrkusanin updated the diff for D71028: [Mips] Add support for min/max/umin/umax atomics.

Sorry @atanasyan, you already reviewed this, but for Mips64 tests would fail with -verify-machineinstrs option. Apparently both 'SLT' and 'SLT64' use GPR32 for result. It's been corrected now and there should be no issues for EXPENSIVE_CHECKS builds. Can you take a quick look at new changes? Thanks.

Dec 11 2019, 7:22 AM · Restricted Project

Dec 5 2019

mbrkusanin updated the summary of D71028: [Mips] Add support for min/max/umin/umax atomics.
Dec 5 2019, 2:02 AM · Restricted Project

Dec 4 2019

mbrkusanin updated the summary of D71028: [Mips] Add support for min/max/umin/umax atomics.
Dec 4 2019, 10:50 AM · Restricted Project
mbrkusanin added a comment to D71028: [Mips] Add support for min/max/umin/umax atomics.

There is a trick we can do to avoid taking an additional register. We can reuse either OldVal or Incr for intermediate results. I know that return value needs to be same as OldVal but I don't know if changing Incr is allowed.

Dec 4 2019, 10:50 AM · Restricted Project
mbrkusanin created D71028: [Mips] Add support for min/max/umin/umax atomics.
Dec 4 2019, 10:39 AM · Restricted Project