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Differential D136690

[AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions
ClosedPublic

Authored by david-arm on Oct 25 2022, 7:59 AM.

Details

Reviewers
sdesmalen
CarolineConcatto
aemerson
paulwalker-arm
kmclaughlin
efriedma
Commits
rG4b48c3993be0: [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

sqrshrn : Signed saturating rounding shift right narrow by immediate and interleave
sqrshrun : Signed saturating rounding shift right unsigned narrow by immediate and interleave
uqrshrn : Unsigned saturating rounding shift right narrow by immediate and interleave

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Oct 25 2022, 7:59 AM
Herald added a reviewer: efriedma. · View Herald TranscriptOct 25 2022, 7:59 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Oct 25 2022, 7:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 25 2022, 7:59 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B194186: Diff 470497.Oct 25 2022, 9:55 AM
paulwalker-arm added inline comments.Oct 25 2022, 12:16 PM
llvm/lib/Target/AArch64/SVEInstrFormats.td
8701

Much like D136689 can you expose tsz at this level and then hide it with a multiclass?

david-arm updated this revision to Diff 471045.Oct 27 2022, 12:45 AM
  • Expose tsz field to the class
david-arm marked an inline comment as done.Oct 27 2022, 12:45 AM
Harbormaster completed remote builds in B194574: Diff 471045.Oct 27 2022, 2:06 AM
paulwalker-arm accepted this revision.Oct 27 2022, 4:44 PM
paulwalker-arm added inline comments.
llvm/lib/Target/AArch64/SVEInstrFormats.td
8714

Sorry I missed this during my previous review but looking at the decode table opc should be Inst{13-11}.

This revision is now accepted and ready to land.Oct 27 2022, 4:44 PM
david-arm added inline comments.Oct 27 2022, 11:04 PM
llvm/lib/Target/AArch64/SVEInstrFormats.td
8714

Sure I can do that, except I'll be passing in exactly the same bit 11 for all instructions.

paulwalker-arm added inline comments.Oct 28 2022, 2:33 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
8714

Yep I understand, I just prefer to match the encoding group so there's potentially less work when adding new instructions later.

Matt added a subscriber: Matt.Oct 29 2022, 8:21 AM
This revision was landed with ongoing or failed builds.Oct 31 2022, 6:46 AM
Closed by commit rG4b48c3993be0: [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions (authored by david-arm). · Explain Why
This revision was automatically updated to reflect the committed changes.
david-arm added a commit: rG4b48c3993be0: [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
3 lines
25 lines
test/
MC/
AArch64/
SVE2p1/
40 lines
38 lines
40 lines
38 lines
40 lines
38 lines

Diff 471987

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,589 Lines • ▼ Show 20 Lines
def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>; def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">; defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">; defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;
defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>; defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>; defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>; defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
defm SQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101>;
defm UQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111>;
defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001>;
} // End HasSVE2p1_or_HasSME2 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,692 Lines • ▼ Show 20 Linesclass sve2p1_two_way_dot_vvi<string mnemonic, bit u>
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = DestructiveOther; let DestructiveInstType = DestructiveOther;
} }
class sve2p1_ptrue_pn<string mnemonic, bits<2> sz, PNRP8to15RegOp pnrty> class sve2p1_ptrue_pn<string mnemonic, bits<2> sz, PNRP8to15RegOp pnrty>
: I<(outs pnrty:$PNd), (ins ), mnemonic, "\t$PNd", : I<(outs pnrty:$PNd), (ins ), mnemonic, "\t$PNd",
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Much like D136689 can you expose tsz at this level and then hide it with a multiclass?

paulwalker-arm: Much like D136689 can you expose `tsz` at this level and then hide it with a multiclass?
"", []>, Sched<[]> { "", []>, Sched<[]> {
bits<3> PNd; bits<3> PNd;
let Inst{31-24} = 0b00100101; let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21-3} = 0b1000000111100000010; let Inst{21-3} = 0b1000000111100000010;
let Inst{2-0} = PNd; let Inst{2-0} = PNd;
} }
multiclass sve2p1_ptrue_pn<string mnemonic> { multiclass sve2p1_ptrue_pn<string mnemonic> {
def _B : sve2p1_ptrue_pn<mnemonic, 0b00, PNR8_p8to15>; def _B : sve2p1_ptrue_pn<mnemonic, 0b00, PNR8_p8to15>;
def _H : sve2p1_ptrue_pn<mnemonic, 0b01, PNR16_p8to15>; def _H : sve2p1_ptrue_pn<mnemonic, 0b01, PNR16_p8to15>;
def _S : sve2p1_ptrue_pn<mnemonic, 0b10, PNR32_p8to15>; def _S : sve2p1_ptrue_pn<mnemonic, 0b10, PNR32_p8to15>;
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Sorry I missed this during my previous review but looking at the decode table opc should be Inst{13-11}.

paulwalker-arm: Sorry I missed this during my previous review but looking at the decode table `opc` should be…
david-armAuthorUnsubmitted
Done
ReplyInline Actions

Sure I can do that, except I'll be passing in exactly the same bit 11 for all instructions.

david-arm: Sure I can do that, except I'll be passing in exactly the same bit 11 for all instructions.
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Yep I understand, I just prefer to match the encoding group so there's potentially less work when adding new instructions later.

paulwalker-arm: Yep I understand, I just prefer to match the encoding group so there's potentially less work…
def _D : sve2p1_ptrue_pn<mnemonic, 0b11, PNR64_p8to15>; def _D : sve2p1_ptrue_pn<mnemonic, 0b11, PNR64_p8to15>;
} }
class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty> class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty>
: I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, VectorIndexS:$imm2), : I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, VectorIndexS:$imm2),
mnemonic, "\t$Pd, $PNn$imm2", mnemonic, "\t$Pd, $PNn$imm2",
"", []>, Sched<[]> { "", []>, Sched<[]> {
Show All 35 Linesclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
let Inst{9-6} = Zn; let Inst{9-6} = Zn;
let Inst{5} = 0b0; let Inst{5} = 0b0;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
} }
multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc> { multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc> {
def : sve2p1_multi_vec_extract_narrow<mnemonic, opc, 0b010>; def : sve2p1_multi_vec_extract_narrow<mnemonic, opc, 0b010>;
} }
// SVE2 multi-vec shift narrow
class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz>
: I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4),
mnemonic, "\t$Zd, $Zn, $imm4",
"", []>, Sched<[]> {
bits<5> Zd;
bits<4> Zn;
bits<4> imm4;
let Inst{31-23} = 0b010001011;
let Inst{22} = tsz{1};
let Inst{21} = 0b1;
let Inst{20} = tsz{0};
let Inst{19-16} = imm4;
let Inst{15-14} = 0b00;
let Inst{13-11} = opc;
let Inst{10} = 0b0;
let Inst{9-6} = Zn;
let Inst{5} = 0b0;
let Inst{4-0} = Zd;
}
multiclass sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc> {
def : sve2p1_multi_vec_shift_narrow<mnemonic, opc, 0b01>;
}

llvm/test/MC/AArch64/SVE2p1/sqrshrn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshrn z0.h, {z0.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshrn z0.h, {z0.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrn z0.h, {z1.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqrshrn z0.h, {z1.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
sqrshrn z0.b, {z0.s-z1.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrn z0.b, {z0.s-z1.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrn z0.h, {z0.d-z1.d}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshrn z0.h, {z0.d-z1.d}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshrn z0.h, {z0.s-z1.s}, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: sqrshrn z0.h, {z0.s-z1.s}, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrn z0.h, {z0.s-z1.s}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: sqrshrn z0.h, {z0.s-z1.s}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sqrshrn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshrn z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00101000-00000000
// CHECK-INST: sqrshrn z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x00,0x28,0xb0,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b02800 <unknown>
sqrshrn z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00101001-01010101
// CHECK-INST: sqrshrn z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x55,0x29,0xb5,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b52955 <unknown>
sqrshrn z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00101001-10010111
// CHECK-INST: sqrshrn z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0x97,0x29,0xb8,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b82997 <unknown>
sqrshrn z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00101011-11011111
// CHECK-INST: sqrshrn z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xdf,0x2b,0xbf,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45bf2bdf <unknown>

llvm/test/MC/AArch64/SVE2p1/sqrshrun-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshrun z0.h, {z0.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshrun z0.h, {z0.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrun z0.h, {z1.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqrshrun z0.h, {z1.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
sqrshrun z0.b, {z0.s-z1.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrun z0.b, {z0.s-z1.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrun z0.h, {z0.d-z1.d}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshrun z0.h, {z0.d-z1.d}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshrun z0.h, {z0.s-z1.s}, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: sqrshrun z0.h, {z0.s-z1.s}, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrun z0.h, {z0.s-z1.s}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: sqrshrun z0.h, {z0.s-z1.s}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sqrshrun.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshrun z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00001000-00000000
// CHECK-INST: sqrshrun z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x00,0x08,0xb0,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b00800 <unknown>
sqrshrun z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00001001-01010101
// CHECK-INST: sqrshrun z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x55,0x09,0xb5,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b50955 <unknown>
sqrshrun z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00001001-10010111
// CHECK-INST: sqrshrun z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0x97,0x09,0xb8,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b80997 <unknown>
sqrshrun z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00001011-11011111
// CHECK-INST: sqrshrun z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xdf,0x0b,0xbf,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45bf0bdf <unknown>

llvm/test/MC/AArch64/SVE2p1/uqrshrn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
uqrshrn z0.h, {z0.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshrn z0.h, {z0.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrn z0.h, {z1.s-z2.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: uqrshrn z0.h, {z1.s-z2.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
uqrshrn z0.b, {z0.s-z1.s}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrn z0.b, {z0.s-z1.s}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrn z0.h, {z0.d-z1.d}, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshrn z0.h, {z0.d-z1.d}, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
uqrshrn z0.h, {z0.s-z1.s}, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: uqrshrn z0.h, {z0.s-z1.s}, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrn z0.h, {z0.s-z1.s}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: uqrshrn z0.h, {z0.s-z1.s}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uqrshrn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqrshrn z0.h, {z0.s-z1.s}, #16 // 01000101-10110000-00111000-00000000
// CHECK-INST: uqrshrn z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x00,0x38,0xb0,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b03800 <unknown>
uqrshrn z21.h, {z10.s-z11.s}, #11 // 01000101-10110101-00111001-01010101
// CHECK-INST: uqrshrn z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x55,0x39,0xb5,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b53955 <unknown>
uqrshrn z23.h, {z12.s-z13.s}, #8 // 01000101-10111000-00111001-10010111
// CHECK-INST: uqrshrn z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0x97,0x39,0xb8,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45b83997 <unknown>
uqrshrn z31.h, {z30.s-z31.s}, #1 // 01000101-10111111-00111011-11011111
// CHECK-INST: uqrshrn z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xdf,0x3b,0xbf,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45bf3bdf <unknown>