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Differential D136689

[AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions
ClosedPublic

Authored by david-arm on Oct 25 2022, 7:51 AM.

Details

Reviewers
sdesmalen
CarolineConcatto
aemerson
paulwalker-arm
kmclaughlin
efriedma
Commits
rG08a26a4d8f72: [AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

sqcvtn : Signed saturating extract narrow and interleave
sqcvtun : Signed saturating unsigned extract narrow and interleave
uqcvtn : Unsigned saturating extract narrow and interleave

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Oct 25 2022, 7:51 AM
Herald added a reviewer: efriedma. · View Herald TranscriptOct 25 2022, 7:51 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Oct 25 2022, 7:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 25 2022, 7:51 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B194184: Diff 470495.Oct 25 2022, 9:52 AM
paulwalker-arm added inline comments.Oct 25 2022, 10:51 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
8701

Do you mind exposing tsz8_64 at this level to match sve2_int_sat_extract_narrow...? I know we only need one size right now but structurally this will make it easier to update in the future. You can still have multiclass sve2p1_multi_vec_extract_narrow that uses this minimalist interface, again much like how sve2_int_sat_extract_narrow_bottom works. We'll need the multiclass anyway once we start enabling code generation.

llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s
8

Just an observation but it seems preferable to get the same nice error message as we do for the {z1.s-z2.s} case.

paulwalker-arm mentioned this in D136690: [AArch64][SVE2] Add the SVE2.1 shift-and-narrow instructions.Oct 25 2022, 12:16 PM
david-arm updated this revision to Diff 471038.Oct 27 2022, 12:28 AM
  • Expose tsz to the class
david-arm marked an inline comment as done.Oct 27 2022, 12:35 AM
david-arm added inline comments.
llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s
8

If I get chance I can try to take a look at this. I suspect it's probably due to non-matching suffixes for the single vector and vector list. We probably need to change how we deal with diagnostics for ZZ_s_mul_r operands.

Harbormaster completed remote builds in B194568: Diff 471038.Oct 27 2022, 2:11 AM
paulwalker-arm accepted this revision.Oct 27 2022, 4:50 PM
This revision is now accepted and ready to land.Oct 27 2022, 4:50 PM
Closed by commit rG08a26a4d8f72: [AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions (authored by david-arm). · Explain WhyOct 27 2022, 11:59 PM
This revision was automatically updated to reflect the committed changes.
david-arm added a commit: rG08a26a4d8f72: [AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
24 lines
test/
MC/
AArch64/
SVE2p1/
27 lines
38 lines
27 lines
38 lines
27 lines
38 lines

Diff 471413

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,583 Lines • ▼ Show 20 Lines
def SDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"sdot", 0b0>; def SDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"sdot", 0b0>;
def UDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"udot", 0b1>; def UDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"udot", 0b1>;
def SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0>; def SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0>;
def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>; def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">; defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">; defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;
defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
} // End HasSVE2p1_or_HasSME2 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,692 Lines • ▼ Show 20 Linesclass sve2p1_two_way_dot_vvi<string mnemonic, bit u>
let Inst{4-0} = Zda; let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda"; let Constraints = "$Zda = $_Zda";
let DestructiveInstType = DestructiveOther; let DestructiveInstType = DestructiveOther;
} }
class sve2p1_ptrue_pn<string mnemonic, bits<2> sz, PNRP8to15RegOp pnrty> class sve2p1_ptrue_pn<string mnemonic, bits<2> sz, PNRP8to15RegOp pnrty>
: I<(outs pnrty:$PNd), (ins ), mnemonic, "\t$PNd", : I<(outs pnrty:$PNd), (ins ), mnemonic, "\t$PNd",
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Do you mind exposing tsz8_64 at this level to match sve2_int_sat_extract_narrow...? I know we only need one size right now but structurally this will make it easier to update in the future. You can still have multiclass sve2p1_multi_vec_extract_narrow that uses this minimalist interface, again much like how sve2_int_sat_extract_narrow_bottom works. We'll need the multiclass anyway once we start enabling code generation.

paulwalker-arm: Do you mind exposing `tsz8_64` at this level to match `sve2_int_sat_extract_narrow...`? I know…
"", []>, Sched<[]> { "", []>, Sched<[]> {
bits<3> PNd; bits<3> PNd;
let Inst{31-24} = 0b00100101; let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz; let Inst{23-22} = sz;
let Inst{21-3} = 0b1000000111100000010; let Inst{21-3} = 0b1000000111100000010;
let Inst{2-0} = PNd; let Inst{2-0} = PNd;
} }
Show All 24 Lines
multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> { multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> {
def _B : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b00, PPR8>; def _B : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b00, PPR8>;
def _H : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b01, PPR16>; def _H : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b01, PPR16>;
def _S : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b10, PPR32>; def _S : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b10, PPR32>;
def _D : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b11, PPR64>; def _D : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b11, PPR64>;
} }
// SME2 multi-vec extract narrow
class sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
: I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
mnemonic, "\t$Zd, $Zn",
"", []>, Sched<[]> {
bits<5> Zd;
bits<4> Zn;
let Inst{31-23} = 0b010001010;
let Inst{22} = tsz{2};
let Inst{21} = 0b1;
let Inst{20-19} = tsz{1-0};
let Inst{18-13} = 0b001010;
let Inst{12-11} = opc;
let Inst{10} = 0b0;
let Inst{9-6} = Zn;
let Inst{5} = 0b0;
let Inst{4-0} = Zd;
}
multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc> {
def : sve2p1_multi_vec_extract_narrow<mnemonic, opc, 0b010>;
}

llvm/test/MC/AArch64/SVE2p1/sqcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvtn z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtn z0.h, {z0.s-z2.s}
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Just an observation but it seems preferable to get the same nice error message as we do for the {z1.s-z2.s} case.

paulwalker-arm: Just an observation but it seems preferable to get the same nice error message as we do for the…
david-armAuthorUnsubmitted
Done
ReplyInline Actions

If I get chance I can try to take a look at this. I suspect it's probably due to non-matching suffixes for the single vector and vector list. We probably need to change how we deal with diagnostics for ZZ_s_mul_r operands.

david-arm: If I get chance I can try to take a look at this. I suspect it's probably due to non-matching…
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtn z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqcvtn z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
sqcvtn z0.b, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqcvtn z0.b, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtn z0.h, {z0.d-z1.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtn z0.h, {z0.d-z1.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sqcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvtn z0.h, {z0.s-z1.s} // 01000101-00110001-01000000-00000000
// CHECK-INST: sqcvtn z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0x40,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314000 <unknown>
sqcvtn z21.h, {z10.s-z11.s} // 01000101-00110001-01000001-01010101
// CHECK-INST: sqcvtn z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0x41,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314155 <unknown>
sqcvtn z23.h, {z12.s-z13.s} // 01000101-00110001-01000001-10010111
// CHECK-INST: sqcvtn z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0x41,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314197 <unknown>
sqcvtn z31.h, {z30.s-z31.s} // 01000101-00110001-01000011-11011111
// CHECK-INST: sqcvtn z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0x43,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 453143df <unknown>

llvm/test/MC/AArch64/SVE2p1/sqcvtun-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqcvtun z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtun z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtun z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqcvtun z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
sqcvtun z0.b, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqcvtun z0.b, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcvtun z0.h, {z0.d-z1.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqcvtun z0.h, {z0.d-z1.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sqcvtun.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqcvtun z0.h, {z0.s-z1.s} // 01000101-00110001-01010000-00000000
// CHECK-INST: sqcvtun z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0x50,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45315000 <unknown>
sqcvtun z21.h, {z10.s-z11.s} // 01000101-00110001-01010001-01010101
// CHECK-INST: sqcvtun z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0x51,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45315155 <unknown>
sqcvtun z23.h, {z12.s-z13.s} // 01000101-00110001-01010001-10010111
// CHECK-INST: sqcvtun z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0x51,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45315197 <unknown>
sqcvtun z31.h, {z30.s-z31.s} // 01000101-00110001-01010011-11011111
// CHECK-INST: sqcvtun z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0x53,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 453153df <unknown>

llvm/test/MC/AArch64/SVE2p1/uqcvtn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
uqcvtn z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqcvtn z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqcvtn z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: uqcvtn z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffixes
uqcvtn z0.b, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqcvtn z0.b, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqcvtn z0.h, {z0.d-z1.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqcvtn z0.h, {z0.d-z1.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uqcvtn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqcvtn z0.h, {z0.s-z1.s} // 01000101-00110001-01001000-00000000
// CHECK-INST: uqcvtn z0.h, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0x48,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314800 <unknown>
uqcvtn z21.h, {z10.s-z11.s} // 01000101-00110001-01001001-01010101
// CHECK-INST: uqcvtn z21.h, { z10.s, z11.s }
// CHECK-ENCODING: [0x55,0x49,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314955 <unknown>
uqcvtn z23.h, {z12.s-z13.s} // 01000101-00110001-01001001-10010111
// CHECK-INST: uqcvtn z23.h, { z12.s, z13.s }
// CHECK-ENCODING: [0x97,0x49,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314997 <unknown>
uqcvtn z31.h, {z30.s-z31.s} // 01000101-00110001-01001011-11011111
// CHECK-INST: uqcvtn z31.h, { z30.s, z31.s }
// CHECK-ENCODING: [0xdf,0x4b,0x31,0x45]
// CHECK-ERROR: instruction requires: sme2 or sve2p1
// CHECK-UNKNOWN: 45314bdf <unknown>