[AArch64][SVE2] Add the SVE2.1 fdot instructions

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instructions:

FDOT : Half-precision floating-point dot product
FDOT : Half-precision floating-point indexed dot product

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[david-arm]

llvm/test/MC/AArch64/SME2/fdot_sme2_or_sve2p1-diagnostics.s

1 ↗

(On Diff #469496)

I just realised these tests should probably be moved to SVE2. I'll do that in an update!

[david-arm]

• Rebase.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3579

I think this should be ZZZI

[david-arm]

• Renamed FDOT_ZZI to FDOT_ZZZI.

[c-rhodes]

llvm/test/MC/AArch64/SME2/fdot_sme2_or_sve2p1-diagnostics.s

1 ↗

(On Diff #469496)

I just realised these tests should probably be moved to SVE2. I'll do that in an update!

how about creating an SVE2.1 directory? And I don't think sme2_or_sve2p1 needs to be in the filename.

[david-arm]

• Moved tests into llvm/test/MC/AArch64/SVE2p1 directory and removed the sme2_or_sve2p1 parts from the names.

[paulwalker-arm]

llvm/lib/Target/AArch64/SVEInstrFormats.td

8221

I guess you taken this by cloning sve_bfloat_dot_base, but is this correct? ElementSize is used for movprfx handling and usually the largest element type is choose. Given these are unpredicated instructions I'm wondering if the easiest fix is to just remove the line?

For what it's worth I suspect sve_bfloat_dot_base is also wrong for the same reason.

8247

As above?

[david-arm]

• Removed ElementType from instruction classes.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3578–3579

Sorry, last drive by comment I promise, but should these be FDOT_ZZZ_S and FDOT_ZZZI_S to match the existing naming style? As before, I think the existing bfloat classes are not to be followed because they're wrong.

[david-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3578–3579

Is that to denote the fact the output size is different to the input, i.e. this is a special case? I just want to make sure we're consistent with naming schemes that's all because the FCLAMP_ZZZ above it doesn't have a _H suffix. It's useful to know for future patches if we should be putting a suffix for the destination element size on everything.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3578–3579

FCLAMP_ZZZ does have this but it's buried within the sve2p1_fclamp multiclass. In general all the SVE instructions end with an element type letter that is usually but not always the result register's element type. See how SDOT/UDOT is defined. The exception here is that currently only a single variant exists but that might not always be the case.

[david-arm]

• Added _S suffix to instruction names.

[david-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3578–3579

Doh! Of course the fclamp are in a multiclass. :face_palm

[paulwalker-arm]

Thanks @david-arm

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 } // End HasSVE2p1_or_HasSME
 
 //===----------------------------------------------------------------------===//
 // SME2 or SVE2.1 instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE2p1_or_HasSME2] in {
 defm FCLAMP_ZZZ : sve2p1_fclamp<"fclamp">;
+def FDOT_ZZZ    : sve_float_dot<0b0, "fdot">;
+def FDOT_ZZI    : sve_float_dot_indexed<0b0, "fdot">;
 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs ZPR32:$Zda), iops, asm, ops, "", []>, Sched<[]> {
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zda;
 
   let Constraints = "$Zda = $_Zda";
   let DestructiveInstType = DestructiveOther;
   let ElementSize = ElementSizeH;
 }
 
-class sve_bfloat_dot<string asm>
-: sve_bfloat_dot_base<0b10, asm, "\t$Zda, $Zn, $Zm",
-  (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm)> {
+class sve_float_dot<bit bf, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
+     asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
   bits<5> Zm;
+  let Inst{31-23} = 0b011001000;
+  let Inst{22}    = bf;
+  let Inst{21}    = 0b1;
   let Inst{20-16} = Zm;
+  let Inst{15-10} = 0b100000;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = DestructiveOther;
+  let ElementSize = ElementSizeH;
 }
 
 multiclass sve_bfloat_dot<string asm, SDPatternOperator op> {
-  def NAME : sve_bfloat_dot<asm>;
+  def NAME : sve_float_dot<0b1, asm>;
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16 ,!cast<Instruction>(NAME)>;
 }
 
-class sve_bfloat_dot_indexed<string asm>
-: sve_bfloat_dot_base<0b01, asm, "\t$Zda, $Zn, $Zm$iop",
-  (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexS:$iop)> {
-  bits<2> iop;
+class sve_float_dot_indexed<bit bf, string asm>
+: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexS:$iop),
+    asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
   bits<3> Zm;
+  bits<2> iop;
+  let Inst{31-23} = 0b011001000;
+  let Inst{22}    = bf;
+  let Inst{21}    = 0b1;
   let Inst{20-19} = iop;
   let Inst{18-16} = Zm;
+  let Inst{15-10} = 0b010000;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = DestructiveOther;
+  let ElementSize = ElementSizeH;
 }
 
 multiclass sve_bfloat_dot_indexed<string asm, SDPatternOperator op> {
-  def NAME : sve_bfloat_dot_indexed<asm>;
+  def NAME : sve_float_dot_indexed<0b1, asm>;
   def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16, i64, VectorIndexS_timm, !cast<Instruction>(NAME)>;
 }
 
 class sve_bfloat_matmul<string asm>
 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
   asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
   bits<5> Zm;
   bits<5> Zda;

llvm/test/MC/AArch64/SVE2/fdot_sme2_or_sve2p1-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+fdot z0.s, z0.h, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fdot z0.s, z0.h, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot z0.s, z0.h, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fdot z0.s, z0.h, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fdot z0.h, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdot z0.h, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot z0.d, z0.h, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fdot z0.d, z0.h, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fdot_sme2_or_sve2p1.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23, z31
+fdot    z23.s, z13.h, z8.h  // 01100100-00101000-10000001-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: fdot    z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x81,0x28,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 642881b7 <unknown>
+
+fdot    z0.s, z0.h, z0.h  // 01100100-00100000-10000000-00000000
+// CHECK-INST: fdot    z0.s, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x20,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64208000 <unknown>
+
+fdot    z21.s, z10.h, z21.h  // 01100100-00110101-10000001-01010101
+// CHECK-INST: fdot    z21.s, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x81,0x35,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64358155 <unknown>
+
+fdot    z23.s, z13.h, z8.h  // 01100100-00101000-10000001-10110111
+// CHECK-INST: fdot    z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x81,0x28,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 642881b7 <unknown>
+
+fdot    z31.s, z31.h, z31.h  // 01100100-00111111-10000011-11111111
+// CHECK-INST: fdot    z31.s, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x83,0x3f,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 643f83ff <unknown>
+
+movprfx z23, z31
+fdot    z23.s, z13.h, z0.h[1]  // 01100100-00101000-01000001-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: fdot    z23.s, z13.h, z0.h[1]
+// CHECK-ENCODING: [0xb7,0x41,0x28,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 642841b7 <unknown>
+
+fdot    z0.s, z0.h, z0.h[0]  // 01100100-00100000-01000000-00000000
+// CHECK-INST: fdot    z0.s, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x40,0x20,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64204000 <unknown>
+
+fdot    z21.s, z10.h, z5.h[2]  // 01100100-00110101-01000001-01010101
+// CHECK-INST: fdot    z21.s, z10.h, z5.h[2]
+// CHECK-ENCODING: [0x55,0x41,0x35,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64354155 <unknown>
+
+fdot    z23.s, z13.h, z0.h[1]  // 01100100-00101000-01000001-10110111
+// CHECK-INST: fdot    z23.s, z13.h, z0.h[1]
+// CHECK-ENCODING: [0xb7,0x41,0x28,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 642841b7 <unknown>
+
+fdot    z31.s, z31.h, z7.h[3]  // 01100100-00111111-01000011-11111111
+// CHECK-INST: fdot    z31.s, z31.h, z7.h[3]
+// CHECK-ENCODING: [0xff,0x43,0x3f,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 643f43ff <unknown>