[AArch64][SVE] Use more flag-setting instructions

[c-rhodes]

Summary

If OP in PTEST(PG, OP(PG, ...)) has a flag-setting variant change the
opcode so the PTEST becomes redundant. This patch extends this existing
optimization in AArch64::optimizePTestInstr to cover all flag-setting
opcodes.

[peterwaller-arm]

LGTM, one nit.

llvm/test/CodeGen/AArch64/sve-ptest-removal-brk.ll

58

Does this want warrant a comment above it that it's a negtest, or in the name? (otherwise it looks like it's covered by the comment at the top of the file, that these should be removed).

llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp

AArch64CondBrTuning() : MachineFunctionPass(ID) {
     initializeAArch64CondBrTuningPass(*PassRegistry::getPassRegistry());
   }
   void getAnalysisUsage(AnalysisUsage &AU) const override;
   bool runOnMachineFunction(MachineFunction &MF) override;
   StringRef getPassName() const override { return AARCH64_CONDBR_TUNING_NAME; }
 
 private:
   MachineInstr *getOperandDef(const MachineOperand &MO);
-  MachineInstr *convertToFlagSetting(MachineInstr &MI, bool IsFlagSetting);
+  MachineInstr *convertToFlagSetting(MachineInstr &MI, bool IsFlagSetting,
+                                     bool Is64Bit);
   MachineInstr *convertToCondBr(MachineInstr &MI);
   bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
 };
 } // end anonymous namespace
 
 char AArch64CondBrTuning::ID = 0;
 
 INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
                 AARCH64_CONDBR_TUNING_NAME, false, false)
 
 void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesCFG();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
   if (!Register::isVirtualRegister(MO.getReg()))
     return nullptr;
   return MRI->getUniqueVRegDef(MO.getReg());
 }
 
 MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,
-                                                        bool IsFlagSetting) {
+                                                        bool IsFlagSetting,
+                                                        bool Is64Bit) {
   // If this is already the flag setting version of the instruction (e.g., SUBS)
   // just make sure the implicit-def of NZCV isn't marked dead.
   if (IsFlagSetting) {
     for (MachineOperand &MO : MI.implicit_operands())
       if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
         MO.setIsDead(false);
     return &MI;
   }
-  bool Is64Bit;
-  unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit);
+  unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode());
   Register NewDestReg = MI.getOperand(0).getReg();
   if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
     NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
 
   MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
                                     TII->get(NewOpc), NewDestReg);
   for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
     MIB.add(MO);
case AArch64::TBNZW:
       // reads NZCV.
       if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI))
         return false;
       LLVM_DEBUG(dbgs() << "  Replacing instructions:\n    ");
       LLVM_DEBUG(DefMI.print(dbgs()));
       LLVM_DEBUG(dbgs() << "    ");
       LLVM_DEBUG(MI.print(dbgs()));
 
-      NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
+      NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/false);
       NewBr = convertToCondBr(MI);
       break;
     }
     break;
 
   case AArch64::ADDXri:
   case AArch64::ADDXrr:
   case AArch64::ADDXrs:
case AArch64::TBNZX: {
       // reads NZCV.
       if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI))
         return false;
       LLVM_DEBUG(dbgs() << "  Replacing instructions:\n    ");
       LLVM_DEBUG(DefMI.print(dbgs()));
       LLVM_DEBUG(dbgs() << "    ");
       LLVM_DEBUG(MI.print(dbgs()));
 
-      NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
+      NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/true);
       NewBr = convertToCondBr(MI);
       break;
     }
     }
     break;
   }
   (void)NewCmp; (void)NewBr;
   assert(NewCmp && NewBr && "Expected new instructions.");

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   /// Returns the index for the immediate for a given instruction.
   static unsigned getLoadStoreImmIdx(unsigned Opc);
 
   /// Return true if pairing the given load or store may be paired with another.
   static bool isPairableLdStInst(const MachineInstr &MI);
 
   /// Return the opcode that set flags when possible.  The caller is
   /// responsible for ensuring the opc has a flag setting equivalent.
-  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
+  static unsigned convertToFlagSettingOpc(unsigned Opc);
 
   /// Return true if this is a load/store that can be potentially paired/merged.
   bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
 
   /// Hint that pairing the given load or store is unprofitable.
   static void suppressLdStPair(MachineInstr &MI);
 
   Optional<ExtAddrMode>

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (isPTrueOpcode(MaskOpcode) && (PredIsPTestLike || PredIsWhileLike)) {
     // For PTEST(PG_1, PTEST_LIKE(PG2, ...)), PTEST is redundant when both
     // instructions use the same predicate.
     auto PTestLikeMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
     if (Mask != PTestLikeMask)
       return false;
 
     // Fallthough to simply remove the PTEST.
   } else {
-    switch (Pred->getOpcode()) {
+    // If OP in PTEST(PG, OP(PG, ...)) has a flag-setting variant change the
+    // opcode so the PTEST becomes redundant.
+    switch (PredOpcode) {
+    case AArch64::AND_PPzPP:
+    case AArch64::BIC_PPzPP:
+    case AArch64::EOR_PPzPP:
+    case AArch64::NAND_PPzPP:
+    case AArch64::NOR_PPzPP:
+    case AArch64::ORN_PPzPP:
+    case AArch64::ORR_PPzPP:
+    case AArch64::BRKA_PPzP:
+    case AArch64::BRKPA_PPzPP:
     case AArch64::BRKB_PPzP:
-    case AArch64::BRKPB_PPzPP: {
-      // Op 0 is chain, 1 is the mask, 2 the previous predicate to
-      // propagate, 3 the new predicate.
-
-      // Check to see if our mask is the same as the brkpb's. If
-      // not the resulting flag bits may be different and we
-      // can't remove the ptest.
+    case AArch64::BRKPB_PPzPP:
+    case AArch64::RDFFR_PPz: {
+      // Check to see if our mask is the same. If not the resulting flag bits
+      // may be different and we can't remove the ptest.
       auto *PredMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
       if (Mask != PredMask)
         return false;
-
-      // Switch to the new opcode
-      NewOp = Pred->getOpcode() == AArch64::BRKB_PPzP ? AArch64::BRKBS_PPzP
-                                                      : AArch64::BRKPBS_PPzPP;
-      OpChanged = true;
       break;
     }
     case AArch64::BRKN_PPzP: {
+      // BRKN uses an all active implicit mask to set flags unlike the other
+      // flag-setting instructions.
       // PTEST(PTRUE_B(31), BRKN(PG, A, B)) -> BRKNS(PG, A, B).
       if ((MaskOpcode != AArch64::PTRUE_B) ||
           (Mask->getOperand(1).getImm() != 31))
         return false;
-
-      NewOp = AArch64::BRKNS_PPzP;
-      OpChanged = true;
       break;
     }
-    case AArch64::RDFFR_PPz: {
-      // rdffr   p1.b, PredMask=p0/z <--- Definition of Pred
-      // ptest   Mask=p0, Pred=p1.b  <--- If equal masks, remove this and use
-      //                                  `rdffrs p1.b, p0/z` above.
-      auto *PredMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg());
-      if (Mask != PredMask)
-        return false;
-
-      NewOp = AArch64::RDFFRS_PPz;
-      OpChanged = true;
+    case AArch64::PTRUE_B:
+      // PTEST(OP=PTRUE_B(A), OP) -> PTRUES_B(A)
       break;
-    }
     default:
       // Bail out if we don't recognize the input
       return false;
     }
+
+    NewOp = convertToFlagSettingOpc(PredOpcode);
+    OpChanged = true;
   }
 
   const TargetRegisterInfo *TRI = &getRegisterInfo();
 
   // If another instruction between Pred and PTest accesses flags, don't remove
   // the ptest or update the earlier instruction to modify them.
   if (areCFlagsAccessedBetweenInstrs(Pred, PTest, TRI))
     return false;
bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
   case AArch64::LDRWpre:
   case AArch64::LDURXi:
   case AArch64::LDRXpre:
   case AArch64::LDURSWi:
     return true;
   }
 }
 
-unsigned AArch64InstrInfo::convertToFlagSettingOpc(unsigned Opc,
-                                                   bool &Is64Bit) {
+unsigned AArch64InstrInfo::convertToFlagSettingOpc(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("Opcode has no flag setting equivalent!");
   // 32-bit cases:
   case AArch64::ADDWri:
-    Is64Bit = false;
     return AArch64::ADDSWri;
   case AArch64::ADDWrr:
-    Is64Bit = false;
     return AArch64::ADDSWrr;
   case AArch64::ADDWrs:
-    Is64Bit = false;
     return AArch64::ADDSWrs;
   case AArch64::ADDWrx:
-    Is64Bit = false;
     return AArch64::ADDSWrx;
   case AArch64::ANDWri:
-    Is64Bit = false;
     return AArch64::ANDSWri;
   case AArch64::ANDWrr:
-    Is64Bit = false;
     return AArch64::ANDSWrr;
   case AArch64::ANDWrs:
-    Is64Bit = false;
     return AArch64::ANDSWrs;
   case AArch64::BICWrr:
-    Is64Bit = false;
     return AArch64::BICSWrr;
   case AArch64::BICWrs:
-    Is64Bit = false;
     return AArch64::BICSWrs;
   case AArch64::SUBWri:
-    Is64Bit = false;
     return AArch64::SUBSWri;
   case AArch64::SUBWrr:
-    Is64Bit = false;
     return AArch64::SUBSWrr;
   case AArch64::SUBWrs:
-    Is64Bit = false;
     return AArch64::SUBSWrs;
   case AArch64::SUBWrx:
-    Is64Bit = false;
     return AArch64::SUBSWrx;
   // 64-bit cases:
   case AArch64::ADDXri:
-    Is64Bit = true;
     return AArch64::ADDSXri;
   case AArch64::ADDXrr:
-    Is64Bit = true;
     return AArch64::ADDSXrr;
   case AArch64::ADDXrs:
-    Is64Bit = true;
     return AArch64::ADDSXrs;
   case AArch64::ADDXrx:
-    Is64Bit = true;
     return AArch64::ADDSXrx;
   case AArch64::ANDXri:
-    Is64Bit = true;
     return AArch64::ANDSXri;
   case AArch64::ANDXrr:
-    Is64Bit = true;
     return AArch64::ANDSXrr;
   case AArch64::ANDXrs:
-    Is64Bit = true;
     return AArch64::ANDSXrs;
   case AArch64::BICXrr:
-    Is64Bit = true;
     return AArch64::BICSXrr;
   case AArch64::BICXrs:
-    Is64Bit = true;
     return AArch64::BICSXrs;
   case AArch64::SUBXri:
-    Is64Bit = true;
     return AArch64::SUBSXri;
   case AArch64::SUBXrr:
-    Is64Bit = true;
     return AArch64::SUBSXrr;
   case AArch64::SUBXrs:
-    Is64Bit = true;
     return AArch64::SUBSXrs;
   case AArch64::SUBXrx:
-    Is64Bit = true;
     return AArch64::SUBSXrx;
+  // SVE instructions:
+  case AArch64::AND_PPzPP:
+    return AArch64::ANDS_PPzPP;
+  case AArch64::BIC_PPzPP:
+    return AArch64::BICS_PPzPP;
+  case AArch64::EOR_PPzPP:
+    return AArch64::EORS_PPzPP;
+  case AArch64::NAND_PPzPP:
+    return AArch64::NANDS_PPzPP;
+  case AArch64::NOR_PPzPP:
+    return AArch64::NORS_PPzPP;
+  case AArch64::ORN_PPzPP:
+    return AArch64::ORNS_PPzPP;
+  case AArch64::ORR_PPzPP:
+    return AArch64::ORRS_PPzPP;
+  case AArch64::BRKA_PPzP:
+    return AArch64::BRKAS_PPzP;
+  case AArch64::BRKPA_PPzPP:
+    return AArch64::BRKPAS_PPzPP;
+  case AArch64::BRKB_PPzP:
+    return AArch64::BRKBS_PPzP;
+  case AArch64::BRKPB_PPzPP:
+    return AArch64::BRKPBS_PPzPP;
+  case AArch64::BRKN_PPzP:
+    return AArch64::BRKNS_PPzP;
+  case AArch64::RDFFR_PPz:
+    return AArch64::RDFFRS_PPz;
+  case AArch64::PTRUE_B:
+    return AArch64::PTRUES_B;
   }
 }
 
 // Is this a candidate for ld/st merging or pairing?  For example, we don't
 // touch volatiles or load/stores that have a hint to avoid pair formation.
 bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
 
   bool IsPreLdSt = isPreLdSt(MI);

llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ; ANDV
 
 define i1 @reduce_and_nxv16i1(<vscale x 16 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_nxv16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.b
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_and_nxv8i1(<vscale x 8 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_nxv8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.h
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_and_nxv4i1(<vscale x 4 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_and_nxv2i1(<vscale x 2 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_nxv2i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_and_nxv1i1(<vscale x 1 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_nxv1i1:

 }
 
 ; SMAXV
 
 define i1 @reduce_smax_nxv16i1(<vscale x 16 x i1> %vec) {
 ; CHECK-LABEL: reduce_smax_nxv16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.b
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_smax_nxv8i1(<vscale x 8 x i1> %vec) {
 ; CHECK-LABEL: reduce_smax_nxv8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.h
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_smax_nxv4i1(<vscale x 4 x i1> %vec) {
 ; CHECK-LABEL: reduce_smax_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_smax_nxv2i1(<vscale x 2 x i1> %vec) {
 ; CHECK-LABEL: reduce_smax_nxv2i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_smax_nxv1i1(<vscale x 1 x i1> %vec) {
 ; CHECK-LABEL: reduce_smax_nxv1i1:

 }
 
 ; UMINV
 
 define i1 @reduce_umin_nxv16i1(<vscale x 16 x i1> %vec) {
 ; CHECK-LABEL: reduce_umin_nxv16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.b
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_umin_nxv8i1(<vscale x 8 x i1> %vec) {
 ; CHECK-LABEL: reduce_umin_nxv8i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.h
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_umin_nxv4i1(<vscale x 4 x i1> %vec) {
 ; CHECK-LABEL: reduce_umin_nxv4i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_umin_nxv1i1(<vscale x 1 x i1> %vec) {
 ; CHECK-LABEL: reduce_umin_nxv1i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
 ; CHECK-NEXT:    punpklo p2.h, p1.b
 ; CHECK-NEXT:    eor p0.b, p1/z, p0.b, p2.b
 ; CHECK-NEXT:    ptest p2, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)
   ret i1 %res
 }
 
 define i1 @reduce_umin_nxv2i1(<vscale x 2 x i1> %vec) {
 ; CHECK-LABEL: reduce_umin_nxv2i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
   ret i1 %res
 }
 
 declare i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
 declare i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)

llvm/test/CodeGen/AArch64/sve-ptest-removal-brk.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
 
 ; Test that redundant ptest instruction is removed when using a flag setting brk
 
 define i32 @brkpa(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: brkpa:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    brkpa p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    brkpas p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   %conv = zext i1 %2 to i32
   ret i32 %conv
 }
 
 define i32 @brkpb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: brkpb:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    brkpbs p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   %conv = zext i1 %2 to i32
   ret i32 %conv
 }
 
 define i32 @brka(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
 ; CHECK-LABEL: brka:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    brka p1.b, p0/z, p1.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    brkas p0.b, p0/z, p1.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   %conv = zext i1 %2 to i32
   ret i32 %conv
 }
 
 define i32 @brkb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
 ; CHECK-LABEL: brkb:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    brkbs p0.b, p0/z, p1.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   %conv = zext i1 %2 to i32
   ret i32 %conv
 }
 
 define i32 @brkn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: brkn:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    brkn p2.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    ptest p0, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   %conv = zext i1 %2 to i32
   ret i32 %conv
 }
 

llvm/test/CodeGen/AArch64/sve-ptest-removal-log.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
 
 ; Test flag-setting bitwise logical instructions are used and redundant ptest
 ; instruction is removed.
 
 define i1 @and(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: and:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    ands p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @bic(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: bic:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    bic p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    bics p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @eor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: eor:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    eor p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    eors p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @nand(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: nand:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    nand p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    nands p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @nor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: nor:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    nor p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    nors p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @orn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: orn:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orn p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    orns p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 define i1 @orr(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
 ; CHECK-LABEL: orr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr p1.b, p0/z, p1.b, p2.b
-; CHECK-NEXT:    ptest p0, p1.b
+; CHECK-NEXT:    orrs p0.b, p0/z, p1.b, p2.b
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
 declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)

llvm/test/CodeGen/AArch64/sve-ptest-removal-ptrue.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
 
 define i1 @ptrue() {
 ; CHECK-LABEL: ptrue:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.b, pow2
-; CHECK-NEXT:    ptest p0, p0.b
+; CHECK-NEXT:    ptrues p0.b, pow2
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
   %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
   ret i1 %2
 }
 
 declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)

llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ; ANDV
 
 define i1 @andv_nxv32i1(<vscale x 32 x i1> %a) {
 ; CHECK-LABEL: andv_nxv32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p2.b
 ; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
-; CHECK-NEXT:    not p0.b, p2/z, p0.b
-; CHECK-NEXT:    ptest p2, p0.b
+; CHECK-NEXT:    nots p0.b, p2/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %a)
   ret i1 %res
 }
 
 define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) {
 ; CHECK-LABEL: andv_nxv64i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
 ; CHECK-NEXT:    and p1.b, p1/z, p1.b, p3.b
 ; CHECK-NEXT:    and p0.b, p0/z, p0.b, p2.b
 ; CHECK-NEXT:    str p4, [sp, #7, mul vl] // 2-byte Folded Spill
 ; CHECK-NEXT:    ptrue p4.b
 ; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
-; CHECK-NEXT:    not p0.b, p4/z, p0.b
-; CHECK-NEXT:    ptest p4, p0.b
+; CHECK-NEXT:    nots p0.b, p4/z, p0.b
 ; CHECK-NEXT:    ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a)
   ret i1 %res
 }

 
 ; SMAXV
 
 define i1 @smaxv_nxv32i1(<vscale x 32 x i1> %a) {
 ; CHECK-LABEL: smaxv_nxv32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p2.b
 ; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
-; CHECK-NEXT:    not p0.b, p2/z, p0.b
-; CHECK-NEXT:    ptest p2, p0.b
+; CHECK-NEXT:    nots p0.b, p2/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %a)
   ret i1 %res
 }
 
 ; SMINV
 

 
 ; UMINV
 
 define i1 @uminv_nxv32i1(<vscale x 32 x i1> %a) {
 ; CHECK-LABEL: uminv_nxv32i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p2.b
 ; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
-; CHECK-NEXT:    not p0.b, p2/z, p0.b
-; CHECK-NEXT:    ptest p2, p0.b
+; CHECK-NEXT:    nots p0.b, p2/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %res = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %a)
   ret i1 %res
 }
 
 declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
 declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)

llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll

 ;
 ; AND reductions
 ;
 
 define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) {
 ; CHECK-LABEL: reduce_and_insert_subvec_into_ones:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %allones.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
   %allones = shufflevector <vscale x 16 x i1> %allones.ins,  <vscale x 16 x i1> poison,  <vscale x 16 x i32> zeroinitializer
   %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %allones, <vscale x 4 x i1> %in, i64 0)
   %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
   ret i1 %res
 }
 
 define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
 ; CHECK-LABEL: reduce_and_insert_subvec_into_poison:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    not p0.b, p1/z, p0.b
-; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    nots p0.b, p1/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
   %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
   ret i1 %res
 }
 
 define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {
 ; CHECK-LABEL: reduce_and_insert_subvec_into_var:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    punpklo p3.h, p1.b
 ; CHECK-NEXT:    punpkhi p1.h, p1.b
 ; CHECK-NEXT:    punpkhi p3.h, p3.b
 ; CHECK-NEXT:    ptrue p2.b
 ; CHECK-NEXT:    uzp1 p0.h, p0.h, p3.h
 ; CHECK-NEXT:    uzp1 p0.b, p0.b, p1.b
-; CHECK-NEXT:    not p0.b, p2/z, p0.b
-; CHECK-NEXT:    ptest p2, p0.b
+; CHECK-NEXT:    nots p0.b, p2/z, p0.b
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
   %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
   ret i1 %res
 }
 
 declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
 declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
 declare <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64)