[AArch64] Add GPR rr instructions to isAssociativeAndCommutative

[dmgreen]

Summary

This adds some more scalar instructions that are both associative and commutative to isAssociativeAndCommutative, allowing the machine combiner to reassociate them to reduce critical path length.

[samtebbs]

From the tests it's not immediately clear what is improved. Have you run any benchmarks to see what improves?

[labrinea]

Looks okay.

[dmgreen]

The swift-return test shows it best, where it changes:

; CHECK:  add     [[TMP:x.*]], x0, x1
; CHECK:  add     [[TMP]], [[TMP]], x2
; CHECK:  add     [[TMP]], [[TMP]], x3
; CHECK:  add     x0, [[TMP]], x4

To:

; CHECK:  add     [[TMP:x.*]], x0, x1
; CHECK:  add     [[TMP2:x.*]], x2, x3
; CHECK:  add     [[TMP]], [[TMP]], [[TMP2]]
; CHECK:  add     x0, [[TMP]], x4

This allow the first two operations to be executed in parallel. This reassociation in the machine combiner is what this patch now allows.

[vitalybuka]

It breaks Msan: https://lab.llvm.org/buildbot/#/builders/237/builds/417
49510c50200cf58c9f2dedf4e4ab36a16503878e OK
c9f0a3e39df223c5bbf63522bbb52a02ca1a06a3 BAD

[abrachet]

I see this has just been reverted but I'd like to add that we have also seen failures, that I've bisected down to this patch. See https://ci.chromium.org/ui/p/fuchsia/builders/prod/clang-linux-arm64/b8797325013179537905/overview, which is a 2 stage clang build. It causes an unrelated test to fail, presumably because of a miscompile.

[dmgreen]

Oh OK, Sorry for the breakage. I would guess it was the ands, that probably doesn't work as I expect it to. It looks like the buildbot went green again a couple of times after this patch, I guess it doesn't always run all the tests?

I'll see if I can reproduce the error. Thanks for the reports and the revert.

[llvm-commits]

Build bot was green only when I scheduled older revisons to find a root
cause.

• msg-14769-465.txt163 BDownload

[dmgreen]

After testing it, I've recommitted this without ANDS and the bot renamed green. Please let me know if any other issues come up.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::isAssociativeAndCommutative(
   case AArch64::FMULXv2f64:
   case AArch64::FMULXv4f32:
   case AArch64::FMULv2f32:
   case AArch64::FMULv2f64:
   case AArch64::FMULv4f32:
     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath ||
            (Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
             Inst.getFlag(MachineInstr::MIFlag::FmNsz));
+  case AArch64::ADDXrr:
+  case AArch64::ANDXrr:
+  case AArch64::ORRXrr:
+  case AArch64::EORXrr:
+  case AArch64::EONXrr:
+  case AArch64::ADDWrr:
+  case AArch64::ANDWrr:
+  case AArch64::ORRWrr:
+  case AArch64::EORWrr:
+  case AArch64::EONWrr:
+    return true;
   default:
     return false;
   }
 }
 
 /// Find instructions that can be turned into madd.
 static bool getMaddPatterns(MachineInstr &Root,
                             SmallVectorImpl<MachineCombinerPattern> &Patterns) {

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_8:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldrb w9, [x0, #4095]
 ; CHECK-NOLSE-O1-NEXT:    ldrb w10, [x0, w1, sxtw]
 ; CHECK-NOLSE-O1-NEXT:    ldurb w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldrb w8, [x8]
-; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
+; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_8:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x0, #4095]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x0, w1, sxtw
 ; CHECK-NOLSE-O0-NEXT:    ldrb w8, [x8]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    subs x9, x0, #256
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_8:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldrb w8, [x0, #4095]
 ; CHECK-LSE-O1-NEXT:    ldrb w9, [x0, w1, sxtw]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
-; CHECK-LSE-O1-NEXT:    ldurb w9, [x0, #-256]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
+; CHECK-LSE-O1-NEXT:    ldurb w10, [x0, #-256]
+; CHECK-LSE-O1-NEXT:    add w8, w8, w10
+; CHECK-LSE-O1-NEXT:    add w8, w9, w8
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldrb w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_8:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldrb w9, [x0, #4095]

 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_16:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldrh w9, [x0, #8190]
 ; CHECK-NOLSE-O1-NEXT:    ldrh w10, [x0, w1, sxtw #1]
 ; CHECK-NOLSE-O1-NEXT:    ldurh w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldrh w8, [x8]
-; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
+; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_16:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x0, #8190]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x0, w1, sxtw #1
 ; CHECK-NOLSE-O0-NEXT:    ldrh w8, [x8]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    subs x9, x0, #256
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_16:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldrh w8, [x0, #8190]
 ; CHECK-LSE-O1-NEXT:    ldrh w9, [x0, w1, sxtw #1]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
-; CHECK-LSE-O1-NEXT:    ldurh w9, [x0, #-256]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
+; CHECK-LSE-O1-NEXT:    ldurh w10, [x0, #-256]
+; CHECK-LSE-O1-NEXT:    add w8, w8, w10
+; CHECK-LSE-O1-NEXT:    add w8, w9, w8
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldrh w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_16:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldrh w9, [x0, #8190]

 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_32:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldr w9, [x0, #16380]
 ; CHECK-NOLSE-O1-NEXT:    ldr w10, [x0, w1, sxtw #2]
 ; CHECK-NOLSE-O1-NEXT:    ldur w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldr w8, [x8]
-; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
+; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_32:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [x0, #16380]
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [x0, w1, sxtw #2]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    ldur w9, [x0, #-256]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_32:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldr w8, [x0, #16380]
 ; CHECK-LSE-O1-NEXT:    ldr w9, [x0, w1, sxtw #2]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
-; CHECK-LSE-O1-NEXT:    ldur w9, [x0, #-256]
-; CHECK-LSE-O1-NEXT:    add w8, w8, w9
+; CHECK-LSE-O1-NEXT:    ldur w10, [x0, #-256]
+; CHECK-LSE-O1-NEXT:    add w8, w8, w10
+; CHECK-LSE-O1-NEXT:    add w8, w9, w8
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldr w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_32:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldr w8, [x0, #16380]

 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_64:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldr x9, [x0, #32760]
 ; CHECK-NOLSE-O1-NEXT:    ldr x10, [x0, w1, sxtw #3]
 ; CHECK-NOLSE-O1-NEXT:    ldur x11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldr x8, [x8]
-; CHECK-NOLSE-O1-NEXT:    add x9, x9, x10
 ; CHECK-NOLSE-O1-NEXT:    add x9, x9, x11
+; CHECK-NOLSE-O1-NEXT:    add x9, x10, x9
 ; CHECK-NOLSE-O1-NEXT:    add x0, x9, x8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_64:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldr x8, [x0, #32760]
 ; CHECK-NOLSE-O0-NEXT:    ldr x9, [x0, w1, sxtw #3]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    ldur x9, [x0, #-256]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldr x9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add x0, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_64:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldr x8, [x0, #32760]
 ; CHECK-LSE-O1-NEXT:    ldr x9, [x0, w1, sxtw #3]
-; CHECK-LSE-O1-NEXT:    add x8, x8, x9
-; CHECK-LSE-O1-NEXT:    ldur x9, [x0, #-256]
-; CHECK-LSE-O1-NEXT:    add x8, x8, x9
+; CHECK-LSE-O1-NEXT:    ldur x10, [x0, #-256]
+; CHECK-LSE-O1-NEXT:    add x8, x8, x10
+; CHECK-LSE-O1-NEXT:    add x8, x9, x8
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldr x9, [x9]
 ; CHECK-LSE-O1-NEXT:    add x0, x8, x9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_64:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldr x8, [x0, #32760]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll

define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURBBi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRBBui killed renamable $x8, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
   %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1, !pcsections !0
 
   %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
   %val_regoff = load atomic i8, i8* %ptr_regoff unordered, align 1, !pcsections !0
   %tot1 = add i8 %val_unsigned, %val_regoff, !pcsections !0
define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURHHi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRHHui killed renamable $x8, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
   %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2, !pcsections !0
 
   %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
   %val_regoff = load atomic i16, i16* %ptr_regoff unordered, align 2, !pcsections !0
   %tot1 = add i16 %val_unsigned, %val_regoff, !pcsections !0
define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURWi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRWui killed renamable $x8, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
   %val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4, !pcsections !0
 
   %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
   %val_regoff = load atomic i32, i32* %ptr_regoff unordered, align 4, !pcsections !0
   %tot1 = add i32 %val_unsigned, %val_regoff, !pcsections !0
define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $x9 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $x10 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $x11 = LDURXi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $x8 = LDRXui killed renamable $x8, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random)
-  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x10, 0, pcsections !0
-  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0, pcsections !0
+  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0
+  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x10, killed renamable $x9, 0
   ; CHECK-NEXT:   $x0 = ADDXrs killed renamable $x9, killed renamable $x8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $x0
   %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
   %val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8, !pcsections !0
 
   %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
   %val_regoff = load atomic i64, i64* %ptr_regoff unordered, align 8, !pcsections !0
   %tot1 = add i64 %val_unsigned, %val_regoff, !pcsections !0

llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

 
 
 define i32 @novla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
 entry:
   %l1 = alloca i32, align 4
   %conv = fptosi double %d10 to i32
   %add = add nsw i32 %conv, %i10
   %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
-  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %add1 = or i32 %add, %l1.0.l1.0.
   %call = tail call i32 @g()
   %add2 = add nsw i32 %add1, %call
   ret i32 %add2
 }
 ; CHECK-LABEL: novla_nodynamicrealign_call
 ; CHECK: .cfi_startproc
 ;   Check that used callee-saved registers are saved
 ; CHECK: sub  sp, sp, #32

 
 
 define i32 @novla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
 entry:
   %l1 = alloca i32, align 128
   %conv = fptosi double %d10 to i32
   %add = add nsw i32 %conv, %i10
   %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
-  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %add1 = or i32 %add, %l1.0.l1.0.
   %call = tail call i32 @g()
   %add2 = add nsw i32 %add1, %call
   ret i32 %add2
 }
 
 ; CHECK-LABEL: novla_dynamicrealign_call
 ; CHECK: .cfi_startproc
 ;   Check that used callee-saved registers are saved

 define i32 @vla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
 entry:
   %l1 = alloca i32, align 4
   %0 = zext i32 %i1 to i64
   %vla = alloca i32, i64 %0, align 4
   %conv = fptosi double %d10 to i32
   %add = add nsw i32 %conv, %i10
   %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
-  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %add1 = or i32 %add, %l1.0.l1.0.
   %call = tail call i32 @g()
   %add2 = add nsw i32 %add1, %call
   %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
   %add3 = add nsw i32 %add2, %1
   ret i32 %add3
 }
 
 ; CHECK-LABEL: vla_nodynamicrealign_call

 define i32 @vla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
 entry:
   %l1 = alloca i32, align 128
   %0 = zext i32 %i1 to i64
   %vla = alloca i32, i64 %0, align 4
   %conv = fptosi double %d10 to i32
   %add = add nsw i32 %conv, %i10
   %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
-  %add1 = add nsw i32 %add, %l1.0.l1.0.
+  %add1 = or i32 %add, %l1.0.l1.0.
   %call = tail call i32 @g()
   %add2 = add nsw i32 %add1, %call
   %1 = load volatile i32, i32* %vla, align 4, !tbaa !1
   %add3 = add nsw i32 %add2, %1
   ret i32 %add3
 }
 
 ; CHECK-LABEL: vla_dynamicrealign_call

llvm/test/CodeGen/AArch64/arm64-rev.ll

 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_rev16_w:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr w8, w0, #8
 ; GISEL-NEXT:    lsl w9, w0, #8
 ; GISEL-NEXT:    and w10, w8, #0xff0000
 ; GISEL-NEXT:    and w11, w9, #0xff000000
+; GISEL-NEXT:    and w8, w8, #0xff
 ; GISEL-NEXT:    and w9, w9, #0xff00
 ; GISEL-NEXT:    orr w10, w11, w10
-; GISEL-NEXT:    and w8, w8, #0xff
-; GISEL-NEXT:    orr w9, w10, w9
-; GISEL-NEXT:    orr w0, w9, w8
+; GISEL-NEXT:    orr w8, w9, w8
+; GISEL-NEXT:    orr w0, w10, w8
 ; GISEL-NEXT:    ret
 entry:
   %tmp1 = lshr i32 %X, 8
   %X15 = bitcast i32 %X to i32
   %tmp4 = shl i32 %X15, 8
   %tmp2 = and i32 %tmp1, 16711680
   %tmp5 = and i32 %tmp4, -16777216
   %tmp9 = and i32 %tmp1, 255

 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex1:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr x8, x0, #8
 ; GISEL-NEXT:    lsl x9, x0, #8
 ; GISEL-NEXT:    and x10, x8, #0xff000000000000
 ; GISEL-NEXT:    and x11, x9, #0xff00000000000000
+; GISEL-NEXT:    and x12, x8, #0xff00000000
+; GISEL-NEXT:    and x13, x9, #0xff0000000000
 ; GISEL-NEXT:    orr x10, x10, x11
-; GISEL-NEXT:    and x11, x8, #0xff00000000
-; GISEL-NEXT:    orr x10, x10, x11
-; GISEL-NEXT:    and x11, x9, #0xff0000000000
-; GISEL-NEXT:    orr x10, x10, x11
-; GISEL-NEXT:    and x11, x8, #0xff0000
-; GISEL-NEXT:    orr x10, x10, x11
-; GISEL-NEXT:    and x11, x9, #0xff000000
-; GISEL-NEXT:    orr x10, x10, x11
+; GISEL-NEXT:    orr x11, x12, x13
+; GISEL-NEXT:    and x12, x8, #0xff0000
+; GISEL-NEXT:    and x13, x9, #0xff000000
+; GISEL-NEXT:    orr x12, x12, x13
 ; GISEL-NEXT:    and x8, x8, #0xff
+; GISEL-NEXT:    orr x10, x10, x11
+; GISEL-NEXT:    orr x8, x12, x8
 ; GISEL-NEXT:    orr x8, x10, x8
 ; GISEL-NEXT:    and x9, x9, #0xff00
 ; GISEL-NEXT:    orr x0, x8, x9
 ; GISEL-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 8
   %1 = and i64 %0, 71776119061217280
   %2 = shl i64 %a, 8

 ; CHECK-NEXT:    bfi x8, x11, #24, #8
 ; CHECK-NEXT:    bfi x8, x0, #8, #8
 ; CHECK-NEXT:    mov x0, x8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex2:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr x8, x0, #8
-; GISEL-NEXT:    lsl x10, x0, #8
-; GISEL-NEXT:    and x9, x8, #0xff000000000000
+; GISEL-NEXT:    lsl x9, x0, #8
+; GISEL-NEXT:    and x10, x8, #0xff000000000000
 ; GISEL-NEXT:    and x11, x8, #0xff00000000
-; GISEL-NEXT:    orr x9, x9, x11
-; GISEL-NEXT:    and x11, x8, #0xff0000
-; GISEL-NEXT:    orr x9, x9, x11
+; GISEL-NEXT:    and x12, x8, #0xff0000
 ; GISEL-NEXT:    and x8, x8, #0xff
-; GISEL-NEXT:    orr x8, x9, x8
-; GISEL-NEXT:    and x9, x10, #0xff00000000000000
-; GISEL-NEXT:    orr x8, x8, x9
-; GISEL-NEXT:    and x9, x10, #0xff0000000000
-; GISEL-NEXT:    orr x8, x8, x9
-; GISEL-NEXT:    and x9, x10, #0xff000000
-; GISEL-NEXT:    orr x8, x8, x9
-; GISEL-NEXT:    and x9, x10, #0xff00
+; GISEL-NEXT:    orr x10, x10, x11
+; GISEL-NEXT:    orr x8, x12, x8
+; GISEL-NEXT:    and x11, x9, #0xff00000000000000
+; GISEL-NEXT:    and x12, x9, #0xff0000000000
+; GISEL-NEXT:    orr x11, x11, x12
+; GISEL-NEXT:    and x12, x9, #0xff000000
+; GISEL-NEXT:    orr x8, x10, x8
+; GISEL-NEXT:    orr x10, x11, x12
+; GISEL-NEXT:    orr x8, x8, x10
+; GISEL-NEXT:    and x9, x9, #0xff00
 ; GISEL-NEXT:    orr x0, x8, x9
 ; GISEL-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 8
   %1 = and i64 %0, 71776119061217280
   %2 = shl i64 %a, 8
   %3 = and i64 %0, 1095216660480
   %4 = or i64 %1, %3

 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex3:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr x8, x0, #8
 ; GISEL-NEXT:    lsl x9, x0, #8
 ; GISEL-NEXT:    and x10, x8, #0xff000000000000
 ; GISEL-NEXT:    and x11, x9, #0xff00000000000000
+; GISEL-NEXT:    and x12, x8, #0xff00000000
+; GISEL-NEXT:    and x13, x9, #0xff0000000000
 ; GISEL-NEXT:    orr x10, x11, x10
-; GISEL-NEXT:    and x11, x8, #0xff00000000
-; GISEL-NEXT:    orr x10, x11, x10
-; GISEL-NEXT:    and x11, x9, #0xff0000000000
-; GISEL-NEXT:    orr x10, x11, x10
-; GISEL-NEXT:    and x11, x8, #0xff0000
-; GISEL-NEXT:    orr x10, x11, x10
-; GISEL-NEXT:    and x11, x9, #0xff000000
-; GISEL-NEXT:    orr x10, x11, x10
+; GISEL-NEXT:    orr x11, x12, x13
+; GISEL-NEXT:    and x12, x8, #0xff0000
+; GISEL-NEXT:    and x13, x9, #0xff000000
+; GISEL-NEXT:    orr x12, x12, x13
 ; GISEL-NEXT:    and x8, x8, #0xff
-; GISEL-NEXT:    orr x8, x8, x10
+; GISEL-NEXT:    orr x10, x10, x11
+; GISEL-NEXT:    orr x8, x12, x8
+; GISEL-NEXT:    orr x8, x10, x8
 ; GISEL-NEXT:    and x9, x9, #0xff00
 ; GISEL-NEXT:    orr x0, x9, x8
 ; GISEL-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 8
   %1 = and i64 %0, 71776119061217280
   %2 = shl i64 %a, 8
   %3 = and i64 %2, -72057594037927936
entry:
   %6 = or i64 %4, %5
   ret i64 %6
 }
 
 define i64 @test_or_and_combine2(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: test_or_and_combine2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsr x8, x0, #8
-; CHECK-NEXT:    lsl x10, x0, #8
-; CHECK-NEXT:    and x9, x8, #0xff000000000000
+; CHECK-NEXT:    lsl x9, x0, #8
+; CHECK-NEXT:    and x10, x8, #0xff000000000000
+; CHECK-NEXT:    and x11, x9, #0xff00000000
 ; CHECK-NEXT:    and x8, x8, #0xff0000
-; CHECK-NEXT:    orr x9, x9, x10
-; CHECK-NEXT:    and x10, x10, #0xff00000000
-; CHECK-NEXT:    orr x9, x9, x10
+; CHECK-NEXT:    orr x9, x10, x9
+; CHECK-NEXT:    orr x8, x11, x8
 ; CHECK-NEXT:    orr x0, x9, x8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_or_and_combine2:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr x8, x0, #8
-; GISEL-NEXT:    lsl x10, x0, #8
-; GISEL-NEXT:    and x9, x8, #0xff000000000000
+; GISEL-NEXT:    lsl x9, x0, #8
+; GISEL-NEXT:    and x10, x8, #0xff000000000000
+; GISEL-NEXT:    and x11, x9, #0xff00000000
 ; GISEL-NEXT:    and x8, x8, #0xff0000
-; GISEL-NEXT:    orr x9, x9, x10
-; GISEL-NEXT:    and x10, x10, #0xff00000000
-; GISEL-NEXT:    orr x9, x9, x10
+; GISEL-NEXT:    orr x9, x10, x9
+; GISEL-NEXT:    orr x8, x11, x8
 ; GISEL-NEXT:    orr x0, x9, x8
 ; GISEL-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 8
   %1 = and i64 %0, 71776119061217280
   %2 = shl i64 %a, 8
   %3 = or i64 %1, %2
   %4 = and i64 %2, 1095216660480

llvm/test/CodeGen/AArch64/cmp-chains.ll

 ;
 ; GISEL-LABEL: cmp_and4:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmp w2, w3
 ; GISEL-NEXT:    cset w8, hi
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w9, lo
 ; GISEL-NEXT:    cmp w4, w5
-; GISEL-NEXT:    and w8, w8, w9
-; GISEL-NEXT:    cset w9, ne
+; GISEL-NEXT:    cset w10, ne
 ; GISEL-NEXT:    cmp w6, w7
+; GISEL-NEXT:    cset w11, eq
 ; GISEL-NEXT:    and w8, w8, w9
-; GISEL-NEXT:    cset w9, eq
+; GISEL-NEXT:    and w9, w10, w11
 ; GISEL-NEXT:    and w0, w8, w9
 ; GISEL-NEXT:    ret
   %9 = icmp ugt i32 %2, %3
   %10 = icmp ult i32 %0, %1
   %11 = select i1 %9, i1 %10, i1 false
   %12 = icmp ne i32 %4, %5
   %13 = select i1 %11, i1 %12, i1 false
   %14 = icmp eq i32 %6, %7

 ;
 ; GISEL-LABEL: cmp_or4:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    cmp w0, w1
 ; GISEL-NEXT:    cset w8, lo
 ; GISEL-NEXT:    cmp w2, w3
 ; GISEL-NEXT:    cset w9, hi
 ; GISEL-NEXT:    cmp w4, w5
-; GISEL-NEXT:    orr w8, w8, w9
-; GISEL-NEXT:    cset w9, ne
+; GISEL-NEXT:    cset w10, ne
 ; GISEL-NEXT:    cmp w6, w7
+; GISEL-NEXT:    cset w11, eq
 ; GISEL-NEXT:    orr w8, w8, w9
-; GISEL-NEXT:    cset w9, eq
+; GISEL-NEXT:    orr w9, w10, w11
 ; GISEL-NEXT:    orr w0, w8, w9
 ; GISEL-NEXT:    ret
   %9 = icmp ult i32 %0, %1
   %10 = icmp ugt i32 %2, %3
   %11 = select i1 %9, i1 true, i1 %10
   %12 = icmp ne i32 %4, %5
   %13 = select i1 %11, i1 true, i1 %12
   %14 = icmp eq i32 %6, %7

llvm/test/CodeGen/AArch64/reduce-and.ll

; GISEL-NEXT:    ret
   %and_result = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
   ret i8 %and_result
 }
 
 define i8 @test_redand_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: test_redand_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w10, w11, w10
+; CHECK-NEXT:    and w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v4i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]
 ; GISEL-NEXT:    fmov w8, s0
 ; GISEL-NEXT:    fmov w9, s1
 ; GISEL-NEXT:    fmov w10, s2
 ; GISEL-NEXT:    fmov w11, s3
 ; GISEL-NEXT:    and w8, w8, w9
 ; GISEL-NEXT:    and w9, w10, w11
 ; GISEL-NEXT:    and w0, w8, w9
 ; GISEL-NEXT:    ret
   %and_result = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)
   ret i8 %and_result
 }
 
 define i8 @test_redand_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: test_redand_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.b[1]
-; CHECK-NEXT:    umov w9, v0.b[0]
-; CHECK-NEXT:    umov w10, v0.b[2]
-; CHECK-NEXT:    umov w11, v0.b[3]
-; CHECK-NEXT:    umov w12, v0.b[4]
-; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w8, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[4]
+; CHECK-NEXT:    umov w10, v0.b[1]
+; CHECK-NEXT:    umov w11, v0.b[0]
+; CHECK-NEXT:    umov w12, v0.b[3]
+; CHECK-NEXT:    umov w13, v0.b[2]
+; CHECK-NEXT:    umov w14, v0.b[6]
+; CHECK-NEXT:    umov w15, v0.b[7]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[6]
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[7]
-; CHECK-NEXT:    and w8, w8, w11
-; CHECK-NEXT:    and w8, w8, w12
-; CHECK-NEXT:    and w8, w8, w13
-; CHECK-NEXT:    and w8, w8, w9
-; CHECK-NEXT:    and w0, w8, w10
+; CHECK-NEXT:    and w10, w11, w10
+; CHECK-NEXT:    and w11, w13, w12
+; CHECK-NEXT:    and w9, w10, w11
+; CHECK-NEXT:    and w8, w8, w14
+; CHECK-NEXT:    and w8, w9, w8
+; CHECK-NEXT:    and w0, w8, w15
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v8i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]
 ; GISEL-NEXT:    mov b3, v0.b[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    and w10, w10, w11
+; CHECK-NEXT:    and w11, w12, w13
 ; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    and w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    and w8, w8, w12
-; CHECK-NEXT:    and w8, w8, w9
+; CHECK-NEXT:    and w10, w11, w14
 ; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v16i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]

 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    and w10, w10, w11
+; CHECK-NEXT:    and w11, w12, w13
 ; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    and w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    and w8, w8, w12
-; CHECK-NEXT:    and w8, w8, w9
+; CHECK-NEXT:    and w10, w11, w14
 ; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v32i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
; GISEL-NEXT:    ret
   %and_result = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %a)
   ret i8 %and_result
 }
 
 define i16 @test_redand_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: test_redand_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w10, w11, w10
+; CHECK-NEXT:    and w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v4i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w9, w10, w11
+; CHECK-NEXT:    and w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v8i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]

 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w9, w10, w11
+; CHECK-NEXT:    and w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v16i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    and v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    and v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]

llvm/test/CodeGen/AArch64/reduce-or.ll

; GISEL-NEXT:    ret
   %or_result = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %a)
   ret i8 %or_result
 }
 
 define i8 @test_redor_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: test_redor_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w10, w11, w10
+; CHECK-NEXT:    orr w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v4i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]
 ; GISEL-NEXT:    fmov w8, s0
 ; GISEL-NEXT:    fmov w9, s1
 ; GISEL-NEXT:    fmov w10, s2
 ; GISEL-NEXT:    fmov w11, s3
 ; GISEL-NEXT:    orr w8, w8, w9
 ; GISEL-NEXT:    orr w9, w10, w11
 ; GISEL-NEXT:    orr w0, w8, w9
 ; GISEL-NEXT:    ret
   %or_result = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
   ret i8 %or_result
 }
 
 define i8 @test_redor_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: test_redor_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.b[1]
-; CHECK-NEXT:    umov w9, v0.b[0]
-; CHECK-NEXT:    umov w10, v0.b[2]
-; CHECK-NEXT:    umov w11, v0.b[3]
-; CHECK-NEXT:    umov w12, v0.b[4]
-; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w8, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[4]
+; CHECK-NEXT:    umov w10, v0.b[1]
+; CHECK-NEXT:    umov w11, v0.b[0]
+; CHECK-NEXT:    umov w12, v0.b[3]
+; CHECK-NEXT:    umov w13, v0.b[2]
+; CHECK-NEXT:    umov w14, v0.b[6]
+; CHECK-NEXT:    umov w15, v0.b[7]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[6]
-; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[7]
-; CHECK-NEXT:    orr w8, w8, w11
-; CHECK-NEXT:    orr w8, w8, w12
-; CHECK-NEXT:    orr w8, w8, w13
-; CHECK-NEXT:    orr w8, w8, w9
-; CHECK-NEXT:    orr w0, w8, w10
+; CHECK-NEXT:    orr w10, w11, w10
+; CHECK-NEXT:    orr w11, w13, w12
+; CHECK-NEXT:    orr w9, w10, w11
+; CHECK-NEXT:    orr w8, w8, w14
+; CHECK-NEXT:    orr w8, w9, w8
+; CHECK-NEXT:    orr w0, w8, w15
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v8i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]
 ; GISEL-NEXT:    mov b3, v0.b[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    orr w10, w10, w11
+; CHECK-NEXT:    orr w11, w12, w13
 ; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    orr w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    orr w8, w8, w12
-; CHECK-NEXT:    orr w8, w8, w9
+; CHECK-NEXT:    orr w10, w11, w14
 ; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v16i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]

 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    orr w10, w10, w11
+; CHECK-NEXT:    orr w11, w12, w13
 ; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    orr w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    orr w8, w8, w12
-; CHECK-NEXT:    orr w8, w8, w9
+; CHECK-NEXT:    orr w10, w11, w14
 ; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v32i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
; GISEL-NEXT:    ret
   %or_result = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %a)
   ret i8 %or_result
 }
 
 define i16 @test_redor_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: test_redor_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w10, w11, w10
+; CHECK-NEXT:    orr w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v4i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w9, w10, w11
+; CHECK-NEXT:    orr w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v8i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]

 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    orr w8, w8, w10
-; CHECK-NEXT:    orr w0, w8, w11
+; CHECK-NEXT:    orr w9, w10, w11
+; CHECK-NEXT:    orr w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redor_v16i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]

llvm/test/CodeGen/AArch64/reduce-xor.ll

; GISEL-NEXT:    ret
   %xor_result = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %a)
   ret i8 %xor_result
 }
 
 define i8 @test_redxor_v4i8(<4 x i8> %a) {
 ; CHECK-LABEL: test_redxor_v4i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w10, w11, w10
+; CHECK-NEXT:    eor w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v4i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]
 ; GISEL-NEXT:    fmov w8, s0
 ; GISEL-NEXT:    fmov w9, s1
 ; GISEL-NEXT:    fmov w10, s2
 ; GISEL-NEXT:    fmov w11, s3
 ; GISEL-NEXT:    eor w8, w8, w9
 ; GISEL-NEXT:    eor w9, w10, w11
 ; GISEL-NEXT:    eor w0, w8, w9
 ; GISEL-NEXT:    ret
   %xor_result = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a)
   ret i8 %xor_result
 }
 
 define i8 @test_redxor_v8i8(<8 x i8> %a) {
 ; CHECK-LABEL: test_redxor_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.b[1]
-; CHECK-NEXT:    umov w9, v0.b[0]
-; CHECK-NEXT:    umov w10, v0.b[2]
-; CHECK-NEXT:    umov w11, v0.b[3]
-; CHECK-NEXT:    umov w12, v0.b[4]
-; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w8, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[4]
+; CHECK-NEXT:    umov w10, v0.b[1]
+; CHECK-NEXT:    umov w11, v0.b[0]
+; CHECK-NEXT:    umov w12, v0.b[3]
+; CHECK-NEXT:    umov w13, v0.b[2]
+; CHECK-NEXT:    umov w14, v0.b[6]
+; CHECK-NEXT:    umov w15, v0.b[7]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[6]
-; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[7]
-; CHECK-NEXT:    eor w8, w8, w11
-; CHECK-NEXT:    eor w8, w8, w12
-; CHECK-NEXT:    eor w8, w8, w13
-; CHECK-NEXT:    eor w8, w8, w9
-; CHECK-NEXT:    eor w0, w8, w10
+; CHECK-NEXT:    eor w10, w11, w10
+; CHECK-NEXT:    eor w11, w13, w12
+; CHECK-NEXT:    eor w9, w10, w11
+; CHECK-NEXT:    eor w8, w8, w14
+; CHECK-NEXT:    eor w8, w9, w8
+; CHECK-NEXT:    eor w0, w8, w15
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v8i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]
 ; GISEL-NEXT:    mov b3, v0.b[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    eor w10, w10, w11
+; CHECK-NEXT:    eor w11, w12, w13
 ; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    eor w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    eor w8, w8, w12
-; CHECK-NEXT:    eor w8, w8, w9
+; CHECK-NEXT:    eor w10, w11, w14
 ; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v16i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
 ; GISEL-NEXT:    mov b2, v0.b[2]

 ; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.b[1]
 ; CHECK-NEXT:    umov w9, v0.b[0]
 ; CHECK-NEXT:    umov w10, v0.b[2]
 ; CHECK-NEXT:    umov w11, v0.b[3]
 ; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w13, v0.b[5]
+; CHECK-NEXT:    umov w14, v0.b[6]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
+; CHECK-NEXT:    umov w9, v0.b[7]
+; CHECK-NEXT:    eor w10, w10, w11
+; CHECK-NEXT:    eor w11, w12, w13
 ; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    eor w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    eor w8, w8, w12
-; CHECK-NEXT:    eor w8, w8, w9
+; CHECK-NEXT:    eor w10, w11, w14
 ; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v32i8:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    eor v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov b1, v0.b[1]
; GISEL-NEXT:    ret
   %xor_result = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %a)
   ret i8 %xor_result
 }
 
 define i16 @test_redxor_v4i16(<4 x i16> %a) {
 ; CHECK-LABEL: test_redxor_v4i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    umov w8, v0.h[1]
-; CHECK-NEXT:    umov w9, v0.h[0]
-; CHECK-NEXT:    umov w10, v0.h[2]
-; CHECK-NEXT:    umov w11, v0.h[3]
+; CHECK-NEXT:    umov w8, v0.h[3]
+; CHECK-NEXT:    umov w9, v0.h[2]
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w11, v0.h[0]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w10, w11, w10
+; CHECK-NEXT:    eor w0, w10, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v4i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]
 ; GISEL-NEXT:    mov h3, v0.h[3]

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w9, w10, w11
+; CHECK-NEXT:    eor w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v8i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]
 ; GISEL-NEXT:    mov h2, v0.h[2]

 ; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    umov w9, v0.h[0]
 ; CHECK-NEXT:    umov w10, v0.h[2]
 ; CHECK-NEXT:    umov w11, v0.h[3]
 ; CHECK-NEXT:    eor w8, w9, w8
-; CHECK-NEXT:    eor w8, w8, w10
-; CHECK-NEXT:    eor w0, w8, w11
+; CHECK-NEXT:    eor w9, w10, w11
+; CHECK-NEXT:    eor w0, w8, w9
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redxor_v16i16:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    eor v0.16b, v0.16b, v1.16b
 ; GISEL-NEXT:    mov d1, v0.d[1]
 ; GISEL-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; GISEL-NEXT:    mov h1, v0.h[1]

llvm/test/CodeGen/AArch64/swift-return.ll

entry:
   ret i16 %conv
 }
 
 declare swiftcc { i16, i8 } @gen(i32)
 
 ; CHECK-LABEL: test2
 ; CHECK:  bl      _gen2
 ; CHECK:  add     [[TMP:x.*]], x0, x1
-; CHECK:  add     [[TMP]], [[TMP]], x2
-; CHECK:  add     [[TMP]], [[TMP]], x3
+; CHECK:  add     [[TMP2:x.*]], x2, x3
+; CHECK:  add     [[TMP]], [[TMP]], [[TMP2]]
 ; CHECK:  add     x0, [[TMP]], x4
 ; CHECK-O0-LABEL: test2
 ; CHECK-O0:  bl      _gen2
 ; CHECK-O0:  add     [[TMP:x.*]], x0, x1
 ; CHECK-O0:  add     [[TMP]], [[TMP]], x2
 ; CHECK-O0:  add     [[TMP]], [[TMP]], x3
 ; CHECK-O0:  add     x0, [[TMP]], x4
 
define swiftcc { i64, i64, i64, i64, i64 } @gen2(i64 %key) {
   %Z3 = insertvalue { i64, i64, i64, i64, i64 } %Z2, i64 %key, 3
   %Z4 = insertvalue { i64, i64, i64, i64, i64 } %Z3, i64 %key, 4
   ret { i64, i64, i64, i64, i64 } %Z4
 }
 
 ; CHECK-LABEL: test3
 ; CHECK: bl      _gen3
 ; CHECK: add             [[TMP:w.*]], w0, w1
-; CHECK: add             [[TMP]], [[TMP]], w2
-; CHECK: add             w0, [[TMP]], w3
+; CHECK: add             [[TMP2:w.*]], w2, w3
+; CHECK: add             w0, [[TMP]], [[TMP2]]
 ; CHECK-O0-LABEL: test3
 ; CHECK-O0: bl      _gen3
 ; CHECK-O0: add             [[TMP:w.*]], w0, w1
 ; CHECK-O0: add             [[TMP]], [[TMP]], w2
 ; CHECK-O0: add             w0, [[TMP]], w3
 define i32 @test3(i32) {
 entry:
   %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)

 declare swiftcc { double, double, double, double } @gen5()
 
 ; CHECK-LABEL: test6
 ; CHECK:   bl      _gen6
 ; CHECK-DAG:   fadd    d0, d0, d1
 ; CHECK-DAG:   fadd    d0, d0, d2
 ; CHECK-DAG:   fadd    d0, d0, d3
 ; CHECK-DAG:   add     [[TMP:w.*]], w0, w1
-; CHECK-DAG:   add     [[TMP]], [[TMP]], w2
-; CHECK-DAG:   add     w0, [[TMP]], w3
+; CHECK-DAG:   add     [[TMP2:w.*]], w2, w3
+; CHECK-DAG:   add     w0, [[TMP]], [[TMP2]]
 ; CHECK-O0-LABEL: test6
 ; CHECK-O0:   bl      _gen6
 ; CHECK-O0-DAG:   fadd    d0, d0, d1
 ; CHECK-O0-DAG:   fadd    d0, d0, d2
 ; CHECK-O0-DAG:   fadd    d0, d0, d3
 ; CHECK-O0-DAG:   add     [[TMP:w.*]], w0, w1
 ; CHECK-O0-DAG:   add     [[TMP]], [[TMP]], w2
 ; CHECK-O0-DAG:   add     w0, [[TMP]], w3

llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

; CHECK-NEXT:    ret
   %b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
   ret i8 %b
 }
 
 define i8 @test_v9i8(<9 x i8> %a) nounwind {
 ; CHECK-LABEL: test_v9i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-1
-; CHECK-NEXT:    umov w12, v0.b[4]
+; CHECK-NEXT:    umov w9, v0.b[5]
 ; CHECK-NEXT:    mov v1.16b, v0.16b
+; CHECK-NEXT:    umov w10, v0.b[6]
+; CHECK-NEXT:    umov w15, v0.b[7]
 ; CHECK-NEXT:    mov v1.b[9], w8
 ; CHECK-NEXT:    mov v1.b[10], w8
 ; CHECK-NEXT:    mov v1.b[11], w8
 ; CHECK-NEXT:    mov v1.b[13], w8
+; CHECK-NEXT:    umov w8, v0.b[4]
 ; CHECK-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT:    and v1.8b, v0.8b, v1.8b
-; CHECK-NEXT:    umov w8, v1.b[1]
-; CHECK-NEXT:    umov w9, v1.b[0]
-; CHECK-NEXT:    umov w10, v1.b[2]
-; CHECK-NEXT:    umov w11, v1.b[3]
-; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    umov w9, v0.b[5]
-; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    umov w10, v0.b[6]
-; CHECK-NEXT:    and w8, w8, w11
-; CHECK-NEXT:    umov w11, v0.b[7]
-; CHECK-NEXT:    and w8, w8, w12
 ; CHECK-NEXT:    and w8, w8, w9
 ; CHECK-NEXT:    and w8, w8, w10
-; CHECK-NEXT:    and w0, w8, w11
+; CHECK-NEXT:    and w8, w8, w15
+; CHECK-NEXT:    and v1.8b, v0.8b, v1.8b
+; CHECK-NEXT:    umov w11, v1.b[1]
+; CHECK-NEXT:    umov w12, v1.b[0]
+; CHECK-NEXT:    umov w13, v1.b[2]
+; CHECK-NEXT:    umov w14, v1.b[3]
+; CHECK-NEXT:    and w9, w12, w11
+; CHECK-NEXT:    and w11, w13, w14
+; CHECK-NEXT:    and w9, w9, w11
+; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
   ret i8 %b
 }
 
 define i32 @test_v3i32(<3 x i32> %a) nounwind {
 ; CHECK-LABEL: test_v3i32:
 ; CHECK:       // %bb.0: