[RISCV] Verify consistency of a couple TSFlags related to vector operands

[reames]

Summary

Mostly a starting point for discussion. I think it makes sense to have verification rules for these flags; mostly to make it easier to figure out their function. Do others agree?

If so, any other proposed rules we'd like to enforce? I picked these two somewhat arbitrarily based on code I was looking at today.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1224

SEW -> VL

[liaolucy]

Title [RISCV\ -> [RISCV]

[frasercrmck]

I think some level of verification makes sense. I half worry that some instructions may not behave so nicely and we'll have to add exceptions to our rules, but none come to mind right now.

[reames]

In D133810#3802256, @frasercrmck wrote:

I think some level of verification makes sense. I half worry that some instructions may not behave so nicely and we'll have to add exceptions to our rules, but none come to mind right now.

This doesn't sound like a bad outcome to me. Finding and documenting the hidden invariants is a major reason for this change. :)

[reames]

Rebase

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

#define CASE_OPERAND_UIMM(NUM)                                                 \
   }
 
   const uint64_t TSFlags = Desc.TSFlags;
   if (RISCVII::hasMergeOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getMergeOpNum(Desc);
     if (MI.findTiedOperandIdx(0) != OpIdx) {
       ErrInfo = "Merge op improperly tied";
       return false;
     }
   }
   if (RISCVII::hasVLOp(TSFlags)) {
     const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
     if (!Op.isImm() && !Op.isReg())  {
       ErrInfo = "Invalid operand type for VL operand";
       return false;
     }
     if (Op.isReg() && Op.getReg() != RISCV::NoRegister) {
       const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
       auto *RC = MRI.getRegClass(Op.getReg());
       if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
         ErrInfo = "Invalid register class for VL operand";
         return false;
       }
     }
+    if (!RISCVII::hasSEWOp(TSFlags)) {
+      ErrInfo = "VL operand w/o SEW operand?";
+      return false;
+    }
   }
   if (RISCVII::hasSEWOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
     uint64_t Log2SEW = MI.getOperand(OpIdx).getImm();
     if (Log2SEW > 31) {
       ErrInfo = "Unexpected SEW value";
       return false;
     }
     unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
     if (!RISCVVType::isValidSEW(SEW)) {
       ErrInfo = "Unexpected SEW value";
       return false;
     }
   }
   if (RISCVII::hasVecPolicyOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getVecPolicyOpNum(Desc);
     uint64_t Policy = MI.getOperand(OpIdx).getImm();
     if (Policy > (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) {
       ErrInfo = "Invalid Policy Value";
       return false;
     }
+    if (!RISCVII::hasVLOp(TSFlags)) {
+      ErrInfo = "policy operand w/o VL operand?";
+      return false;
+    }
   }
 
   return true;
 }
 
 // Return true if get the base operand, byte offset of an instruction and the
 // memory width. Width is the size of memory that is being loaded/stored.
 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(