[RISCV] Verify consistency of a couple TSFlags related to vector operands

[reames]

Summary

Mostly a starting point for discussion. I think it makes sense to have verification rules for these flags; mostly to make it easier to figure out their function. Do others agree?

If so, any other proposed rules we'd like to enforce? I picked these two somewhat arbitrarily based on code I was looking at today.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1229

SEW -> VL

[liaolucy]

Title [RISCV\ -> [RISCV]

[frasercrmck]

I think some level of verification makes sense. I half worry that some instructions may not behave so nicely and we'll have to add exceptions to our rules, but none come to mind right now.

[reames]

In D133810#3802256, @frasercrmck wrote:

I think some level of verification makes sense. I half worry that some instructions may not behave so nicely and we'll have to add exceptions to our rules, but none come to mind right now.

This doesn't sound like a bad outcome to me. Finding and documenting the hidden invariants is a major reason for this change. :)

[reames]

Rebase

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

break;
         if (!Ok) {
           ErrInfo = "Invalid immediate";
           return false;
         }
       }
     }
   }
 
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  if (RISCVII::hasVLOp(TSFlags) && !RISCVII::hasSEWOp(TSFlags)) {
+    ErrInfo = "VL operand w/o SEW operand?";
+    return false;
+  }
+  if (RISCVII::hasVecPolicyOp(TSFlags) && !RISCVII::hasVLOp(TSFlags)) {
+    ErrInfo = "policy operand w/o SEW operand?";
+    return false;
+  }
   return true;
 }
 
 // Return true if get the base operand, byte offset of an instruction and the
 // memory width. Width is the size of memory that is being loaded/stored.
 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
     unsigned &Width, const TargetRegisterInfo *TRI) const {