[PowerPC] XCOFF exception section support on the direct assembler path and exception language and reason code lowering from trap intrinsics

[pscoro]

Summary

This feature implements support for making entries in the exception section on XCOFF on the direct assembly path using the ".except" pseudo-op. It also provides functionality to lower entries (comprised of language and reason codes) into the exception section through the use of annotation metadata attached to llvm.ppc.trap/trapd/tw/tdw intrinsics. Integrated assembler support will be provided in another review. https://reviews.llvm.org/D133030 needs to merge first for LIT tests

[shchenz]

Add more reviewers as we add a target hook TargetLowering::LowerTargetIntrinsic in the target independent part while building target intrinsic.

[RKSimon]

llvm/include/llvm/CodeGen/TargetLowering.h

4576

Please document the instruction and its arguments. Is Op necessary - should it be returned instead? Use SmallVectorImpl<SDValue>?

llvm/include/llvm/MC/MCStreamer.h

639

is it really necessary to add const to the integer args?

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

4868

Do you need Result? Should this be returning anything?

[pscoro]

Added integrated assembly support

[pscoro]

formatting

[pscoro]

small fix to lit test

[pscoro]

whitespace fix

[shchenz]

You should not add the integrated-as mode change to the existing non integrated-as change.
Better to post two patches for these two functionalities.

[RKSimon]

In D132146#3785383, @shchenz wrote:

You should not add the integrated-as mode change to the existing non integrated-as change.
Better to post two patches for these two functionalities.

+1 Please split these

[pscoro]

In D132146#3785383, @shchenz wrote:

You should not add the integrated-as mode change to the existing non integrated-as change.
Better to post two patches for these two functionalities.

In D132146#3785915, @RKSimon wrote:

In D132146#3785383, @shchenz wrote:

You should not add the integrated-as mode change to the existing non integrated-as change.
Better to post two patches for these two functionalities.

+1 Please split these

How would you recommend splitting these up? Beside the lit tests there is only one file (MCAsmStreamer) that has code specific to the direct assembly path, and only MCXCOFFStreamer and XCOFFObjectWriter are specific to the integrated-as path. The rest is shared code. My assumption was that if there is this much shared code it would be safer to make one review because the second review can't merge until this first one has and for a given feature, the full body of code that is needed for it is present in its review. That being said, do you prefer if I just move MCXCOFFStreamer, XCOFFObjectWriter and the object lit tests to a separate review?

[pscoro]

Split review

[pscoro]

Added temporary llvm_unreachable for integrated assembler path

[shchenz]

Thanks, looks almost good to me. Some minor comments.

llvm/include/llvm/MC/MCObjectWriter.h

108

This seems not belonging to this patch?

llvm/lib/MC/MCAsmStreamer.cpp

949

format

llvm/lib/MC/MCStreamer.cpp

1193

Please use clang-format to reformat all the changes. The format here seems not right.

1197

report_fatal_error seems like a better choice. llvm_unreachable may not stop the program in some configurations.

llvm/lib/MC/MCXCOFFStreamer.cpp

89

report_fatal_error

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-64bit.ll

12

This seems not right.

You already added RUN line for obj file type. You can just check: (can not redirect stderr to /dev/null)

: OBJ: LLVM ERROR: emitXCOFFExceptDirective not yet supported for integrated assembler path.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations.ll

12

Ditto. add a new runline for obj file type and check the error messages.

[pscoro]

fixes

[pscoro]

changes to LowerTargetIntrinsic

[shchenz]

llvm/lib/MC/MCStreamer.cpp

1199

nit: format

llvm/lib/MC/MCXCOFFStreamer.cpp

89

nit: a space after "integrated" and reformat please

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-64bit.ll

2

is the utils/update_llc_test_checks.py able to handle not --crash llc RUN line? I tested this, seems it is recognized as WARNING: Skipping non-llc RUN line: not --crash llc. If so, maybe we should delete this line as we are manually changing this file?

12

nit: space between integrated and assembler

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations.ll

2

ditto.

3

Seems like we are testing 32 bit targets in this file? If so, we should use 32 bit triple, like powerpc-unknown-linux-gnu powerpc-unknown-aix

14

nit: space between integrated and assembler

[pscoro]

addressing nits

[pscoro]

llvm/lib/MC/MCXCOFFStreamer.cpp

89

ran clang-format after adding the space, no formatting was performed

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations.ll

3

powerpc-unknown-aix already existed, I added powerpc-unknown-linux-gnu, no changes to assembly generated.

[shchenz]

llvm/lib/MC/MCXCOFFStreamer.cpp

89

Nit: Seems for a long string, the usual way is to put the space at the end of first line, instead of at the start of the second line. Need format here if the space is put at the end of integrated

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations.ll

3

hmm, there are still some lines testing 64 bit targets, like the first/fourth/fifth RUN lines.

[pscoro]

changed lit test file names

[shchenz]

LGTM. Thanks for your patience.

[RKSimon]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16250

This is always SDvalue()? If you're never going to create a node and just collect operands, I'd suggest you don't call this 'LowerTargetIntrinsic' and replace it with something more suitable (collectTargetIntrinsicOperands?)

[pscoro]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16250

The idea was to keep the hook somewhat open ended. This particular intrinsic does not require anything besides operand collection but in general another target intrinsic may require additional custom lowering steps. Since its unavoidable that this hook is called for every target intrinsic, shouldn't the hook be general enough that additional intrinsic cases can be added to it later? Let me know what you think.

[RKSimon]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16250

I agree, but its caller doesn't use the return value at all.

[pscoro]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16250

Oh I see, the result gets overwritten anyway. In this case I suppose collectTargetIntrinsicOperands is the simplest solution. Will make the change shortly.

[pscoro]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16250

Also since the result is never used I'm assuming I should revert this function back to returning void?

[pscoro]

changed LowerTargetIntrinsic to CollectTargetIntrinsicOperands

[RKSimon]

Thanks, LGTM

[pscoro]

@shchenz I do not have commit privileges yet. If there are no further revision requests, could you commit this when you get the chance? Thanks

[shchenz]

@shchenz I do not have commit privileges yet. If there are no further revision requests, could you commit this when you get the chance? Thanks

Sure. Will commit this soon.

llvm/include/llvm/BinaryFormat/XCOFF.h

 constexpr size_t AuxFileHeaderSize32 = 72;
 constexpr size_t AuxFileHeaderSize64 = 110;
 constexpr size_t AuxFileHeaderSizeShort = 28;
 constexpr size_t SectionHeaderSize32 = 40;
 constexpr size_t SectionHeaderSize64 = 72;
 constexpr size_t SymbolTableEntrySize = 18;
 constexpr size_t RelocationSerializationSize32 = 10;
 constexpr size_t RelocationSerializationSize64 = 14;
+constexpr size_t ExceptionSectionEntrySize32 = 6;
+constexpr size_t ExceptionSectionEntrySize64 = 10;
 constexpr uint16_t RelocOverflow = 65535;
 constexpr uint8_t AllocRegNo = 31;
 
 enum ReservedSectionNum : int16_t { N_DEBUG = -2, N_ABS = -1, N_UNDEF = 0 };
 
 enum MagicNumber : uint16_t { XCOFF32 = 0x01DF, XCOFF64 = 0x01F7 };
 
 // This field only exists in the XCOFF64 definition.

llvm/include/llvm/CodeGen/TargetLowering.h

virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                             SelectionDAG &DAG) const;
 
   // Lower custom output constraints. If invalid, return SDValue().
   virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
                                               const SDLoc &DL,
                                               const AsmOperandInfo &OpInfo,
                                               SelectionDAG &DAG) const;
 
+  // Lower target intrinsic instruction.
+  virtual void LowerTargetIntrinsic(const CallInst &I, SDValue &Op,
+                                    SmallVector<SDValue, 8> &Ops,
+                                    SelectionDAG &DAG) const;
+
   //===--------------------------------------------------------------------===//
   // Div utility functions
   //
   SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                     SmallVectorImpl<SDNode *> &Created) const;
   SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                     SmallVectorImpl<SDNode *> &Created) const;
 

llvm/include/llvm/MC/MCObjectWriter.h

 //===- llvm/MC/MCObjectWriter.h - Object File Writer Interface --*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCOBJECTWRITER_H
public:
   bool getEmitAddrsigSection() { return EmitAddrsigSection; }
 
   /// Record the given symbol in the address-significance table to be written
   /// diring writeObject().
   void addAddrsigSymbol(const MCSymbol *Sym) { AddrsigSyms.push_back(Sym); }
 
   std::vector<const MCSymbol *> &getAddrsigSyms() { return AddrsigSyms; }
 
+  virtual void addExceptionEntry(const MCSymbol *Symbol, MCSymbol *Trap,
+                                 unsigned LanguageCode, unsigned ReasonCode,
+                                 unsigned FunctionSize, bool hasDebug) {}
+
   /// Write the object file and returns the number of bytes written.
   ///
   /// This routine is called by the assembler after layout and relaxation is
   /// complete, fixups have been evaluated and applied, and relocations
   /// generated.
   virtual uint64_t writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) = 0;
 
   /// @}

llvm/include/llvm/MC/MCStreamer.h

public:
   /// undesirable name.
   ///
   /// \param Name - The name used internally in the assembly for references to
   /// the symbol.
   /// \param Rename - The value to which the Name parameter is
   /// changed at the end of assembly.
   virtual void emitXCOFFRenameDirective(const MCSymbol *Name, StringRef Rename);
 
+  /// Emit an XCOFF .except directive which adds information about
+  /// a trap instruction to the object file exception section
+  ///
+  /// \param Symbol - The function containing the trap.
+  /// \param Lang - The language code for the exception entry.
+  /// \param Reason - The reason code for the exception entry.
+  virtual void emitXCOFFExceptDirective(const MCSymbol *Symbol, MCSymbol *Trap,
+                                        unsigned Lang, unsigned Reason,
+                                        unsigned FunctionSize, bool hasDebug);
+
   /// Emit a XCOFF .ref directive which creates R_REF type entry in the
   /// relocation table for one or more symbols.
   ///
   /// \param Sym - The symbol on the .ref directive.
   virtual void emitXCOFFRefDirective(StringRef Sym);
 
   /// Emit an ELF .size directive.
   ///

llvm/include/llvm/MC/MCXCOFFStreamer.h

 //===- MCXCOFFObjectStreamer.h - MCStreamer XCOFF Object File Interface ---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCXCOFFSTREAMER_H
void emitXCOFFRefDirective(StringRef Name) override {
     report_fatal_error("emitXCOFFRefDirective is not implemented yet on object"
                        "generation path");
   }
   void emitXCOFFRenameDirective(const MCSymbol *Name,
                                 StringRef Rename) override {
     report_fatal_error("emitXCOFFRenameDirective is not implemented yet on "
                        "object generation path");
   }
+  void emitXCOFFExceptDirective(const MCSymbol *Symbol, MCSymbol *Trap,
+                                unsigned Lang, unsigned Reason,
+                                unsigned FunctionSize, bool hasDebug) override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCXCOFFSTREAMER_H

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
   // Propagate fast-math-flags from IR to node(s).
   SDNodeFlags Flags;
   if (auto *FPMO = dyn_cast<FPMathOperator>(&I))
     Flags.copyFMF(*FPMO);
   SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
 
   // Create the node.
   SDValue Result;
+  TLI.LowerTargetIntrinsic(I, Result, Ops, DAG);
   if (IsTgtIntrinsic) {
     // This is target intrinsic that touches memory
     Result =
         DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT,
                                 MachinePointerInfo(Info.ptrVal, Info.offset),
                                 Info.align, Info.flags, Info.size,
                                 I.getAAMetadata());
   } else if (!HasChain) {

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

while (true) {
       }
       return;
     }
     break;
   }
   }
 }
 
+void TargetLowering::LowerTargetIntrinsic(const CallInst &I, SDValue &Op,
+                                          SmallVector<SDValue, 8> &Ops,
+                                          SelectionDAG &DAG) const {
+  return;
+}
+
 std::pair<unsigned, const TargetRegisterClass *>
 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
                                              StringRef Constraint,
                                              MVT VT) const {
   if (Constraint.empty() || Constraint[0] != '{')
     return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
   assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?");
 

llvm/lib/MC/MCAsmStreamer.cpp

public:
   void emitXCOFFSymbolLinkageWithVisibility(MCSymbol *Symbol,
                                             MCSymbolAttr Linakge,
                                             MCSymbolAttr Visibility) override;
   void emitXCOFFRenameDirective(const MCSymbol *Name,
                                 StringRef Rename) override;
 
   void emitXCOFFRefDirective(StringRef Name) override;
 
+  void emitXCOFFExceptDirective(const MCSymbol *Symbol, MCSymbol *Trap,
+                                unsigned Lang, unsigned Reason,
+                                unsigned FunctionSize, bool hasDebug) override;
+
   void emitELFSize(MCSymbol *Symbol, const MCExpr *Value) override;
   void emitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
                         unsigned ByteAlignment) override;
 
   /// Emit a local common (.lcomm) symbol.
   ///
   /// @param Symbol - The common symbol to emit.
   /// @param Size - The size of the common symbol.
void MCAsmStreamer::emitXCOFFRenameDirective(const MCSymbol *Name,
   EmitEOL();
 }
 
 void MCAsmStreamer::emitXCOFFRefDirective(StringRef Name) {
   OS << "\t.ref " << Name;
   EmitEOL();
 }
 
+void MCAsmStreamer::emitXCOFFExceptDirective(const MCSymbol *Symbol,
+                             MCSymbol *Trap, unsigned Lang, unsigned Reason, 
+                             unsigned FunctionSize, bool hasDebug) {
+  OS << "\t.except\t";
+  Symbol->print(OS, MAI);
+  OS << ", " << Lang << ", " << Reason;
+  EmitEOL();
+}
+
 void MCAsmStreamer::emitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
   assert(MAI->hasDotTypeDotSizeDirective());
   OS << "\t.size\t";
   Symbol->print(OS, MAI);
   OS << ", ";
   Value->print(OS, MAI);
   EmitEOL();
 }

llvm/lib/MC/MCStreamer.cpp

void MCStreamer::emitXCOFFRenameDirective(const MCSymbol *Name,
   llvm_unreachable("emitXCOFFRenameDirective is only supported on "
                    "XCOFF targets");
 }
 
 void MCStreamer::emitXCOFFRefDirective(StringRef Name) {
   llvm_unreachable("emitXCOFFRefDirective is only supported on XCOFF targets");
 }
 
+void MCStreamer::emitXCOFFExceptDirective(const MCSymbol *Symbol,
+                          MCSymbol *Trap, unsigned Lang, unsigned Reason,
+                          unsigned FunctionSize, bool hasDebug) {
+  llvm_unreachable("emitXCOFFExceptDirective is only supported on "
+                   "XCOFF targets");
+}
+
 void MCStreamer::emitELFSize(MCSymbol *Symbol, const MCExpr *Value) {}
 void MCStreamer::emitELFSymverDirective(const MCSymbol *OriginalSym,
                                         StringRef Name, bool KeepOriginalSym) {}
 void MCStreamer::emitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
                                        unsigned ByteAlignment) {}
 void MCStreamer::emitTBSSSymbol(MCSection *Section, MCSymbol *Symbol,
                                 uint64_t Size, unsigned ByteAlignment) {}
 void MCStreamer::changeSection(MCSection *, const MCExpr *) {}

llvm/lib/MC/MCXCOFFStreamer.cpp

 //===- lib/MC/MCXCOFFStreamer.cpp - XCOFF Object Output -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file assembles .s files and emits XCOFF .o object files.
void MCXCOFFStreamer::emitXCOFFSymbolLinkageWithVisibility(
 
   // When the caller passes `MCSA_Invalid` for the visibility, do not emit one.
   if (Visibility == MCSA_Invalid)
     return;
 
   emitSymbolAttribute(Symbol, Visibility);
 }
 
+void MCXCOFFStreamer::emitXCOFFExceptDirective(const MCSymbol *Symbol,
+                                               MCSymbol *Trap, unsigned Lang,
+                                               unsigned Reason,
+                                               unsigned FunctionSize,
+                                               bool hasDebug) {
+  getAssembler().getWriter().addExceptionEntry(Symbol, Trap, Lang, Reason,
+                                               FunctionSize, hasDebug);
+}
+
 void MCXCOFFStreamer::emitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
                                        unsigned ByteAlignment) {
   getAssembler().registerSymbol(*Symbol);
   Symbol->setExternal(cast<MCSymbolXCOFF>(Symbol)->getStorageClass() !=
                       XCOFF::C_HIDEXT);
   Symbol->setCommon(Size, ByteAlignment);
 
   // Default csect align is 4, but common symbols have explicit alignment values

llvm/lib/MC/XCOFFObjectWriter.cpp

DwarfSectionEntry(StringRef N, int32_t Flags,
     memcpy(Name, N.data(), N.size());
   }
 
   DwarfSectionEntry(DwarfSectionEntry &&s) = default;
 
   virtual ~DwarfSectionEntry() = default;
 };
 
+struct ExceptionTableEntry {
+  MCSymbol *Trap;
+  unsigned TrapAddress;
+  unsigned Lang;
+  unsigned Reason;
+
+  ExceptionTableEntry(MCSymbol *Trap, unsigned Lang, unsigned Reason) :
+                      Trap(Trap), Lang(Lang), Reason(Reason) {}
+};
+
+struct ExceptionInfo {
+  const MCSymbol *Symbol;
+  unsigned FunctionSize;
+  std::vector<ExceptionTableEntry> Entries;
+};
+
+struct ExceptionSectionEntry : public SectionEntry {
+  std::vector<ExceptionInfo> ExceptionTable;
+  bool isDebugEnabled;
+
+  ExceptionSectionEntry(StringRef N, int32_t Flags) :
+                        SectionEntry(N, Flags | XCOFF::STYP_EXCEPT) {
+    memcpy(Name, N.data(), N.size());
+  }
+
+  ExceptionSectionEntry(ExceptionSectionEntry &&s) = default;
+
+  virtual ~ExceptionSectionEntry() = default;
+};
+
 class XCOFFObjectWriter : public MCObjectWriter {
 
   uint32_t SymbolTableEntryCount = 0;
   uint64_t SymbolTableOffset = 0;
   uint16_t SectionCount = 0;
   uint64_t RelocationEntryOffset = 0;
   std::vector<std::pair<std::string, size_t>> FileNames;
   bool HasVisibility = false;
class XCOFFObjectWriter : public MCObjectWriter {
 
   // All the XCOFF sections, in the order they will appear in the section header
   // table.
   std::array<CsectSectionEntry *const, 5> Sections{
       {&Text, &Data, &BSS, &TData, &TBSS}};
 
   std::vector<DwarfSectionEntry> DwarfSections;
 
+  ExceptionSectionEntry ExceptionSection;
+
   CsectGroup &getCsectGroup(const MCSectionXCOFF *MCSec);
 
   void reset() override;
 
   void executePostLayoutBinding(MCAssembler &, const MCAsmLayout &) override;
 
   void recordRelocation(MCAssembler &, const MCAsmLayout &, const MCFragment *,
                         const MCFixup &, MCValue, uint64_t &) override;
class XCOFFObjectWriter : public MCObjectWriter {
   void writeSectionForControlSectionEntry(const MCAssembler &Asm,
                                           const MCAsmLayout &Layout,
                                           const CsectSectionEntry &CsectEntry,
                                           uint64_t &CurrentAddressLocation);
   void writeSectionForDwarfSectionEntry(const MCAssembler &Asm,
                                         const MCAsmLayout &Layout,
                                         const DwarfSectionEntry &DwarfEntry,
                                         uint64_t &CurrentAddressLocation);
+  void writeSectionForExceptionSectionEntry(const MCAssembler &Asm,
+                                const MCAsmLayout &Layout,
+                                ExceptionSectionEntry &ExceptionEntry,
+                                uint64_t &CurrentAddressLocation);
   void writeSymbolTable(const MCAsmLayout &Layout);
   void writeSymbolAuxDwarfEntry(uint64_t LengthOfSectionPortion,
                                 uint64_t NumberOfRelocEnt = 0);
   void writeSymbolAuxCsectEntry(uint64_t SectionOrLength,
                                 uint8_t SymbolAlignmentAndType,
                                 uint8_t StorageMappingClass);
+  void writeSymbolAuxFunctionEntry(uint32_t EntryOffset, 
+                                   uint32_t FunctionSize,
+                                   uint64_t LineNumberPointer, 
+                                   uint32_t EndIndex);
+  void writeSymbolAuxExceptionEntry(uint64_t EntryOffset,
+                                    uint32_t FunctionSize, uint32_t EndIndex);
   void writeSymbolEntry(StringRef SymbolName, uint64_t Value,
                         int16_t SectionNumber, uint16_t SymbolType,
                         uint8_t StorageClass, uint8_t NumberOfAuxEntries = 1);
   void writeRelocations();
   void writeRelocation(XCOFFRelocation Reloc, const XCOFFSection &Section);
 
   // Called after all the csects and symbols have been processed by
   // `executePostLayoutBinding`, this function handles building up the majority
   // of the structures in the object file representation. Namely:
   // *) Calculates physical/virtual addresses, raw-pointer offsets, and section
   //    sizes.
   // *) Assigns symbol table indices.
   // *) Builds up the section header table by adding any non-empty sections to
   //    `Sections`.
   void assignAddressesAndIndices(const MCAsmLayout &);
   void finalizeSectionInfo();
+  void addExceptionEntry(const MCSymbol *Symbol, MCSymbol *Trap,
+                         unsigned LanguageCode, unsigned ReasonCode,
+                         unsigned FunctionSize, bool hasDebug) override;
+
+  // TODO aux header support not implemented.
+  bool needsAuxiliaryHeader() const { return false; }
+
+  bool hasExceptionSection() { return (bool) getExceptionSectionSize(); }
+  unsigned getExceptionSectionSize();
+  unsigned getExceptionOffset(const MCSymbol *Symbol);
 
   size_t auxiliaryHeaderSize() const {
     // 64-bit object files have no auxiliary header.
     return HasVisibility && !is64Bit() ? XCOFF::AuxFileHeaderSizeShort : 0;
   }
 
 public:
   XCOFFObjectWriter(std::unique_ptr<MCXCOFFObjectTargetWriter> MOTW,
: W(OS, support::big), TargetObjectWriter(std::move(MOTW)),
            CsectGroups{&ProgramCodeCsects, &ReadOnlyCsects}),
       Data(".data", XCOFF::STYP_DATA, /* IsVirtual */ false,
            CsectGroups{&DataCsects, &FuncDSCsects, &TOCCsects}),
       BSS(".bss", XCOFF::STYP_BSS, /* IsVirtual */ true,
           CsectGroups{&BSSCsects}),
       TData(".tdata", XCOFF::STYP_TDATA, /* IsVirtual */ false,
             CsectGroups{&TDataCsects}),
       TBSS(".tbss", XCOFF::STYP_TBSS, /* IsVirtual */ true,
-           CsectGroups{&TBSSCsects}) {}
+           CsectGroups{&TBSSCsects}),
+      ExceptionSection(".except", XCOFF::STYP_EXCEPT) {}
 
 void XCOFFObjectWriter::reset() {
   // Clear the mappings we created.
   SymbolIndexMap.clear();
   SectionMap.clear();
 
   UndefinedCsects.clear();
   // Reset any sections we have written to, and empty the section header table.
   for (auto *Sec : Sections)
     Sec->reset();
   for (auto &DwarfSec : DwarfSections)
     DwarfSec.reset();
+  ExceptionSection.reset();
 
   // Reset states in XCOFFObjectWriter.
   SymbolTableEntryCount = 0;
   SymbolTableOffset = 0;
   SectionCount = 0;
   RelocationEntryOffset = 0;
   Strings.clear();
 
void XCOFFObjectWriter::writeSections(const MCAssembler &Asm,
                                       const MCAsmLayout &Layout) {
   uint64_t CurrentAddressLocation = 0;
   for (const auto *Section : Sections)
     writeSectionForControlSectionEntry(Asm, Layout, *Section,
                                        CurrentAddressLocation);
   for (const auto &DwarfSection : DwarfSections)
     writeSectionForDwarfSectionEntry(Asm, Layout, DwarfSection,
                                      CurrentAddressLocation);
+  writeSectionForExceptionSectionEntry(Asm, Layout, ExceptionSection,
+                                       CurrentAddressLocation);
 }
 
 uint64_t XCOFFObjectWriter::writeObject(MCAssembler &Asm,
                                         const MCAsmLayout &Layout) {
   // We always emit a timestamp of 0 for reproducibility, so ensure incremental
   // linking is not enabled, in case, like with Windows COFF, such a timestamp
   // is incompatible with incremental linking of XCOFF.
   if (Asm.isIncrementalLinkerCompatible())
void XCOFFObjectWriter::writeSymbolEntry(StringRef SymbolName, uint64_t Value,
   if (is64Bit()) {
     W.write<uint64_t>(Value);
     W.write<uint32_t>(Strings.getOffset(SymbolName));
   } else {
     writeSymbolName(SymbolName);
     W.write<uint32_t>(Value);
   }
   W.write<int16_t>(SectionNumber);
-  // TODO Set the function indicator (bit 10, 0x0020) for functions
-  // when debugging is enabled.
   W.write<uint16_t>(SymbolType);
   W.write<uint8_t>(StorageClass);
   W.write<uint8_t>(NumberOfAuxEntries);
 }
 
 void XCOFFObjectWriter::writeSymbolAuxCsectEntry(uint64_t SectionOrLength,
                                                  uint8_t SymbolAlignmentAndType,
                                                  uint8_t StorageMappingClass) {

 }
 
 void XCOFFObjectWriter::writeSymbolEntryForCsectMemberLabel(
     const Symbol &SymbolRef, const XCOFFSection &CSectionRef,
     int16_t SectionIndex, uint64_t SymbolOffset) {
   assert(SymbolOffset <= MaxRawDataSize - CSectionRef.Address &&
          "Symbol address overflowed.");
 
+  for (auto &SymbolEntry : ExceptionSection.ExceptionTable) {
+    if(SymbolRef.MCSym == SymbolEntry.Symbol) {
+      writeSymbolEntry(SymbolRef.getSymbolTableName(),
+                   CSectionRef.Address + SymbolOffset, SectionIndex,
+                   is64Bit() ? SymbolRef.getVisibilityType() : 
+                   SymbolRef.getVisibilityType() | 0x0020, 
+                   SymbolRef.getStorageClass(), 
+                   (is64Bit() && ExceptionSection.isDebugEnabled) ? 3 : 2);
+
+      if(is64Bit() && ExceptionSection.isDebugEnabled) {
+        writeSymbolAuxExceptionEntry(ExceptionSection.FileOffsetToData + 
+            getExceptionOffset(SymbolEntry.Symbol), 
+            SymbolEntry.FunctionSize, 
+            SymbolIndexMap[SymbolEntry.Symbol] + 4);
+      }
+      writeSymbolAuxFunctionEntry(ExceptionSection.FileOffsetToData + 
+          getExceptionOffset(SymbolEntry.Symbol), 
+          SymbolEntry.FunctionSize, 0, 
+    (is64Bit() && ExceptionSection.isDebugEnabled) ?
+          SymbolIndexMap[SymbolEntry.Symbol] + 4 :
+          SymbolIndexMap[SymbolEntry.Symbol] + 3);
+
+      writeSymbolAuxCsectEntry(CSectionRef.SymbolTableIndex, XCOFF::XTY_LD,
+                               CSectionRef.MCSec->getMappingClass());
+      return;
+    }
+  }
+
   writeSymbolEntry(SymbolRef.getSymbolTableName(),
                    CSectionRef.Address + SymbolOffset, SectionIndex,
                    SymbolRef.getVisibilityType(), SymbolRef.getStorageClass());
 
   writeSymbolAuxCsectEntry(CSectionRef.SymbolTableIndex, XCOFF::XTY_LD,
                            CSectionRef.MCSec->getMappingClass());
 }
 
void XCOFFObjectWriter::writeSymbolEntryForControlSection(
     XCOFF::StorageClass StorageClass) {
   writeSymbolEntry(CSectionRef.getSymbolTableName(), CSectionRef.Address,
                    SectionIndex, CSectionRef.getVisibilityType(), StorageClass);
 
   writeSymbolAuxCsectEntry(CSectionRef.Size, getEncodedType(CSectionRef.MCSec),
                            CSectionRef.MCSec->getMappingClass());
 }
 
+void XCOFFObjectWriter::writeSymbolAuxFunctionEntry(
+                        uint32_t EntryOffset, uint32_t FunctionSize,
+                        uint64_t LineNumberPointer, uint32_t EndIndex) {
+  if (is64Bit()) writeWord(LineNumberPointer);
+  else W.write<uint32_t>(EntryOffset);
+  W.write<uint32_t>(FunctionSize);
+  if (!is64Bit()) W.write<uint32_t>(LineNumberPointer);
+  W.write<uint32_t>(EndIndex);
+  if(is64Bit()) {
+    W.OS.write_zeros(1);
+    W.write<uint8_t>(XCOFF::AUX_FCN);
+  } else {
+    W.OS.write_zeros(2);
+  }
+}
+
+void XCOFFObjectWriter::writeSymbolAuxExceptionEntry(
+    uint64_t EntryOffset, uint32_t FunctionSize, uint32_t EndIndex) {
+  assert(is64Bit() && "Exception auxilliary entries are 64-bit only.");
+  W.write<uint64_t>(EntryOffset);
+  W.write<uint32_t>(FunctionSize);
+  W.write<uint32_t>(EndIndex);
+  W.OS.write_zeros(1); // Pad (unused)
+  W.write<uint8_t>(XCOFF::AUX_EXCEPT);
+}
+
 void XCOFFObjectWriter::writeFileHeader() {
   W.write<uint16_t>(is64Bit() ? XCOFF::XCOFF64 : XCOFF::XCOFF32);
   W.write<uint16_t>(SectionCount);
   W.write<int32_t>(0); // TimeStamp
   writeWord(SymbolTableOffset);
   if (is64Bit()) {
     W.write<uint16_t>(auxiliaryHeaderSize());
     W.write<uint16_t>(0); // Flags
auto writeSectionHeader = [&](const SectionEntry *Sec, bool IsDwarf) {
 
     return true;
   };
 
   for (const auto *CsectSec : Sections)
     writeSectionHeader(CsectSec, /* IsDwarf */ false);
   for (const auto &DwarfSec : DwarfSections)
     writeSectionHeader(&DwarfSec, /* IsDwarf */ true);
+  if(hasExceptionSection())
+    writeSectionHeader(&ExceptionSection, false);
 }
 
 void XCOFFObjectWriter::writeRelocation(XCOFFRelocation Reloc,
                                         const XCOFFSection &Section) {
   if (Section.MCSec->isCsect())
     writeWord(Section.Address + Reloc.FixupOffsetInCsect);
   else {
     // DWARF sections' address is set to 0.
for (auto &DwarfSec : DwarfSections)
     calcOffsetToRelocations(&DwarfSec, /* IsDwarf */ true);
 
   // TODO Error check that the number of symbol table entries fits in 32-bits
   // signed ...
   if (SymbolTableEntryCount)
     SymbolTableOffset = RawPointer;
 }
 
+void XCOFFObjectWriter::addExceptionEntry(
+                        const MCSymbol *Symbol, MCSymbol *Trap,
+                        unsigned LanguageCode, unsigned ReasonCode,
+                        unsigned FunctionSize, bool hasDebug) {
+  // if a module had debug info, debugging is enabled and XCOFF emits the 
+  // exception auxilliary entry.
+  if (hasDebug) ExceptionSection.isDebugEnabled = true;
+  for(auto &SymbolEntry : ExceptionSection.ExceptionTable) {
+    if (Symbol == SymbolEntry.Symbol) {
+      SymbolEntry.Entries.push_back(
+                          ExceptionTableEntry(Trap, LanguageCode, ReasonCode));
+      return;
+    }
+  }
+  ExceptionInfo NewEntry;
+  NewEntry.Symbol = Symbol;
+  NewEntry.FunctionSize = FunctionSize;
+  NewEntry.Entries.push_back(
+                   ExceptionTableEntry(Trap, LanguageCode, ReasonCode));
+  ExceptionSection.ExceptionTable.push_back(NewEntry);
+}
+
+unsigned XCOFFObjectWriter::getExceptionSectionSize() {
+  unsigned Size = 0;
+  for(auto &SymbolEntry : ExceptionSection.ExceptionTable) {
+    Size += (is64Bit()) ?  (SymbolEntry.Entries.size() + 1) * 
+                                        XCOFF::ExceptionSectionEntrySize64 : 
+                           (SymbolEntry.Entries.size() + 1) * 
+                                        XCOFF::ExceptionSectionEntrySize32;
+  }
+  return Size;
+}
+
+unsigned XCOFFObjectWriter::getExceptionOffset(const MCSymbol *Symbol) {
+  unsigned Offset = 0;
+  for(auto &SymbolEntry : ExceptionSection.ExceptionTable) {
+    if(Symbol == SymbolEntry.Symbol) return Offset;
+    Offset += (is64Bit()) ? XCOFF::ExceptionSectionEntrySize64 : 
+                            XCOFF::ExceptionSectionEntrySize32;
+    for(auto &TrapEntry : SymbolEntry.Entries) {
+      (void) TrapEntry;
+      Offset += (is64Bit()) ? XCOFF::ExceptionSectionEntrySize64 : 
+                              XCOFF::ExceptionSectionEntrySize32;
+    }
+  }
+  return Offset;
+}
+
 void XCOFFObjectWriter::assignAddressesAndIndices(const MCAsmLayout &Layout) {
   // The symbol table starts with all the C_FILE symbols.
   uint32_t SymbolTableIndex = FileNames.size();
 
   // Calculate indices for undefined symbols.
   for (auto &Csect : UndefinedCsects) {
     Csect.Size = 0;
     Csect.Address = 0;
for (auto *Group : Section->Groups) {
         Csect.Size = Layout.getSectionAddressSize(MCSec);
         Address = Csect.Address + Csect.Size;
         Csect.SymbolTableIndex = SymbolTableIndex;
         SymbolIndexMap[MCSec->getQualNameSymbol()] = Csect.SymbolTableIndex;
         // 1 main and 1 auxiliary symbol table entry for the csect.
         SymbolTableIndex += 2;
 
         for (auto &Sym : Csect.Syms) {
+          bool hasExceptEntry = false;
+          for (auto &SymbolEntry : ExceptionSection.ExceptionTable) {
+            if (SymbolEntry.Symbol == Sym.MCSym) {
+              hasExceptEntry = true;
+              for(auto &TrapEntry : SymbolEntry.Entries) {
+                TrapEntry.TrapAddress = Layout.getSymbolOffset(*(Sym.MCSym)) +
+                    TrapEntry.Trap->getOffset();
+        }
+      }
+    }
           Sym.SymbolTableIndex = SymbolTableIndex;
           SymbolIndexMap[Sym.MCSym] = Sym.SymbolTableIndex;
           // 1 main and 1 auxiliary symbol table entry for each contained
-          // symbol.
+          // symbol. 1 or 2 additional auxiliary entries if exception section
+          // present.
+          SymbolTableIndex += 2;
+          if(hasExceptionSection() && hasExceptEntry) {
+            if(is64Bit() && ExceptionSection.isDebugEnabled) 
                 SymbolTableIndex += 2;
+            else SymbolTableIndex += 1;
+          }
         }
       }
 
       if (!SectionAddressSet) {
         Section->Address = Group->front().Address;
         SectionAddressSet = true;
       }
     }
void XCOFFObjectWriter::assignAddressesAndIndices(const MCAsmLayout &Layout) {
   }
   if (LastDwarfSection) {
     // Make the final DWARF section address align to the default section
     // alignment for follow contents.
     Address = alignTo(LastDwarfSection->Address + LastDwarfSection->Size,
                       DefaultSectionAlign);
     LastDwarfSection->MemorySize = Address - LastDwarfSection->Address;
   }
-
+  if (hasExceptionSection()) {
+    ExceptionSection.Index = SectionIndex++;
+    SectionCount++;
+    ExceptionSection.Address = 0; 
+    ExceptionSection.Size = getExceptionSectionSize(); 
+    Address += ExceptionSection.Size;
+    Address = alignTo(Address, DefaultSectionAlign);
+  } 
   SymbolTableEntryCount = SymbolTableIndex;
 
   // Calculate the RawPointer value for each section.
   uint64_t RawPointer =
       (is64Bit() ? (XCOFF::FileHeaderSize64 +
                     SectionCount * XCOFF::SectionHeaderSize64)
                  : (XCOFF::FileHeaderSize32 +
                     SectionCount * XCOFF::SectionHeaderSize32)) +
for (auto &DwarfSection : DwarfSections) {
     DwarfSection.FileOffsetToData = RawPointer;
 
     RawPointer += DwarfSection.MemorySize;
 
     assert(RawPointer <= MaxRawDataSize &&
            "Section raw data overflowed this object file.");
   }
 
+  if(hasExceptionSection()) {
+    ExceptionSection.FileOffsetToData = RawPointer;
+    RawPointer += ExceptionSection.Size;
+
+    assert(RawPointer <= MaxRawDataSize &&
+           "Section raw data overflowed this object file.");
+  }
+
   RelocationEntryOffset = RawPointer;
 }
 
 void XCOFFObjectWriter::writeSectionForControlSectionEntry(
     const MCAssembler &Asm, const MCAsmLayout &Layout,
     const CsectSectionEntry &CsectEntry, uint64_t &CurrentAddressLocation) {
   // Nothing to write for this Section.
   if (CsectEntry.Index == SectionEntry::UninitializedIndex)
void XCOFFObjectWriter::writeSectionForDwarfSectionEntry(
   uint32_t Mod = CurrentAddressLocation % DefaultSectionAlign;
   uint32_t TailPaddingSize = Mod ? DefaultSectionAlign - Mod : 0;
   if (TailPaddingSize)
     W.OS.write_zeros(TailPaddingSize);
 
   CurrentAddressLocation += TailPaddingSize;
 }
 
+void XCOFFObjectWriter::writeSectionForExceptionSectionEntry(
+    const MCAssembler &Asm, const MCAsmLayout &Layout,
+    ExceptionSectionEntry &ExceptionEntry, uint64_t &CurrentAddressLocation) {
+  for(auto const &SymbolEntry : ExceptionEntry.ExceptionTable) {
+    W.write<uint32_t>(SymbolIndexMap[SymbolEntry.Symbol]);
+    if (is64Bit()) {
+      W.OS.write_zeros(4);
+    }
+    W.OS.write_zeros(2);
+    for(auto &TrapEntry : SymbolEntry.Entries) {
+      if (is64Bit()) {
+        W.write<uint64_t>(TrapEntry.TrapAddress);
+      } else {
+        W.write<uint32_t>(TrapEntry.TrapAddress);
+      }
+      W.write<uint8_t>(TrapEntry.Lang);
+      W.write<uint8_t>(TrapEntry.Reason);
+    }
+  }
+
+  CurrentAddressLocation += getExceptionSectionSize();
+}
+
 // Takes the log base 2 of the alignment and shifts the result into the 5 most
 // significant bits of a byte, then or's in the csect type into the least
 // significant 3 bits.
 uint8_t getEncodedType(const MCSectionXCOFF *Sec) {
   unsigned Align = Sec->getAlignment();
   assert(isPowerOf2_32(Align) && "Alignment must be a power of 2.");
   unsigned Log2Align = Log2_32(Align);
   // Result is a number in the range [0, 31] which fits in the 5 least

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

bool PPCAIXAsmPrinter::doInitialization(Module &M) {
 
   return Result;
 }
 
 void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default:
     break;
+  case PPC::TW:
+  case PPC::TWI:
+  case PPC::TD:
+  case PPC::TDI: {
+    if (MI->getNumOperands() < 5)
+      break; 
+    const MachineOperand &LangMO = MI->getOperand(3);
+    const MachineOperand &ReasonMO = MI->getOperand(4);
+    if (!LangMO.isImm() || !ReasonMO.isImm())
+      break;
+    MCSymbol *TempSym = OutContext.createNamedTempSymbol();
+    OutStreamer->emitLabel(TempSym);
+    OutStreamer->emitXCOFFExceptDirective(CurrentFnSym, TempSym,
+                 LangMO.getImm(), ReasonMO.getImm(),
+                 Subtarget->isPPC64() ? MI->getMF()->getInstructionCount() * 8 :
+                 MI->getMF()->getInstructionCount() * 4,
+     MMI->hasDebugInfo());
+    break;
+  }
   case PPC::GETtlsADDR64AIX:
   case PPC::GETtlsADDR32AIX: {
     // The reference to .__tls_get_addr is unknown to the assembler
     // so we need to emit an external symbol reference.
     MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext);
     ExtSymSDNodeSymbols.insert(TlsGetAddr);
     break;
   }

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
       ReplaceNode(N, selectI64Imm(CurDAG, N));
       return;
     }
     break;
 
   case ISD::INTRINSIC_VOID: {
     auto IntrinsicID = N->getConstantOperandVal(1);
-    if (IntrinsicID == Intrinsic::ppc_tdw || IntrinsicID == Intrinsic::ppc_tw) {
-      unsigned Opcode = IntrinsicID == Intrinsic::ppc_tdw ? PPC::TDI : PPC::TWI;
+    if (IntrinsicID != Intrinsic::ppc_tdw && IntrinsicID != Intrinsic::ppc_tw &&
+        IntrinsicID != Intrinsic::ppc_trapd &&
+        IntrinsicID != Intrinsic::ppc_trap)
+        break;
+    unsigned Opcode = (IntrinsicID == Intrinsic::ppc_tdw ||
+                       IntrinsicID == Intrinsic::ppc_trapd)
+                          ? PPC::TDI
+                          : PPC::TWI;
+    SmallVector<SDValue, 4> OpsWithMD;
+    unsigned MDIndex;
+    if (IntrinsicID == Intrinsic::ppc_tdw ||
+        IntrinsicID == Intrinsic::ppc_tw) {
       SDValue Ops[] = {N->getOperand(4), N->getOperand(2), N->getOperand(3)};
       int16_t SImmOperand2;
       int16_t SImmOperand3;
       int16_t SImmOperand4;
       bool isOperand2IntS16Immediate =
           isIntS16Immediate(N->getOperand(2), SImmOperand2);
       bool isOperand3IntS16Immediate =
           isIntS16Immediate(N->getOperand(3), SImmOperand3);
if (IntrinsicID == Intrinsic::ppc_tdw ||
           TO = (TO & 0x1) ? TO + 1 : TO - 1;
         // We swap the fourth and fifth bit of TO if they are not same.
         if ((TO & 0x8) != ((TO & 0x10) >> 1))
           TO = (TO & 0x8) ? TO + 8 : TO - 8;
         Ops[0] = getI32Imm(TO, dl);
         Ops[1] = N->getOperand(3);
         Ops[2] = getI32Imm(int(SImmOperand2) & 0xFFFF, dl);
       }
-      CurDAG->SelectNodeTo(N, Opcode, MVT::Other, Ops);
-      return;
+      OpsWithMD = {Ops[0], Ops[1], Ops[2]};
+      MDIndex = 5;
+    } else {
+      OpsWithMD = {getI32Imm(24, dl), N->getOperand(2), getI32Imm(0, dl)};
+      MDIndex = 3;
     }
-    break;
+
+    if (N->getNumOperands() > MDIndex) {
+      SDValue MDV = N->getOperand(MDIndex);
+      const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
+      assert(MD->getNumOperands() != 0 && "Empty MDNode in operands!");
+      assert((isa<MDString>(MD->getOperand(0)) && cast<MDString>(
+           MD->getOperand(0))->getString().equals("ppc-trap-reason")) 
+           && "Unsupported annotation data type!");
+      for (unsigned i = 1; i < MD->getNumOperands(); i++) {
+        assert(isa<MDString>(MD->getOperand(i)) && 
+               "Invalid data type for annotation ppc-trap-reason!");
+        OpsWithMD.push_back(
+            getI32Imm(std::stoi(cast<MDString>(
+                      MD->getOperand(i))->getString().str()), dl));
+      }
+    }
+    OpsWithMD.push_back(N->getOperand(0)); // chain
+    CurDAG->SelectNodeTo(N, Opcode, MVT::Other, OpsWithMD);
+    return;
   }
 
   case ISD::INTRINSIC_WO_CHAIN: {
     // We emit the PPC::FSELS instruction here because of type conflicts with
     // the comparison operand. The FSELS instruction is defined to use an 8-byte
     // comparison like the FSELD version. The fsels intrinsic takes a 4-byte
     // value for the comparison. When selecting through a .td file, a type
     // error is raised. Must check this first so we never break on the

llvm/lib/Target/PowerPC/PPCISelLowering.h

getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
         return InlineAsm::Constraint_Q;
       else if (ConstraintCode == "Z")
         return InlineAsm::Constraint_Z;
       else if (ConstraintCode == "Zy")
         return InlineAsm::Constraint_Zy;
       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     }
 
+    void LowerTargetIntrinsic(const CallInst &I, SDValue &Op,
+                              SmallVector<SDValue, 8> &Ops,
+                              SelectionDAG &DAG) const override;
+
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
                                Type *Ty, unsigned AS,
                                Instruction *I = nullptr) const override;
 
     /// isLegalICmpImmediate - Return true if the specified immediate is legal
     /// icmp immediate, that is the target has icmp instructions which can

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Result.getNode()) {
     Ops.push_back(Result);
     return;
   }
 
   // Handle standard constraint letters.
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
+void PPCTargetLowering::LowerTargetIntrinsic(const CallInst &I, SDValue &Op,
+                                             SmallVector<SDValue, 8> &Ops,
+                                             SelectionDAG &DAG) const {
+  if (I.getNumOperands() <= 1)
+    return;
+  if (!isa<ConstantSDNode>(Ops[1].getNode()))
+    return;
+  auto IntrinsicID = cast<ConstantSDNode>(Ops[1].getNode())->getZExtValue();
+  if (IntrinsicID != Intrinsic::ppc_tdw && IntrinsicID != Intrinsic::ppc_tw &&
+      IntrinsicID != Intrinsic::ppc_trapd && IntrinsicID != Intrinsic::ppc_trap)
+    return;
+
+  if (I.hasMetadata("annotation")) {
+    MDNode *MDN = I.getMetadata("annotation");
+    Ops.push_back(DAG.getMDNode(MDN));
+  }
+  return;
+}
+
 // isLegalAddressingMode - Return true if the addressing mode represented
 // by AM is legal for this target, for a load/store of the specified type.
 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                               const AddrMode &AM, Type *Ty,
                                               unsigned AS,
                                               Instruction *I) const {
   // Vector type r+i form is supported since power9 as DQ form. We don't check
   // the offset matching DQ form requirement(off % 16 == 0), because on PowerPC,

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
           (STDCX g8rc:$A, ForceXForm:$dst)>;
 
-// trapd
-def : Pat<(int_ppc_trapd g8rc:$A),
-          (TDI 24, $A, 0)>;
 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
           (MFSPR8 $SPR)>;
 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
           (MTSPR8 $SPR, $RT)>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
                           "stwat $rS, $rA, $FC", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
-def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
+def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm, variable_ops),
                      "twi $to, $rA, $imm", IIC_IntTrapW, []>;
-def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
+def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB, variable_ops),
                  "tw $to, $rA, $rB", IIC_IntTrapW, []>;
-def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
+def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm, variable_ops),
                      "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
-def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
+def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB, variable_ops),
                  "td $to, $rA, $rB", IIC_IntTrapD, []>;
 
 def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
                        "popcntb $rA, $rS", IIC_IntGeneral,
                        [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Load Instructions.

 // swap the high word and low word.
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
           (STWCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
           (STBCX gprc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_trap gprc:$A),
-          (TWI 24, $A, 0)>;
 
 def : Pat<(int_ppc_fcfid f64:$A),
         (XSCVSXDDP $A)>;
 def : Pat<(int_ppc_fcfud f64:$A),
         (XSCVUXDDP $A)>;
 def : Pat<(int_ppc_fctid f64:$A),
         (FCTID $A)>;
 def : Pat<(int_ppc_fctidz f64:$A),

llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll

+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --exception-section %t.o | FileCheck %s --check-prefix=EXCEPT64
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefix=READ64
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --syms %t.o | FileCheck %s --check-prefix=SYMS64
+
+; If any debug information is included in a module and is XCOFF64, exception auxilliary entries are emitted
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+
+!0 = !{i32 2, !"Dwarf Version", i32 3}
+!1 = !{i32 2, !"Debug Info Version", i32 3}
+!2 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !3, producer: "ASTI IR translator", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false)
+!3 = !DIFile(filename: "t.f", directory: ".")
+!4 = distinct !DISubprogram(name: "test__trap_annotation_debug", linkageName: "test__trap_annotation_debug", scope: !3, file: !3, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !6)
+!5 = !DISubroutineType(types: !6)
+!6 = !{}
+!7 = !DILocation(line: 4, column: 1, scope: !4)
+!8 = !{!"ppc-trap-reason", !"1", !"2"}
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @sub_test() {
+  call void @llvm.ppc.trap(i32 1), !annotation !8
+  ret void
+}
+define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 {
+  call void @llvm.ppc.trap(i32 %a), !annotation !8
+  call void @sub_test()
+  call void @llvm.ppc.trap(i32 %a), !annotation !8
+  ret void
+}
+
+; EXCEPT64:       Exception section {
+; EXCEPT64-NEXT:    Symbol Index: 3 (.sub_test)
+; EXCEPT64-NEXT:    LangID: 0
+; EXCEPT64-NEXT:    Reason: 0
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x4
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:    Symbol Index: 7 (.test__trap_annotation_debug)
+; EXCEPT64-NEXT:    LangID: 0
+; EXCEPT64-NEXT:    Reason: 0
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x38
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x44
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:  }
+
+; READ64:       Sections [
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 1
+; READ64-NEXT:      Name: .text
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x8C
+; READ64-NEXT:      RawDataOffset: 0x1C8
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_TEXT (0x20)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 2
+; READ64-NEXT:      Name: .data
+; READ64-NEXT:      PhysicalAddress: 0x90
+; READ64-NEXT:      VirtualAddress: 0x90
+; READ64-NEXT:      Size: 0x30
+; READ64-NEXT:      RawDataOffset: 0x254
+; READ64-NEXT:      RelocationPointer: 0x3C6
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 4
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_DATA (0x40)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 3
+; READ64-NEXT:      Name: .dwabrev
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x2A
+; READ64-NEXT:      RawDataOffset: 0x284
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_DWARF (0x10)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 4
+; READ64-NEXT:      Name: .dwinfo
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x9A
+; READ64-NEXT:      RawDataOffset: 0x2C4
+; READ64-NEXT:      RelocationPointer: 0x3FE
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 6
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_DWARF (0x10)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 5
+; READ64-NEXT:      Name: .dwline
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x30
+; READ64-NEXT:      RawDataOffset: 0x364
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_DWARF (0x10)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 6
+; READ64-NEXT:      Name: .except
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x32
+; READ64-NEXT:      RawDataOffset: 0x394
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_EXCEPT (0x100)
+; READ64-NEXT:    }
+; READ64-NEXT:  ]
+
+; SYMS64:           Index: [[#IND:]]{{.*}}{{[[:space:]] *}}Name: .sub_test
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x0
+; SYMS64-NEXT:      Section: .text
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 3
+; SYMS64-NEXT:      Exception Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+1]]
+; SYMS64-NEXT:        OffsetToExceptionTable: 0x394
+; SYMS64-NEXT:        SizeOfFunction: 0x18
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+4]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_EXCEPT (0xFF)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      Function Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+2]]
+; SYMS64-NEXT:        SizeOfFunction: 0x18
+; SYMS64-NEXT:        PointerToLineNum: 0x0
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+4]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_FCN (0xFE)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+3]]
+; SYMS64-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 0
+; SYMS64-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS64-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+4]]
+; SYMS64-NEXT:      Name: .test__trap_annotation_debug
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x28
+; SYMS64-NEXT:      Section: .text
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 3
+; SYMS64-NEXT:      Exception Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+5]]
+; SYMS64-NEXT:        OffsetToExceptionTable: 0x3A8
+; SYMS64-NEXT:        SizeOfFunction: 0x68
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+8]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_EXCEPT (0xFF)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      Function Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+6]]
+; SYMS64-NEXT:        SizeOfFunction: 0x68
+; SYMS64-NEXT:        PointerToLineNum: 0x0
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+8]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_FCN (0xFE)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+7]]
+; SYMS64-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 0
+; SYMS64-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS64-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+8]]
+; SYMS64-NEXT:      Name: sub_test
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x90
+; SYMS64-NEXT:      Section: .data
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 1
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+9]]
+; SYMS64-NEXT:        SectionLen: 24
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 3
+; SYMS64-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS64-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+10]]
+; SYMS64-NEXT:      Name: test__trap_annotation_debug
+; SYMS64-NEXT:      Value (RelocatableAddress): 0xA8
+; SYMS64-NEXT:      Section: .data
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 1
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+11]]
+; SYMS64-NEXT:        SectionLen: 24
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 3
+; SYMS64-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS64-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }

llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll

+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --exception-section %t.o | FileCheck %s --check-prefix=EXCEPT
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefix=READ
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --syms %t.o | FileCheck %s --check-prefix=SYMS
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-objdump --section-headers %t.o | FileCheck %s --check-prefix=DUMP
+
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --exception-section %t.o | FileCheck %s --check-prefix=EXCEPT64
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefix=READ64
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --syms %t.o | FileCheck %s --check-prefix=SYMS64
+; RUN: llc -O0 -mtriple=powerpc64-unknown-aix -filetype=obj -o %t.o < %s
+; RUN: llvm-objdump --section-headers %t.o | FileCheck %s --check-prefix=DUMP64
+
+!1 = !{!"ppc-trap-reason", !"1", !"2"}
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @sub_test() {
+  call void @llvm.ppc.trap(i32 1), !annotation !1
+  ret void
+}
+define dso_local void @test__trap_annotation(i32 %a) {
+  call void @llvm.ppc.trap(i32 %a), !annotation !1
+  call void @sub_test()
+  call void @llvm.ppc.trap(i32 %a), !annotation !1
+  ret void
+}
+
+; EXCEPT:       Exception section {
+; EXCEPT-NEXT:    Symbol Index: 3 (.sub_test)
+; EXCEPT-NEXT:    LangID: 0
+; EXCEPT-NEXT:    Reason: 0
+; EXCEPT-NEXT:    Trap Instr Addr: 0x4
+; EXCEPT-NEXT:    LangID: 1
+; EXCEPT-NEXT:    Reason: 2
+; EXCEPT-NEXT:    Symbol Index: 6 (.test__trap_annotation)
+; EXCEPT-NEXT:    LangID: 0
+; EXCEPT-NEXT:    Reason: 0
+; EXCEPT-NEXT:    Trap Instr Addr: 0x38
+; EXCEPT-NEXT:    LangID: 1
+; EXCEPT-NEXT:    Reason: 2
+; EXCEPT-NEXT:    Trap Instr Addr: 0x44
+; EXCEPT-NEXT:    LangID: 1
+; EXCEPT-NEXT:    Reason: 2
+; EXCEPT-NEXT:  }
+
+; READ:       Sections [
+; READ-NEXT:    Section {
+; READ-NEXT:      Index: 1
+; READ-NEXT:      Name: .text
+; READ-NEXT:      PhysicalAddress: 0x0
+; READ-NEXT:      VirtualAddress: 0x0
+; READ-NEXT:      Size: 0x84
+; READ-NEXT:      RawDataOffset: 0x8C
+; READ-NEXT:      RelocationPointer: 0x0
+; READ-NEXT:      LineNumberPointer: 0x0
+; READ-NEXT:      NumberOfRelocations: 0
+; READ-NEXT:      NumberOfLineNumbers: 0
+; READ-NEXT:      Type: STYP_TEXT (0x20)
+; READ-NEXT:    }
+; READ-NEXT:    Section {
+; READ-NEXT:      Index: 2
+; READ-NEXT:      Name: .data
+; READ-NEXT:      PhysicalAddress: 0x84
+; READ-NEXT:      VirtualAddress: 0x84
+; READ-NEXT:      Size: 0x18
+; READ-NEXT:      RawDataOffset: 0x110
+; READ-NEXT:      RelocationPointer: 0x146
+; READ-NEXT:      LineNumberPointer: 0x0
+; READ-NEXT:      NumberOfRelocations: 4
+; READ-NEXT:      NumberOfLineNumbers: 0
+; READ-NEXT:      Type: STYP_DATA (0x40)
+; READ-NEXT:    }
+; READ-NEXT:    Section {
+; READ-NEXT:      Index: 3
+; READ-NEXT:      Name: .except
+; READ-NEXT:      PhysicalAddress: 0x0
+; READ-NEXT:      VirtualAddress: 0x0
+; READ-NEXT:      Size: 0x1E
+; READ-NEXT:      RawDataOffset: 0x128
+; READ-NEXT:      RelocationPointer: 0x0
+; READ-NEXT:      LineNumberPointer: 0x0
+; READ-NEXT:      NumberOfRelocations: 0
+; READ-NEXT:      NumberOfLineNumbers: 0
+; READ-NEXT:      Type: STYP_EXCEPT (0x100)
+; READ-NEXT:    }
+; READ-NEXT:  ]
+
+; SYMS:           Index: [[#IND:]]{{.*}}{{[[:space:]] *}}Name: .sub_test
+; SYMS-NEXT:      Value (RelocatableAddress): 0x0
+; SYMS-NEXT:      Section: .text
+; SYMS-NEXT:      Type: 0x20
+; SYMS-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS-NEXT:      NumberOfAuxEntries: 2
+; SYMS-NEXT:      Function Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+1]]
+; SYMS-NEXT:        OffsetToExceptionTable: 0x128
+; SYMS-NEXT:        SizeOfFunction: 0xC
+; SYMS-NEXT:        PointerToLineNum: 0x0
+; SYMS-NEXT:        SymbolIndexOfNextBeyond: [[#IND+3]]
+; SYMS-NEXT:      }
+; SYMS-NEXT:      CSECT Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+2]]
+; SYMS-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS-NEXT:        ParameterHashIndex: 0x0
+; SYMS-NEXT:        TypeChkSectNum: 0x0
+; SYMS-NEXT:        SymbolAlignmentLog2: 0
+; SYMS-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS-NEXT:        StabInfoIndex: 0x0
+; SYMS-NEXT:        StabSectNum: 0x0
+; SYMS-NEXT:      }
+; SYMS-NEXT:    }
+; SYMS-NEXT:    Symbol {
+; SYMS-NEXT:      Index: [[#IND+3]]
+; SYMS-NEXT:      Name: .test__trap_annotation
+; SYMS-NEXT:      Value (RelocatableAddress): 0x28
+; SYMS-NEXT:      Section: .text
+; SYMS-NEXT:      Type: 0x20
+; SYMS-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS-NEXT:      NumberOfAuxEntries: 2
+; SYMS-NEXT:      Function Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+4]]
+; SYMS-NEXT:        OffsetToExceptionTable: 0x134
+; SYMS-NEXT:        SizeOfFunction: 0x30
+; SYMS-NEXT:        PointerToLineNum: 0x0
+; SYMS-NEXT:        SymbolIndexOfNextBeyond: [[#IND+6]]
+; SYMS-NEXT:      }
+; SYMS-NEXT:      CSECT Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+5]]
+; SYMS-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS-NEXT:        ParameterHashIndex: 0x0
+; SYMS-NEXT:        TypeChkSectNum: 0x0
+; SYMS-NEXT:        SymbolAlignmentLog2: 0
+; SYMS-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS-NEXT:        StabInfoIndex: 0x0
+; SYMS-NEXT:        StabSectNum: 0x0
+; SYMS-NEXT:      }
+; SYMS-NEXT:    }
+; SYMS-NEXT:    Symbol {
+; SYMS-NEXT:      Index: [[#IND+6]]
+; SYMS-NEXT:      Name: sub_test
+; SYMS-NEXT:      Value (RelocatableAddress): 0x84
+; SYMS-NEXT:      Section: .data
+; SYMS-NEXT:      Type: 0x0
+; SYMS-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS-NEXT:      NumberOfAuxEntries: 1
+; SYMS-NEXT:      CSECT Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+7]]
+; SYMS-NEXT:        SectionLen: 12
+; SYMS-NEXT:        ParameterHashIndex: 0x0
+; SYMS-NEXT:        TypeChkSectNum: 0x0
+; SYMS-NEXT:        SymbolAlignmentLog2: 2
+; SYMS-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS-NEXT:        StabInfoIndex: 0x0
+; SYMS-NEXT:        StabSectNum: 0x0
+; SYMS-NEXT:      }
+; SYMS-NEXT:    }
+; SYMS-NEXT:    Symbol {
+; SYMS-NEXT:      Index: [[#IND+8]]
+; SYMS-NEXT:      Name: test__trap_annotation
+; SYMS-NEXT:      Value (RelocatableAddress): 0x90
+; SYMS-NEXT:      Section: .data
+; SYMS-NEXT:      Type: 0x0
+; SYMS-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS-NEXT:      NumberOfAuxEntries: 1
+; SYMS-NEXT:      CSECT Auxiliary Entry {
+; SYMS-NEXT:        Index: [[#IND+9]]
+; SYMS-NEXT:        SectionLen: 12
+; SYMS-NEXT:        ParameterHashIndex: 0x0
+; SYMS-NEXT:        TypeChkSectNum: 0x0
+; SYMS-NEXT:        SymbolAlignmentLog2: 2
+; SYMS-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS-NEXT:        StabInfoIndex: 0x0
+; SYMS-NEXT:        StabSectNum: 0x0
+; SYMS-NEXT:      }
+; SYMS-NEXT:    }
+
+; DUMP:       Sections:
+; DUMP-NEXT:  Idx Name          Size     VMA      Type
+; DUMP-NEXT:    0 .text         00000084 00000000 TEXT
+; DUMP-NEXT:    1 .data         00000018 00000084 DATA
+; DUMP-NEXT:    2 .except       0000001e 00000000
+
+; EXCEPT64:       Exception section {
+; EXCEPT64-NEXT:    Symbol Index: 3 (.sub_test)
+; EXCEPT64-NEXT:    LangID: 0
+; EXCEPT64-NEXT:    Reason: 0
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x4
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:    Symbol Index: 6 (.test__trap_annotation)
+; EXCEPT64-NEXT:    LangID: 0
+; EXCEPT64-NEXT:    Reason: 0
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x38
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:    Trap Instr Addr: 0x44
+; EXCEPT64-NEXT:    LangID: 1
+; EXCEPT64-NEXT:    Reason: 2
+; EXCEPT64-NEXT:  }
+
+; READ64:       Sections [
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 1
+; READ64-NEXT:      Name: .text
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x84
+; READ64-NEXT:      RawDataOffset: 0xF0
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_TEXT (0x20)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 2
+; READ64-NEXT:      Name: .data
+; READ64-NEXT:      PhysicalAddress: 0x88
+; READ64-NEXT:      VirtualAddress: 0x88
+; READ64-NEXT:      Size: 0x30
+; READ64-NEXT:      RawDataOffset: 0x174
+; READ64-NEXT:      RelocationPointer: 0x1D6
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 4
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_DATA (0x40)
+; READ64-NEXT:    }
+; READ64-NEXT:    Section {
+; READ64-NEXT:      Index: 3
+; READ64-NEXT:      Name: .except
+; READ64-NEXT:      PhysicalAddress: 0x0
+; READ64-NEXT:      VirtualAddress: 0x0
+; READ64-NEXT:      Size: 0x32
+; READ64-NEXT:      RawDataOffset: 0x1A4
+; READ64-NEXT:      RelocationPointer: 0x0
+; READ64-NEXT:      LineNumberPointer: 0x0
+; READ64-NEXT:      NumberOfRelocations: 0
+; READ64-NEXT:      NumberOfLineNumbers: 0
+; READ64-NEXT:      Type: STYP_EXCEPT (0x100)
+; READ64-NEXT:    }
+; READ64-NEXT:  ]
+
+; SYMS64:           Index: [[#IND:]]{{.*}}{{[[:space:]] *}}Name: .sub_test
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x0
+; SYMS64-NEXT:      Section: .text
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 2
+; SYMS64-NEXT:      Function Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+1]]
+; SYMS64-NEXT:        SizeOfFunction: 0x18
+; SYMS64-NEXT:        PointerToLineNum: 0x0
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+3]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_FCN (0xFE)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+2]]
+; SYMS64-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 0
+; SYMS64-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS64-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+3]]
+; SYMS64-NEXT:      Name: .test__trap_annotation
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x28
+; SYMS64-NEXT:      Section: .text
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 2
+; SYMS64-NEXT:      Function Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+4]]
+; SYMS64-NEXT:        SizeOfFunction: 0x68
+; SYMS64-NEXT:        PointerToLineNum: 0x0
+; SYMS64-NEXT:        SymbolIndexOfNextBeyond: [[#IND+6]]
+; SYMS64-NEXT:        Auxiliary Type: AUX_FCN (0xFE)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+5]]
+; SYMS64-NEXT:        ContainingCsectSymbolIndex: 1
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 0
+; SYMS64-NEXT:        SymbolType: XTY_LD (0x2)
+; SYMS64-NEXT:        StorageMappingClass: XMC_PR (0x0)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+6]]
+; SYMS64-NEXT:      Name: sub_test
+; SYMS64-NEXT:      Value (RelocatableAddress): 0x88
+; SYMS64-NEXT:      Section: .data
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 1
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: [[#IND+7]]
+; SYMS64-NEXT:        SectionLen: 24
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 3
+; SYMS64-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS64-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+; SYMS64-NEXT:    Symbol {
+; SYMS64-NEXT:      Index: [[#IND+8]]
+; SYMS64-NEXT:      Name: test__trap_annotation
+; SYMS64-NEXT:      Value (RelocatableAddress): 0xA0
+; SYMS64-NEXT:      Section: .data
+; SYMS64-NEXT:      Type: 0x0
+; SYMS64-NEXT:      StorageClass: C_EXT (0x2)
+; SYMS64-NEXT:      NumberOfAuxEntries: 1
+; SYMS64-NEXT:      CSECT Auxiliary Entry {
+; SYMS64-NEXT:        Index: 12
+; SYMS64-NEXT:        SectionLen: 24
+; SYMS64-NEXT:        ParameterHashIndex: 0x0
+; SYMS64-NEXT:        TypeChkSectNum: 0x0
+; SYMS64-NEXT:        SymbolAlignmentLog2: 3
+; SYMS64-NEXT:        SymbolType: XTY_SD (0x1)
+; SYMS64-NEXT:        StorageMappingClass: XMC_DS (0xA)
+; SYMS64-NEXT:        Auxiliary Type: AUX_CSECT (0xFB)
+; SYMS64-NEXT:      }
+; SYMS64-NEXT:    }
+
+; DUMP64:         Sections:
+; DUMP64-NEXT:    Idx Name          Size     VMA              Type
+; DUMP64-NEXT:    0 .text         00000084 0000000000000000 TEXT
+; DUMP64-NEXT:    1 .data         00000030 0000000000000088 DATA
+; DUMP64-NEXT:    2 .except       00000032 0000000000000000

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-64bit.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s -check-prefix=AIX
+; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 --filetype=obj -o /dev/null %s 2>&1 | FileCheck %s -check-prefix=OBJ
+
+; llc filetype=obj tested in /llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
+
+!1 = !{!"ppc-trap-reason", !"1", !"2"}
+declare void @llvm.ppc.trapd(i64 %a)
+declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
+
+define dso_local void @test__trapd_annotation(i64 %a) {
+; CHECK-LABEL: test__trapd_annotation:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 4, r3, 0
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: test__trapd_annotation:
+; AIX:       # %bb.0:
+; AIX-NEXT:    .except .test__trapd_annotation, 1, 2
+; AIX-NEXT:    tdi 4, r3, 0
+; AIX-NEXT:    blr
+  call void @llvm.ppc.trapd(i64 %a), !annotation !1
+  ret void
+}
+
+define dso_local void @test__tdw_annotation(i64 %a) {
+; CHECK-LABEL: test__tdw_annotation:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 0, r3, 4
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: test__tdw_annotation:
+; AIX:       # %bb.0:
+; AIX-NEXT:    .except .test__tdw_annotation, 1, 2
+; AIX-NEXT:    tdi 0, r3, 4
+; AIX-NEXT:    blr
+  call void @llvm.ppc.tdw(i64 4, i64 %a, i32 0), !annotation !1
+  ret void
+}

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s -check-prefix=AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s -check-prefix=AIX
+
+; llc filetype=obj tested in /llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
+
+!1 = !{!"ppc-trap-reason", !"1", !"2"}
+declare void @llvm.ppc.trap(i32 %a)
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 immarg)
+define dso_local void @test__trap_annotation(i32 %a) {
+; CHECK-LABEL: test__trap_annotation:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 4, r3, 0
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: test__trap_annotation:
+; AIX:       # %bb.0:
+; AIX-NEXT:    .except .test__trap_annotation, 1, 2
+; AIX-NEXT:    twi 4, r3, 0
+; AIX-NEXT:    blr
+  call void @llvm.ppc.trap(i32 %a), !annotation !1
+  ret void
+}
+
+define dso_local void @test__tw_annotation(i32 %a) {
+; CHECK-LABEL: test__tw_annotation:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    twi 0, r3, 4
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: test__tw_annotation:
+; AIX:       # %bb.0:
+; AIX-NEXT:    .except .test__tw_annotation, 1, 2
+; AIX-NEXT:    twi 0, r3, 4
+; AIX-NEXT:    blr
+  call void @llvm.ppc.tw(i32 4, i32 %a, i32 0), !annotation !1
+  ret void
+}