[AArch64]Remove svget/svset/svcreate from llvm

[CarolineConcatto]

Summary

This patch removes the aarch64 instrinsic svget/svset/svcreate from llvm.
It also implements the InstCombine for vector.extract that used to be in svget.

Depends on: D131547

[sdesmalen]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

2436–2437

DstTy and VecTy are misnomers, because these are only non-nullptr for FixedWidthVectors, whereas the code you added works for both ScalableVectors and FixedWidthVectors.
Can you change this code to be:

if (auto *FVTy = dyn_cast<FixedVectorType>(Vec->getType())) {
  if (auto *DstFVTy = dyn_cast<FixedVectorType>(II->getType())) {
    ...
  }
}

2459

Should this combine happen before the combine above?

llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-tuple-extract.ll

1 ↗

(On Diff #451374)

Does this test really need to be AArch64/SVE specific? Or can it live in llvm/test/Transforms/InstCombine ?

[CarolineConcatto]

• Change order of vector.extract instcombine

[CarolineConcatto]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

2459

I was not sure if I should change the order between fixed and generic. But now it is changed.

[sdesmalen]

Can you also add a test for fixed-width vectors?

llvm/test/Transforms/InstCombine/sve-intrinsic-opts-tuple-extract.ll

1 ↗

(On Diff #452647)

Please also remove sve- from the name and any references to aarch64/SVE, e.g.

• this test currently calls @llvm.aarch64.sve.st4
• this test currently uses attributes #0 = { "target-features"="+sve" }
• this test current has target triple = "aarch64-unknown-linux-gnu"

[CarolineConcatto]

Remove aarch64 dependency in opts-tuples-extract-intrinsic.ll test file

[CarolineConcatto]

• nit in opts-tuples-extract-intrinsic.ll

[CarolineConcatto]

@sdesmalen I addressed your comment and made the instcombine test for the vector.extract generic.
There is no dependency on aarch64.
I've used vector.insert to return a wider vector instead of using st4.
Is that fine?

[sdesmalen]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

2423

InsertValue ?

llvm/test/Transforms/InstCombine/opts-tuples-extract-intrinsic.ll

19–34

I find this test largely incomprehensible :)

Maybe you can split out the two cases in the code into two separate tests:

1. extract.vector(insert.vector(InsertTuple, InsertValue, Idx), Idx) --> InsertValue
2. extract.vector(insert.vector(InsertTuple, InsertValue, Idx1), Idx2) --> extract.vector(InsertTuple, Idx2)
3. And also add a negative test where the extracted vector-size != inserted vector-size.

For (1):

define <vscale x 16 x i8> @test_extract_insert_same_idx(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1) {
  ; CHECK-LABEL: @test_extract_insert_same_idx(
  ; CHECK-NEXT: ret <vscale x 16 x i8> %v1
  %vec.ins = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1, i64 48)
  %vec.ext = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %vec.ins, i64 48)
  ret <vscale x 16 x i8> %vec.ext
}

[CarolineConcatto]

Rewrite Instcombine test for vector extract. Now we have a test for when:
The indexes for extract and insert are equal
The indexes are different
The indexes are equal but the return and insert vector type are different

[CarolineConcatto]

llvm/test/Transforms/InstCombine/opts-tuples-extract-intrinsic.ll

19–34

I have changed as you said.
But just in case this was the original test we had for svget/svset intrinsics.

[sdesmalen]

Could you move the code that adds the combine for llvm.vector.extract/insert to a separate patch (along with the beautiful new test), so that we can land that patch before landing D131547?
That also makes this patch simpler, as it will just remove all the svget/svset/svcreate stuff without any other changes.

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

2441

nit: if you write the code as:

auto *FVTy = dyn_cast<FixedVectorType>(Vec->getType());
auto *DstFVTy = dyn_cast<FixedVectorType>(ReturnType);
if (FVTy && DstFVTy) {
  ...
}

you can avoid indenting the whole block (which reduces the size of the diff)

llvm/test/Transforms/InstCombine/opts-tuples-extract-intrinsic.ll

19–34

That looks great, thank you!

[sdesmalen]

As mentioned on D131547, you'll need to add code to AutoUpgrade as well to transform the old get/set/create intrinsics to llvm.vector.extract/insert (plus a corresponding test).

[CarolineConcatto]

• Add intrinsics svget/svet/svcreate in AutoUpgrade.cpp file
• Add test for these intrinsic in llvm/test/Bitcode

[sdesmalen]

llvm/lib/IR/AutoUpgrade.cpp

3883–3884 ↗

(On Diff #457280)

Is the name guaranteed to start with llvm. ?

If not, I would think it makes more sense to write:

`if (!Name.startswith("llvm.aarch64.sve.tuple")) {`

Also, should this be "tuple.get" instead of just "tuple" ?

3899 ↗

(On Diff #457280)

s/Intrinsic::ID/unsigned/ ?

3910–3919 ↗

(On Diff #457280)

Rather than this case relying on it being labeled as '1', can we just have:

if (Name.startswith("llvm.aarch64.sve.tuple.set")) {
  ...
}

if (Name.startswith("llvm.aarch64.sve.tuple.create")) {
  // Now parse the number after 'create'
  ...
}

I think that clarifies the code a bit more.

llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll

6 ↗

(On Diff #457280)

Can you add a CHECK-LABEL: @ret_svint8x2_t to this test (similar for the ones below) ?
(can you just use the update_test_checks.py script for this?)

[CarolineConcatto]

• Address comments for sve.tuple.create
• Add check label in the tests

[CarolineConcatto]

llvm/lib/IR/AutoUpgrade.cpp

3883–3884 ↗

(On Diff #457280)

If you look at line 561 in UpgradeIntrinsicFunction1 you will see this:

Name.substr(5); // Strip offllvm.

So I believe it is safe to assume it will start with llvm.

[kmclaughlin]

Hi Carol
I think you have addressed all of the comments that were previously left here, so other than a couple of minor comments from me I think this patch looks good!

llvm/lib/IR/AutoUpgrade.cpp

3883–3884 ↗

(On Diff #457280)

nit: I think adding a similar comment (// Strip llvm.) to this line would be helpful

llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll

15 ↗

(On Diff #458706)

nit: can you remove #0 from the tests now that the attribute has been removed?

[CarolineConcatto]

-Address Kerry’s comments

Remove “#0” from upgrade-aarch64-sve-intrinsics.ll
Add comment  // Strip llvm

llvm/include/llvm/IR/IntrinsicsAArch64.td

 def llvm_nxv2i64_ty : LLVMType<nxv2i64>;
 def llvm_nxv8f16_ty : LLVMType<nxv8f16>;
 def llvm_nxv8bf16_ty : LLVMType<nxv8bf16>;
 def llvm_nxv4f32_ty : LLVMType<nxv4f32>;
 def llvm_nxv2f64_ty : LLVMType<nxv2f64>;
 
 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 
-  class AdvSIMD_SVE_Create_2Vector_Tuple
-    : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-                [llvm_anyvector_ty, LLVMMatchType<1>],
-                [IntrReadMem]>;
-
-  class AdvSIMD_SVE_Create_3Vector_Tuple
-    : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-                [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>],
-                [IntrReadMem]>;
-
-  class AdvSIMD_SVE_Create_4Vector_Tuple
-    : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-                [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>,
-                 LLVMMatchType<1>],
-                [IntrReadMem]>;
-
-  class AdvSIMD_SVE_Set_Vector_Tuple
-    : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty],
-                [IntrReadMem, ImmArg<ArgIndex<1>>]>;
-
-  class AdvSIMD_SVE_Get_Vector_Tuple
-    : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty],
-                [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
-
   class AdvSIMD_ManyVec_PredLoad_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMPointerToElt<0>],
                 [IntrReadMem, IntrArgMemOnly]>;
 
   class AdvSIMD_1Vec_PredLoad_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                  LLVMPointerToElt<0>],
: DefaultAttrsIntrinsic<[llvm_nxv4f32_ty],
                 [IntrNoMem]>;
 
 class SVE_4Vec_BF16_Indexed
     : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty],
                 [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty, llvm_i64_ty],
                 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
 
 //
-// Vector tuple creation intrinsics (ACLE)
-//
-
-def int_aarch64_sve_tuple_create2 : AdvSIMD_SVE_Create_2Vector_Tuple;
-def int_aarch64_sve_tuple_create3 : AdvSIMD_SVE_Create_3Vector_Tuple;
-def int_aarch64_sve_tuple_create4 : AdvSIMD_SVE_Create_4Vector_Tuple;
-
-//
-// Vector tuple insertion/extraction intrinsics (ACLE)
-//
-
-def int_aarch64_sve_tuple_get : AdvSIMD_SVE_Get_Vector_Tuple;
-def int_aarch64_sve_tuple_set : AdvSIMD_SVE_Set_Vector_Tuple;
-
-//
 // Loads
 //
 
 def int_aarch64_sve_ld1   : AdvSIMD_1Vec_PredLoad_Intrinsic;
 
 def int_aarch64_sve_ld2 : AdvSIMD_ManyVec_PredLoad_Intrinsic;
 def int_aarch64_sve_ld3 : AdvSIMD_ManyVec_PredLoad_Intrinsic;
 def int_aarch64_sve_ld4 : AdvSIMD_ManyVec_PredLoad_Intrinsic;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case Intrinsic::aarch64_sve_st1_scatter_sxtw_index:
                                         AArch64ISD::SST1_SXTW_SCALED_PRED,
                                         /*OnlyPackedOffsets=*/false);
     case Intrinsic::aarch64_sve_st1_scatter_uxtw_index:
       return performScatterStoreCombine(N, DAG,
                                         AArch64ISD::SST1_UXTW_SCALED_PRED,
                                         /*OnlyPackedOffsets=*/false);
     case Intrinsic::aarch64_sve_st1_scatter_scalar_offset:
       return performScatterStoreCombine(N, DAG, AArch64ISD::SST1_IMM_PRED);
-    case Intrinsic::aarch64_sve_tuple_get: {
-      SDLoc DL(N);
-      SDValue Chain = N->getOperand(0);
-      SDValue Src1 = N->getOperand(2);
-      SDValue Idx = N->getOperand(3);
-
-      uint64_t IdxConst = cast<ConstantSDNode>(Idx)->getZExtValue();
-      EVT ResVT = N->getValueType(0);
-      uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue();
-      SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL);
-      SDValue Val =
-          DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, Src1, ExtIdx);
-      return DAG.getMergeValues({Val, Chain}, DL);
-    }
-    case Intrinsic::aarch64_sve_tuple_set: {
-      SDLoc DL(N);
-      SDValue Chain = N->getOperand(0);
-      SDValue Tuple = N->getOperand(2);
-      SDValue Idx = N->getOperand(3);
-      SDValue Vec = N->getOperand(4);
-
-      EVT TupleVT = Tuple.getValueType();
-      uint64_t TupleLanes = TupleVT.getVectorElementCount().getKnownMinValue();
-
-      uint64_t IdxConst = cast<ConstantSDNode>(Idx)->getZExtValue();
-      uint64_t NumLanes =
-          Vec.getValueType().getVectorElementCount().getKnownMinValue();
-
-      if ((TupleLanes % NumLanes) != 0)
-        report_fatal_error("invalid tuple vector!");
-
-      uint64_t NumVecs = TupleLanes / NumLanes;
-
-      SmallVector<SDValue, 4> Opnds;
-      for (unsigned I = 0; I < NumVecs; ++I) {
-        if (I == IdxConst)
-          Opnds.push_back(Vec);
-        else {
-          SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL);
-          Opnds.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
-                                      Vec.getValueType(), Tuple, ExtIdx));
-        }
-      }
-      SDValue Concat =
-          DAG.getNode(ISD::CONCAT_VECTORS, DL, Tuple.getValueType(), Opnds);
-      return DAG.getMergeValues({Concat, Chain}, DL);
-    }
-    case Intrinsic::aarch64_sve_tuple_create2:
-    case Intrinsic::aarch64_sve_tuple_create3:
-    case Intrinsic::aarch64_sve_tuple_create4: {
-      SDLoc DL(N);
-      SDValue Chain = N->getOperand(0);
-
-      SmallVector<SDValue, 4> Opnds;
-      for (unsigned I = 2; I < N->getNumOperands(); ++I)
-        Opnds.push_back(N->getOperand(I));
-
-      EVT VT = Opnds[0].getValueType();
-      EVT EltVT = VT.getVectorElementType();
-      EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
-                                    VT.getVectorElementCount() *
-                                        (N->getNumOperands() - 2));
-      SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
-      return DAG.getMergeValues({Concat, Chain}, DL);
-    }
     case Intrinsic::aarch64_sve_ld2:
     case Intrinsic::aarch64_sve_ld3:
     case Intrinsic::aarch64_sve_ld4: {
       SDLoc DL(N);
       SDValue Chain = N->getOperand(0);
       SDValue Mask = N->getOperand(2);
       SDValue BasePtr = N->getOperand(3);
       SDValue LoadOps[] = {Chain, Mask, BasePtr};

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

static Optional<Instruction *> instCombineSVETBL(InstCombiner &IC,
   auto *Extract = Builder.CreateExtractElement(OpVal, SplatValue);
   auto *VectorSplat =
       Builder.CreateVectorSplat(VTy->getElementCount(), Extract);
 
   VectorSplat->takeName(&II);
   return IC.replaceInstUsesWith(II, VectorSplat);
 }
 
-static Optional<Instruction *> instCombineSVETupleGet(InstCombiner &IC,
-                                                      IntrinsicInst &II) {
-  // Try to remove sequences of tuple get/set.
-  Value *SetTuple, *SetIndex, *SetValue;
-  auto *GetTuple = II.getArgOperand(0);
-  auto *GetIndex = II.getArgOperand(1);
-  // Check that we have tuple_get(GetTuple, GetIndex) where GetTuple is a
-  // call to tuple_set i.e. tuple_set(SetTuple, SetIndex, SetValue).
-  // Make sure that the types of the current intrinsic and SetValue match
-  // in order to safely remove the sequence.
-  if (!match(GetTuple,
-             m_Intrinsic<Intrinsic::aarch64_sve_tuple_set>(
-                 m_Value(SetTuple), m_Value(SetIndex), m_Value(SetValue))) ||
-      SetValue->getType() != II.getType())
-    return None;
-  // Case where we get the same index right after setting it.
-  // tuple_get(tuple_set(SetTuple, SetIndex, SetValue), GetIndex) --> SetValue
-  if (GetIndex == SetIndex)
-    return IC.replaceInstUsesWith(II, SetValue);
-  // If we are getting a different index than what was set in the tuple_set
-  // intrinsic. We can just set the input tuple to the one up in the chain.
-  // tuple_get(tuple_set(SetTuple, SetIndex, SetValue), GetIndex)
-  // --> tuple_get(SetTuple, GetIndex)
-  return IC.replaceOperand(II, 0, SetTuple);
-}
-
 static Optional<Instruction *> instCombineSVEZip(InstCombiner &IC,
                                                  IntrinsicInst &II) {
   // zip1(uzp1(A, B), uzp2(A, B)) --> A
   // zip2(uzp1(A, B), uzp2(A, B)) --> B
   Value *A, *B;
   if (match(II.getArgOperand(0),
             m_Intrinsic<Intrinsic::aarch64_sve_uzp1>(m_Value(A), m_Value(B))) &&
       match(II.getArgOperand(1), m_Intrinsic<Intrinsic::aarch64_sve_uzp2>(
case Intrinsic::aarch64_sve_fsub:
     return instCombineSVEVectorBinOp(IC, II);
   case Intrinsic::aarch64_sve_tbl:
     return instCombineSVETBL(IC, II);
   case Intrinsic::aarch64_sve_uunpkhi:
   case Intrinsic::aarch64_sve_uunpklo:
   case Intrinsic::aarch64_sve_sunpkhi:
   case Intrinsic::aarch64_sve_sunpklo:
     return instCombineSVEUnpack(IC, II);
-  case Intrinsic::aarch64_sve_tuple_get:
-    return instCombineSVETupleGet(IC, II);
   case Intrinsic::aarch64_sve_zip1:
   case Intrinsic::aarch64_sve_zip2:
     return instCombineSVEZip(IC, II);
   case Intrinsic::aarch64_sve_ld1_gather_index:
     return instCombineLD1GatherIndex(IC, II);
   case Intrinsic::aarch64_sve_st1_scatter_index:
     return instCombineST1ScatterIndex(IC, II);
   case Intrinsic::aarch64_sve_ld1:

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

if (DstTy && VecTy && SubVecTy) {
       return replaceInstUsesWith(CI, Shuffle);
     }
     break;
   }
   case Intrinsic::vector_extract: {
     Value *Vec = II->getArgOperand(0);
     Value *Idx = II->getArgOperand(1);
 
-    auto *DstTy = dyn_cast<FixedVectorType>(II->getType());
-    auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
-
+    Type *ReturnType = II->getType();
+    // (extract_vector (insert_vector InsertTuple, InsertValue, InsertIdx),
+    // ExtractIdx)
+    unsigned ExtractIdx = cast<ConstantInt>(Idx)->getZExtValue();
+    Value *InsertTuple, *InsertIdx, *InsertValue;
+    if (match(Vec, m_Intrinsic<Intrinsic::vector_insert>(m_Value(InsertTuple),
+                                                         m_Value(InsertValue),
+                                                         m_Value(InsertIdx))) &&
+        InsertValue->getType() == ReturnType) {
+      unsigned Index = cast<ConstantInt>(InsertIdx)->getZExtValue();
+      // Case where we get the same index right after setting it.
+      // extract.vector(insert.vector(InsertTuple, InsertValue, Idx), Idx) -->
+      // InsertValue
+      if (ExtractIdx == Index)
+        return replaceInstUsesWith(CI, InsertValue);
+      // If we are getting a different index than what was set in the
+      // insert.vector intrinsic. We can just set the input tuple to the one up
+      // in the chain. extract.vector(insert.vector(InsertTuple, InsertValue,
+      // InsertIndex), ExtractIndex)
+      // --> extract.vector(InsertTuple, ExtractIndex)
+      else
+        return replaceOperand(CI, 0, InsertTuple);
+    }
     // Only canonicalize if the the destination vector and Vec are fixed
     // vectors.
-    if (DstTy && VecTy) {
-      unsigned DstNumElts = DstTy->getNumElements();
-      unsigned VecNumElts = VecTy->getNumElements();
+    if (auto *FVTy = dyn_cast<FixedVectorType>(Vec->getType())) {
+      if (auto *DstFVTy = dyn_cast<FixedVectorType>(ReturnType)) {
+        unsigned DstNumElts = DstFVTy->getNumElements();
+        unsigned VecNumElts = FVTy->getNumElements();
         unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
 
         // Extracting the entirety of Vec is a nop.
         if (VecNumElts == DstNumElts) {
           replaceInstUsesWith(CI, Vec);
           return eraseInstFromFunction(CI);
         }
 
         SmallVector<int, 8> Mask;
         for (unsigned i = 0; i != DstNumElts; ++i)
           Mask.push_back(IdxN + i);
 
         Value *Shuffle = Builder.CreateShuffleVector(Vec, Mask);
         return replaceInstUsesWith(CI, Shuffle);
       }
+    }
     break;
   }
   case Intrinsic::experimental_vector_reverse: {
     Value *BO0, *BO1, *X, *Y;
     Value *Vec = II->getArgOperand(0);
     if (match(Vec, m_OneUse(m_BinOp(m_Value(BO0), m_Value(BO1))))) {
       auto *OldBinOp = cast<BinaryOperator>(Vec);
       if (match(BO0, m_Intrinsic<Intrinsic::experimental_vector_reverse>(
                          m_Value(X)))) {
         // rev(binop rev(X), rev(Y)) --> binop X, Y
         if (match(BO1, m_Intrinsic<Intrinsic::experimental_vector_reverse>(

llvm/test/CodeGen/AArch64/sve-calling-convention-tuple-types.ll

-; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
-
-;
-; svint8x2_t
-;
-
-define <vscale x 32 x i8> @ret_svint8x2_t(<vscale x 16 x i8> %unused_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2) #0 {
-; CHECK-LABEL: ret_svint8x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 32 x i8> @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2)
-  ret <vscale x 32 x i8> %tuple
-}
-
-define void @call_svint8x2_t(<vscale x 16 x i8> %dummy_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %dummy_z2, <vscale x 16 x i8> %z3) #0 {
-; CHECK-LABEL: call_svint8x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svint8x2_t
-  %tuple = tail call <vscale x 32 x i8> @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z3)
-  call void @callee_svint8x2_t(<vscale x 32 x i8> %tuple)
-  ret void
-}
-
-;
-; svint16x2_t
-;
-
-define <vscale x 16 x i16> @ret_svint16x2_t(<vscale x 8 x i16> %unused_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2) #0 {
-; CHECK-LABEL: ret_svint16x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2)
-  ret <vscale x 16 x i16> %tuple
-}
-
-define void @call_svint16x2_t(<vscale x 8 x i16> %dummy_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %dummy_z2, <vscale x 8 x i16> %z3) #0 {
-; CHECK-LABEL: call_svint16x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svint16x2_t
-  %tuple = tail call <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z3)
-  call void @callee_svint16x2_t(<vscale x 16 x i16> %tuple)
-  ret void
-}
-
-;
-; svint32x2_t
-;
-
-define <vscale x 8 x i32> @ret_svint32x2_t(<vscale x 4 x i32> %unused_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2) #0 {
-; CHECK-LABEL: ret_svint32x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  ret <vscale x 8 x i32> %tuple
-}
-
-define void @call_svint32x2_t(<vscale x 4 x i32> %dummy_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %dummy_z2, <vscale x 4 x i32> %z3) #0 {
-; CHECK-LABEL: call_svint32x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svint32x2_t
-  %tuple = tail call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z3)
-  call void @callee_svint32x2_t(<vscale x 8 x i32> %tuple)
-  ret void
-}
-
-;
-; svint64x2_t
-;
-
-define <vscale x 4 x i64> @ret_svint64x2_t(<vscale x 2 x i64> %unused_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2) #0 {
-; CHECK-LABEL: ret_svint64x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2)
-  ret <vscale x 4 x i64> %tuple
-}
-
-define void @call_svint64x2_t(<vscale x 2 x i64> %dummy_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %dummy_z2, <vscale x 2 x i64> %z3) #0 {
-; CHECK-LABEL: call_svint64x2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svint64x2_t
-  %tuple = tail call <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z3)
-  call void @callee_svint64x2_t(<vscale x 4 x i64> %tuple)
-  ret void
-}
-
-;
-; svfloatx2_t
-;
-
-define <vscale x 8 x float> @ret_svfloatx2_t(<vscale x 4 x float> %unused_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2) #0 {
-; CHECK-LABEL: ret_svfloatx2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 8 x float> @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z2)
-  ret <vscale x 8 x float> %tuple
-}
-
-define void @call_svfloatx2_t(<vscale x 4 x float> %dummy_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %dummy_z2, <vscale x 4 x float> %z3) #0 {
-; CHECK-LABEL: call_svfloatx2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svfloatx2_t
-  %tuple = tail call <vscale x 8 x float> @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z3)
-  call void @callee_svfloatx2_t(<vscale x 8 x float> %tuple)
-  ret void
-}
-
-;
-; svdoublex2_t
-;
-
-define <vscale x 4 x double> @ret_svdoublex2_t(<vscale x 2 x double> %unused_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2) #0 {
-; CHECK-LABEL: ret_svdoublex2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 4 x double> @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z2)
-  ret <vscale x 4 x double> %tuple
-}
-
-define void @call_svdoublex2_t(<vscale x 2 x double> %dummy_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %dummy_z2, <vscale x 2 x double> %z3) #0 {
-; CHECK-LABEL: call_svdoublex2_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z3.d
-; CHECK-NEXT: bl callee_svdoublex2_t
-  %tuple = tail call <vscale x 4 x double> @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z3)
-  call void @callee_svdoublex2_t(<vscale x 4 x double> %tuple)
-  ret void
-}
-
-;
-; svint8x3_t
-;
-
-define <vscale x 48 x i8> @ret_svint8x3_t(<vscale x 16 x i8> %unused_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3) #0 {
-; CHECK-LABEL: ret_svint8x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 48 x i8> @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3)
-  ret <vscale x 48 x i8> %tuple
-}
-
-define void @call_svint8x3_t(<vscale x 16 x i8> %dummy_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %dummy_z3, <vscale x 16 x i8> %z4) #0 {
-; CHECK-LABEL: call_svint8x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint8x3_t
-  %tuple = tail call <vscale x 48 x i8> @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z4)
-  call void @callee_svint8x3_t(<vscale x 48 x i8> %tuple)
-  ret void
-}
-
-;
-; svint16x3_t
-;
-
-define <vscale x 24 x i16> @ret_svint16x3_t(<vscale x 8 x i16> %unused_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3) #0 {
-; CHECK-LABEL: ret_svint16x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3)
-  ret <vscale x 24 x i16> %tuple
-}
-
-define void @call_svint16x3_t(<vscale x 8 x i16> %dummy_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %dummy_z3, <vscale x 8 x i16> %z4) #0 {
-; CHECK-LABEL: call_svint16x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint16x3_t
-  %tuple = tail call <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z4)
-  call void @callee_svint16x3_t(<vscale x 24 x i16> %tuple)
-  ret void
-}
-
-;
-; svint32x3_t
-;
-
-define <vscale x 12 x i32> @ret_svint32x3_t(<vscale x 4 x i32> %unused_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3) #0 {
-; CHECK-LABEL: ret_svint32x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  ret <vscale x 12 x i32> %tuple
-}
-
-define void @call_svint32x3_t(<vscale x 4 x i32> %dummy_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %dummy_z3, <vscale x 4 x i32> %z4) #0 {
-; CHECK-LABEL: call_svint32x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint32x3_t
-  %tuple = tail call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z4)
-  call void @callee_svint32x3_t(<vscale x 12 x i32> %tuple)
-  ret void
-}
-
-;
-; svint64x3_t
-;
-
-define <vscale x 6 x i64> @ret_svint64x3_t(<vscale x 2 x i64> %unused_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3) #0 {
-; CHECK-LABEL: ret_svint64x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3)
-  ret <vscale x 6 x i64> %tuple
-}
-
-define void @call_svint64x3_t(<vscale x 2 x i64> %dummy_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %dummy_z3, <vscale x 2 x i64> %z4) #0 {
-; CHECK-LABEL: call_svint64x3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint64x3_t
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z4)
-  call void @callee_svint64x3_t(<vscale x 6 x i64> %tuple)
-  ret void
-}
-
-;
-; svfloatx3_t
-;
-
-define <vscale x 12 x float> @ret_svfloatx3_t(<vscale x 4 x float> %unused_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3) #0 {
-; CHECK-LABEL: ret_svfloatx3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3)
-  ret <vscale x 12 x float> %tuple
-}
-
-define void @call_svfloatx3_t(<vscale x 4 x float> %dummy_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %dummy_z3, <vscale x 4 x float> %z4) #0 {
-; CHECK-LABEL: call_svfloatx3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svfloatx3_t
-  %tuple = tail call <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z4)
-  call void @callee_svfloatx3_t(<vscale x 12 x float> %tuple)
-  ret void
-}
-
-;
-; svdoublex3_t
-;
-
-define <vscale x 6 x double> @ret_svdoublex3_t(<vscale x 2 x double> %unused_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3) #0 {
-; CHECK-LABEL: ret_svdoublex3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 6 x double> @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3)
-  ret <vscale x 6 x double> %tuple
-}
-
-define void @call_svdoublex3_t(<vscale x 2 x double> %dummy_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %dummy_z3, <vscale x 2 x double> %z4) #0 {
-; CHECK-LABEL: call_svdoublex3_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svdoublex3_t
-  %tuple = tail call <vscale x 6 x double> @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z4)
-  call void @callee_svdoublex3_t(<vscale x 6 x double> %tuple)
-  ret void
-}
-
-;
-; svint8x4_t
-;
-
-define <vscale x 64 x i8> @ret_svint8x4_t(<vscale x 16 x i8> %unused_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3, <vscale x 16 x i8> %z4) #0 {
-; CHECK-LABEL: ret_svint8x4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3, <vscale x 16 x i8> %z4)
-  ret <vscale x 64 x i8> %tuple
-}
-
-define void @call_svint8x4_t(<vscale x 16 x i8> %dummy_z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %dummy_z3, <vscale x 16 x i8> %z4, <vscale x 16 x i8> %z5) #0 {
-; CHECK-LABEL: call_svint8x4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint8x4_t
-  %tuple = tail call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z4, <vscale x 16 x i8> %z5)
-  call void @callee_svint8x4_t(<vscale x 64 x i8> %tuple)
-  ret void
-}
-
-;
-; svint16x4_t
-;
-
-define <vscale x 32 x i16> @ret_svint16x4_t(<vscale x 8 x i16> %unused_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3, <vscale x 8 x i16> %z4) #0 {
-; CHECK-LABEL: ret_svint16x4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3, <vscale x 8 x i16> %z4)
-  ret <vscale x 32 x i16> %tuple
-}
-
-define void @call_svint16x4_t(<vscale x 8 x i16> %dummy_z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %dummy_z3, <vscale x 8 x i16> %z4, <vscale x 8 x i16> %z5) #0 {
-; CHECK-LABEL: call_svint16x4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint16x4_t
-  %tuple = tail call <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z4, <vscale x 8 x i16> %z5)
-  call void @callee_svint16x4_t(<vscale x 32 x i16> %tuple)
-  ret void
-}
-
-;
-; svint32x4_t
-;
-
-define <vscale x 16 x i32> @ret_svint32x4_t(<vscale x 4 x i32> %unused_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4) #0 {
-; CHECK-LABEL: ret_svint32x4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4)
-  ret <vscale x 16 x i32> %tuple
-}
-
-define void @call_svint32x4_t(<vscale x 4 x i32> %dummy_z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %dummy_z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
-; CHECK-LABEL: call_svint32x4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint32x4_t
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5)
-  call void @callee_svint32x4_t(<vscale x 16 x i32> %tuple)
-  ret void
-}
-
-;
-; svint64x4_t
-;
-
-define <vscale x 8 x i64> @ret_svint64x4_t(<vscale x 2 x i64> %unused_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3, <vscale x 2 x i64> %z4) #0 {
-; CHECK-LABEL: ret_svint64x4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3, <vscale x 2 x i64> %z4)
-  ret <vscale x 8 x i64> %tuple
-}
-
-define void @call_svint64x4_t(<vscale x 2 x i64> %dummy_z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %dummy_z3, <vscale x 2 x i64> %z4, <vscale x 2 x i64> %z5) #0 {
-; CHECK-LABEL: call_svint64x4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svint64x4_t
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z4, <vscale x 2 x i64> %z5)
-  call void @callee_svint64x4_t(<vscale x 8 x i64> %tuple)
-  ret void
-}
-
-;
-; svfloatx4_t
-;
-
-define <vscale x 16 x float> @ret_svfloatx4_t(<vscale x 4 x float> %unused_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3, <vscale x 4 x float> %z4) #0 {
-; CHECK-LABEL: ret_svfloatx4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3, <vscale x 4 x float> %z4)
-  ret <vscale x 16 x float> %tuple
-}
-
-define void @call_svfloatx4_t(<vscale x 4 x float> %dummy_z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %dummy_z3, <vscale x 4 x float> %z4, <vscale x 4 x float> %z5) #0 {
-; CHECK-LABEL: call_svfloatx4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svfloatx4_t
-  %tuple = tail call <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z4, <vscale x 4 x float> %z5)
-  call void @callee_svfloatx4_t(<vscale x 16 x float> %tuple)
-  ret void
-}
-
-;
-; svdoublex4_t
-;
-
-define <vscale x 8 x double> @ret_svdoublex4_t(<vscale x 2 x double> %unused_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3, <vscale x 2 x double> %z4) #0 {
-; CHECK-LABEL: ret_svdoublex4_t
-; CHECK:      mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z3.d
-; CHECK-NEXT: mov z3.d, z4.d
-; CHECK-NEXT: ret
-  %tuple = tail call <vscale x 8 x double> @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3, <vscale x 2 x double> %z4)
-  ret <vscale x 8 x double> %tuple
-}
-
-define void @call_svdoublex4_t(<vscale x 2 x double> %dummy_z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %dummy_z3, <vscale x 2 x double> %z4, <vscale x 2 x double> %z5) #0 {
-; CHECK-LABEL: call_svdoublex4_t
-; CHECK:      mov z3.d, z5.d
-; CHECK-NEXT: mov z0.d, z1.d
-; CHECK-NEXT: mov z1.d, z2.d
-; CHECK-NEXT: mov z2.d, z4.d
-; CHECK-NEXT: bl callee_svdoublex4_t
-  %tuple = tail call <vscale x 8 x double> @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64(<vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z4, <vscale x 2 x double> %z5)
-  call void @callee_svdoublex4_t(<vscale x 8 x double> %tuple)
-  ret void
-}
-
-attributes #0 = { nounwind "target-features"="+sve" }
-
-declare void @callee_svint8x2_t(<vscale x 32 x i8>)
-declare void @callee_svint16x2_t(<vscale x 16 x i16>)
-declare void @callee_svint32x2_t(<vscale x 8 x i32>)
-declare void @callee_svint64x2_t(<vscale x 4 x i64>)
-declare void @callee_svfloatx2_t(<vscale x 8 x float>)
-declare void @callee_svdoublex2_t(<vscale x 4 x double>)
-
-declare void @callee_svint8x3_t(<vscale x 48 x i8>)
-declare void @callee_svint16x3_t(<vscale x 24 x i16>)
-declare void @callee_svint32x3_t(<vscale x 12 x i32>)
-declare void @callee_svint64x3_t(<vscale x 6 x i64>)
-declare void @callee_svfloatx3_t(<vscale x 12 x float>)
-declare void @callee_svdoublex3_t(<vscale x 6 x double>)
-
-declare void @callee_svint8x4_t(<vscale x 64 x i8>)
-declare void @callee_svint16x4_t(<vscale x 32 x i16>)
-declare void @callee_svint32x4_t(<vscale x 16 x i32>)
-declare void @callee_svint64x4_t(<vscale x 8 x i64>)
-declare void @callee_svfloatx4_t(<vscale x 16 x float>)
-declare void @callee_svdoublex4_t(<vscale x 8 x double>)
-
-
-; x2
-declare <vscale x 32 x i8> @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 8 x float> @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 4 x double> @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)
-
-; x3
-declare <vscale x 48 x i8> @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
-declare <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 6 x double> @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
-
-; x4
-declare <vscale x 64 x i8> @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
-declare <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 8 x double> @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)

llvm/test/CodeGen/AArch64/sve-extract-subvector.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-
-; Test that DAGCombiner doesn't drop the scalable flag when it tries to fold:
-;   extract_subv (bitcast X), Index --> bitcast (extract_subv X, Index')
-define <vscale x 16 x i8> @extract_nxv16i8_nxv4i64(<vscale x 4 x i64> %z0_z1) {
-; CHECK-LABEL: extract_nxv16i8_nxv4i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %z0_z1_bc = bitcast <vscale x 4 x i64> %z0_z1 to <vscale x 32 x i8>
-  %ext = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv32i8(<vscale x 32 x i8> %z0_z1_bc, i32 1)
-  ret <vscale x 16 x i8> %ext
-}
-
-
-define <vscale x 2 x i64> @extract_nxv2i64_nxv32i8(<vscale x 32 x i8> %z0_z1) {
-; CHECK-LABEL: extract_nxv2i64_nxv32i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %z0_z1_bc = bitcast <vscale x 32 x i8> %z0_z1 to <vscale x 4 x i64>
-  %ext = call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv4i64(<vscale x 4 x i64> %z0_z1_bc, i32 1)
-  ret <vscale x 2 x i64> %ext
-}
-
-define <vscale x 4 x half> @extract_lo_nxv4f16_nxv8f16(<vscale x 8 x half> %z0) {
-; CHECK-LABEL: extract_lo_nxv4f16_nxv8f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 4 x half> @llvm.aarch64.sve.tuple.get.nxv8f16(<vscale x 8 x half> %z0, i32 0)
-  ret <vscale x 4 x half> %ext
-}
-
-define <vscale x 4 x half> @extract_hi_nxv4f16_nxv8f16(<vscale x 8 x half> %z0) {
-; CHECK-LABEL: extract_hi_nxv4f16_nxv8f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    uunpkhi z0.s, z0.h
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 4 x half> @llvm.aarch64.sve.tuple.get.nxv8f16(<vscale x 8 x half> %z0, i32 1)
-  ret <vscale x 4 x half> %ext
-}
-
-define <vscale x 2 x float> @extract_lo_nxv2f32_nxv4f32(<vscale x 4 x float> %z0) {
-; CHECK-LABEL: extract_lo_nxv2f32_nxv4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 2 x float> @llvm.aarch64.sve.tuple.get.nxv4f32(<vscale x 4 x float> %z0, i32 0)
-  ret <vscale x 2 x float> %ext
-}
-
-define <vscale x 2 x float> @extract_hi_nxv2f32_nxv4f32(<vscale x 4 x float> %z0) {
-; CHECK-LABEL: extract_hi_nxv2f32_nxv4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    uunpkhi z0.d, z0.s
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 2 x float> @llvm.aarch64.sve.tuple.get.nxv4f32(<vscale x 4 x float> %z0, i32 1)
-  ret <vscale x 2 x float> %ext
-}
-
-define <vscale x 4 x float> @load_extract_nxv4f32_nxv8f32(<vscale x 8 x float>* %p) {
-; CHECK-LABEL: load_extract_nxv4f32_nxv8f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT:    ret
-  %tmp1 = load <vscale x 8 x float>, <vscale x 8 x float>* %p, align 16
-  %tmp2 = call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv8f32(<vscale x 8 x float> %tmp1, i32 1)
-  ret <vscale x 4 x float> %tmp2
-}
-
-declare <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv4i64(<vscale x 4 x i64>, i32)
-declare <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv32i8(<vscale x 32 x i8>, i32)
-declare <vscale x 2 x float> @llvm.aarch64.sve.tuple.get.nxv4f32(<vscale x 4 x float>, i32)
-declare <vscale x 4 x half> @llvm.aarch64.sve.tuple.get.nxv8f16(<vscale x 8 x half>, i32)
-declare <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv8f32(<vscale x 8 x float>, i32)

llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple aarch64 -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple aarch64 -mattr=+sme < %s | FileCheck %s
-
-;
-; SVCREATE2 (i8)
-;
-
-define <vscale x 16 x i8> @test_svcreate2_s8_vec0(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s8_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB0_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB0_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x i8> @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8(<vscale x 32 x i8> %tuple, i32 0)
-  ret <vscale x 16 x i8> %extract
-}
-
-define <vscale x 16 x i8> @test_svcreate2_s8_vec1(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s8_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB1_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB1_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x i8> @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8(<vscale x 32 x i8> %tuple, i32 1)
-  ret <vscale x 16 x i8> %extract
-}
-
-;
-; SVCREATE2 (i16)
-;
-
-define <vscale x 8 x i16> @test_svcreate2_s16_vec0(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB2_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB2_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16(<vscale x 16 x i16> %tuple, i32 0)
-  ret <vscale x 8 x i16> %extract
-}
-
-define <vscale x 8 x i16> @test_svcreate2_s16_vec1(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s16_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB3_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB3_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16(<vscale x 16 x i16> %tuple, i32 1)
-  ret <vscale x 8 x i16> %extract
-}
-
-;
-; SVCREATE2 (half)
-;
-
-define <vscale x 8 x half> @test_svcreate2_f16_vec0(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB4_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB4_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x half> @llvm.aarch64.sve.tuple.create2.nxv16f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv16f16(<vscale x 16 x half> %tuple, i32 0)
-  ret <vscale x 8 x half> %extract
-}
-
-define <vscale x 8 x half> @test_svcreate2_f16_vec1(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f16_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB5_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB5_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x half> @llvm.aarch64.sve.tuple.create2.nxv16f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv16f16(<vscale x 16 x half> %tuple, i32 1)
-  ret <vscale x 8 x half> %extract
-}
-
-;
-; SVCREATE2 (bfloat)
-;
-
-define <vscale x 8 x bfloat> @test_svcreate2_bf16_vec0(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1) #1 {
-; CHECK-LABEL: test_svcreate2_bf16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB6_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB6_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x bfloat> @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %tuple, i32 0)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-define <vscale x 8 x bfloat> @test_svcreate2_bf16_vec1(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1) #1 {
-; CHECK-LABEL: test_svcreate2_bf16_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB7_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB7_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x bfloat> @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %tuple, i32 1)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-;
-; SVCREATE2 (i32)
-;
-
-define <vscale x 4 x i32> @test_svcreate2_s32_vec0(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB8_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB8_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32(<vscale x 8 x i32> %tuple, i32 0)
-  ret <vscale x 4 x i32> %extract
-}
-
-define <vscale x 4 x i32> @test_svcreate2_s32_vec1(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s32_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB9_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB9_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32(<vscale x 8 x i32> %tuple, i32 1)
-  ret <vscale x 4 x i32> %extract
-}
-
-;
-; SVCREATE2 (float)
-;
-
-define <vscale x 4 x float> @test_svcreate2_f32_vec0(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB10_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB10_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x float> @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv8f32(<vscale x 8 x float> %tuple, i32 0)
-  ret <vscale x 4 x float> %extract
-}
-
-define <vscale x 4 x float> @test_svcreate2_f32_vec1(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f32_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB11_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB11_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x float> @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv8f32(<vscale x 8 x float> %tuple, i32 1)
-  ret <vscale x 4 x float> %extract
-}
-
-;
-; SVCREATE2 (i64)
-;
-
-define <vscale x 2 x i64> @test_svcreate2_s64_vec0(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB12_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB12_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64(<vscale x 4 x i64> %tuple, i32 0)
-  ret <vscale x 2 x i64> %extract
-}
-
-define <vscale x 2 x i64> @test_svcreate2_s64_vec1(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_s64_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB13_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB13_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64(<vscale x 4 x i64> %tuple, i32 1)
-  ret <vscale x 2 x i64> %extract
-}
-
-;
-; SVCREATE2 (double)
-;
-
-define <vscale x 2 x double> @test_svcreate2_f64_vec0(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB14_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB14_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 4 x double> @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %tuple, i32 0)
-  ret <vscale x 2 x double> %extract
-}
-
-define <vscale x 2 x double> @test_svcreate2_f64_vec1(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1) #0 {
-; CHECK-LABEL: test_svcreate2_f64_vec1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB15_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB15_2: // %L2
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 4 x double> @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %tuple, i32 1)
-  ret <vscale x 2 x double> %extract
-}
-
-;
-; SVCREATE3 (i8)
-;
-
-define <vscale x 16 x i8> @test_svcreate3_s8_vec0(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s8_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB16_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB16_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 48 x i8> @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv48i8(<vscale x 48 x i8> %tuple, i32 0)
-  ret <vscale x 16 x i8> %extract
-}
-
-define <vscale x 16 x i8> @test_svcreate3_s8_vec2(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s8_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB17_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB17_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 48 x i8> @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv48i8(<vscale x 48 x i8> %tuple, i32 2)
-  ret <vscale x 16 x i8> %extract
-}
-
-;
-; SVCREATE3 (i16)
-;
-
-define <vscale x 8 x i16> @test_svcreate3_s16_vec0(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB18_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB18_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16(<vscale x 24 x i16> %tuple, i32 0)
-  ret <vscale x 8 x i16> %extract
-}
-
-define <vscale x 8 x i16> @test_svcreate3_s16_vec2(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s16_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB19_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB19_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16(<vscale x 24 x i16> %tuple, i32 2)
-  ret <vscale x 8 x i16> %extract
-}
-
-;
-; SVCREATE3 (half)
-;
-
-define <vscale x 8 x half> @test_svcreate3_f16_vec0(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB20_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB20_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x half> @llvm.aarch64.sve.tuple.create3.nxv24f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv24f16(<vscale x 24 x half> %tuple, i32 0)
-  ret <vscale x 8 x half> %extract
-}
-
-define <vscale x 8 x half> @test_svcreate3_f16_vec2(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f16_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB21_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB21_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x half> @llvm.aarch64.sve.tuple.create3.nxv24f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv24f16(<vscale x 24 x half> %tuple, i32 2)
-  ret <vscale x 8 x half> %extract
-}
-
-;
-; SVCREATE3 (bfloat)
-;
-
-define <vscale x 8 x bfloat> @test_svcreate3_bf16_vec0(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2) #1 {
-; CHECK-LABEL: test_svcreate3_bf16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB22_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB22_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x bfloat> @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16(<vscale x 24 x bfloat> %tuple, i32 0)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-define <vscale x 8 x bfloat> @test_svcreate3_bf16_vec2(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2) #1 {
-; CHECK-LABEL: test_svcreate3_bf16_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB23_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB23_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x bfloat> @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16(<vscale x 24 x bfloat> %tuple, i32 2)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-;
-; SVCREATE3 (i32)
-;
-
-define <vscale x 4 x i32> @test_svcreate3_s32_vec0(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB24_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB24_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv12i32(<vscale x 12 x i32> %tuple, i32 0)
-  ret <vscale x 4 x i32> %extract
-}
-
-define <vscale x 4 x i32> @test_svcreate3_s32_vec2(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s32_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB25_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB25_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv12i32(<vscale x 12 x i32> %tuple, i32 2)
-  ret <vscale x 4 x i32> %extract
-}
-
-;
-; SVCREATE3 (float)
-;
-
-define <vscale x 4 x float> @test_svcreate3_f32_vec0(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB26_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB26_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv12f32(<vscale x 12 x float> %tuple, i32 0)
-  ret <vscale x 4 x float> %extract
-}
-
-define <vscale x 4 x float> @test_svcreate3_f32_vec2(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f32_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB27_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB27_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv12f32(<vscale x 12 x float> %tuple, i32 2)
-  ret <vscale x 4 x float> %extract
-}
-
-;
-; SVCREATE3 (i64)
-;
-
-define <vscale x 2 x i64> @test_svcreate3_s64_vec0(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB28_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB28_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv6i64(<vscale x 6 x i64> %tuple, i32 0)
-  ret <vscale x 2 x i64> %extract
-}
-
-define <vscale x 2 x i64> @test_svcreate3_s64_vec2(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_s64_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB29_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB29_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv6i64(<vscale x 6 x i64> %tuple, i32 2)
-  ret <vscale x 2 x i64> %extract
-}
-
-;
-; SVCREATE3 (double)
-;
-
-define <vscale x 2 x double> @test_svcreate3_f64_vec0(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB30_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB30_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x double> @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv6f64(<vscale x 6 x double> %tuple, i32 0)
-  ret <vscale x 2 x double> %extract
-}
-
-define <vscale x 2 x double> @test_svcreate3_f64_vec2(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2) #0 {
-; CHECK-LABEL: test_svcreate3_f64_vec2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB31_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB31_2: // %L2
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x double> @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv6f64(<vscale x 6 x double> %tuple, i32 2)
-  ret <vscale x 2 x double> %extract
-}
-
-;
-; SVCREATE4 (i8)
-;
-
-define <vscale x 16 x i8> @test_svcreate4_s8_vec0(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s8_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB32_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB32_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %tuple, i32 0)
-  ret <vscale x 16 x i8> %extract
-}
-
-define <vscale x 16 x i8> @test_svcreate4_s8_vec3(i1 %p, <vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s8_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB33_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB33_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8> %z0, <vscale x 16 x i8> %z1, <vscale x 16 x i8> %z2, <vscale x 16 x i8> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 16 x i8> undef
-L2:
-  %extract = tail call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %tuple, i32 3)
-  ret <vscale x 16 x i8> %extract
-}
-
-;
-; SVCREATE4 (i16)
-;
-
-define <vscale x 8 x i16> @test_svcreate4_s16_vec0(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB34_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB34_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv32i16(<vscale x 32 x i16> %tuple, i32 0)
-  ret <vscale x 8 x i16> %extract
-}
-
-define <vscale x 8 x i16> @test_svcreate4_s16_vec3(i1 %p, <vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s16_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB35_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB35_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16> %z0, <vscale x 8 x i16> %z1, <vscale x 8 x i16> %z2, <vscale x 8 x i16> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x i16> undef
-L2:
-  %extract = tail call <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv32i16(<vscale x 32 x i16> %tuple, i32 3)
-  ret <vscale x 8 x i16> %extract
-}
-
-;
-; SVCREATE4 (half)
-;
-
-define <vscale x 8 x half> @test_svcreate4_f16_vec0(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2, <vscale x 8 x half> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB36_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB36_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x half> @llvm.aarch64.sve.tuple.create4.nxv32f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2, <vscale x 8 x half> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv32f16(<vscale x 32 x half> %tuple, i32 0)
-  ret <vscale x 8 x half> %extract
-}
-
-define <vscale x 8 x half> @test_svcreate4_f16_vec3(i1 %p, <vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2, <vscale x 8 x half> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f16_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB37_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB37_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x half> @llvm.aarch64.sve.tuple.create4.nxv32f16.nxv8f16(<vscale x 8 x half> %z0, <vscale x 8 x half> %z1, <vscale x 8 x half> %z2, <vscale x 8 x half> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x half> undef
-L2:
-  %extract = tail call <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv32f16(<vscale x 32 x half> %tuple, i32 3)
-  ret <vscale x 8 x half> %extract
-}
-
-;
-; SVCREATE4 (bfloat)
-;
-
-define <vscale x 8 x bfloat> @test_svcreate4_bf16_vec0(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2, <vscale x 8 x bfloat> %z3) #1 {
-; CHECK-LABEL: test_svcreate4_bf16_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB38_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB38_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x bfloat> @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2, <vscale x 8 x bfloat> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %tuple, i32 0)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-define <vscale x 8 x bfloat> @test_svcreate4_bf16_vec3(i1 %p, <vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2, <vscale x 8 x bfloat> %z3) #1 {
-; CHECK-LABEL: test_svcreate4_bf16_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB39_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB39_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 32 x bfloat> @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16(<vscale x 8 x bfloat> %z0, <vscale x 8 x bfloat> %z1, <vscale x 8 x bfloat> %z2, <vscale x 8 x bfloat> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 8 x bfloat> undef
-L2:
-  %extract = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %tuple, i32 3)
-  ret <vscale x 8 x bfloat> %extract
-}
-
-;
-; SVCREATE4 (i32)
-;
-
-define <vscale x 4 x i32> @test_svcreate4_s32_vec0(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB40_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB40_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 x i32> %tuple, i32 0)
-  ret <vscale x 4 x i32> %extract
-}
-
-define <vscale x 4 x i32> @test_svcreate4_s32_vec3(i1 %p, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s32_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB41_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB41_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x i32> undef
-L2:
-  %extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 x i32> %tuple, i32 3)
-  ret <vscale x 4 x i32> %extract
-}
-
-;
-; SVCREATE4 (float)
-;
-
-define <vscale x 4 x float> @test_svcreate4_f32_vec0(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f32_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB42_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB42_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv16f32(<vscale x 16 x float> %tuple, i32 0)
-  ret <vscale x 4 x float> %extract
-}
-
-define <vscale x 4 x float> @test_svcreate4_f32_vec3(i1 %p, <vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f32_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB43_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB43_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float> %z0, <vscale x 4 x float> %z1, <vscale x 4 x float> %z2, <vscale x 4 x float> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 4 x float> undef
-L2:
-  %extract = tail call <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv16f32(<vscale x 16 x float> %tuple, i32 3)
-  ret <vscale x 4 x float> %extract
-}
-
-;
-; SVCREATE4 (i64)
-;
-
-define <vscale x 2 x i64> @test_svcreate4_s64_vec0(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB44_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB44_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x i64> %tuple, i32 0)
-  ret <vscale x 2 x i64> %extract
-}
-
-define <vscale x 2 x i64> @test_svcreate4_s64_vec3(i1 %p, <vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_s64_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB45_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB45_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %z0, <vscale x 2 x i64> %z1, <vscale x 2 x i64> %z2, <vscale x 2 x i64> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x i64> undef
-L2:
-  %extract = tail call <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x i64> %tuple, i32 3)
-  ret <vscale x 2 x i64> %extract
-}
-
-;
-; SVCREATE4 (double)
-;
-
-define <vscale x 2 x double> @test_svcreate4_f64_vec0(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f64_vec0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB46_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    // implicit-def: $z0
-; CHECK-NEXT:  .LBB46_2: // %L2
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x double> @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv8f64(<vscale x 8 x double> %tuple, i32 0)
-  ret <vscale x 2 x double> %extract
-}
-
-define <vscale x 2 x double> @test_svcreate4_f64_vec3(i1 %p, <vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3) #0 {
-; CHECK-LABEL: test_svcreate4_f64_vec3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    tbz w0, #0, .LBB47_2
-; CHECK-NEXT:  // %bb.1: // %common.ret
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB47_2: // %L2
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x double> @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64(<vscale x 2 x double> %z0, <vscale x 2 x double> %z1, <vscale x 2 x double> %z2, <vscale x 2 x double> %z3)
-  br i1 %p, label %L1, label %L2
-L1:
-  ret <vscale x 2 x double> undef
-L2:
-  %extract = tail call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv8f64(<vscale x 8 x double> %tuple, i32 3)
-  ret <vscale x 2 x double> %extract
-}
-
-attributes #0 = { nounwind }
-; +bf16 is required for the bfloat version.
-attributes #1 = { nounwind "target-features"="+bf16" }
-
-declare <vscale x 4 x double>  @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)
-declare <vscale x 8 x float>  @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 16 x half>  @llvm.aarch64.sve.tuple.create2.nxv16f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 16 x bfloat>  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
-declare <vscale x 4 x i64>  @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 8 x i32>  @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 32 x i8>  @llvm.aarch64.sve.tuple.create2.nxv32i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-
-declare <vscale x 6 x double>  @llvm.aarch64.sve.tuple.create3.nxv6f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
-declare <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 24 x half> @llvm.aarch64.sve.tuple.create3.nxv24f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 24 x bfloat> @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
-declare <vscale x 6 x i64>  @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 48 x i8>  @llvm.aarch64.sve.tuple.create3.nxv48i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
-
-declare <vscale x 8 x double>  @llvm.aarch64.sve.tuple.create4.nxv8f64.nxv2f64 (<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
-declare <vscale x 16 x float>  @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 32 x half>  @llvm.aarch64.sve.tuple.create4.nxv32f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 32 x bfloat>  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
-declare <vscale x  8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 32 x i16> @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 64 x i8>  @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
-
-declare <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8(<vscale x 32 x i8>, i32 immarg)
-declare <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv48i8(<vscale x 48 x i8>, i32 immarg)
-declare <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8>, i32 immarg)
-
-declare <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16(<vscale x 16 x i16>, i32 immarg)
-declare <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16(<vscale x 24 x i16>, i32 immarg)
-declare <vscale x 8 x i16> @llvm.aarch64.sve.tuple.get.nxv8i16.nxv32i16(<vscale x 32 x i16>, i32 immarg)
-
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32(<vscale x 8 x i32>, i32 immarg)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv12i32(<vscale x 12 x i32>, i32 immarg)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 x i32>, i32 immarg)
-
-declare <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64(<vscale x 4 x i64>, i32 immarg)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv6i64(<vscale x 6 x i64>, i32 immarg)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.tuple.get.nxv2i64.nxv8i64(<vscale x 8 x i64>, i32 immarg)
-
-declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i32 immarg)
-declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16(<vscale x 24 x bfloat>, i32 immarg)
-declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i32 immarg)
-
-declare <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv16f16(<vscale x 16 x half>, i32 immarg)
-declare <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv24f16(<vscale x 24 x half>, i32 immarg)
-declare <vscale x 8 x half> @llvm.aarch64.sve.tuple.get.nxv8f16.nxv32f16(<vscale x 32 x half>, i32 immarg)
-
-declare <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv8f32(<vscale x 8 x float>, i32 immarg)
-declare <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv12f32(<vscale x 12 x float>, i32 immarg)
-declare <vscale x 4 x float> @llvm.aarch64.sve.tuple.get.nxv4f32.nxv16f32(<vscale x 16 x float>, i32 immarg)
-
-declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double>, i32 immarg)
-declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv6f64(<vscale x 6 x double>, i32 immarg)
-declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv8f64(<vscale x 8 x double>, i32 immarg)

llvm/test/CodeGen/AArch64/sve-intrinsics-insert-extract-tuple.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple aarch64 -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple aarch64 -mattr=+sme < %s | FileCheck %s
-
-; All these tests create a vector tuple, insert z5 into one of the elements,
-; and finally extracts that element from the wide vector to return it.  These
-; checks ensure that z5 is always the value that is returned.
-
-;
-; Insert into two element tuples
-;
-
-; tuple:      { tuple2.res0, tuple2.res1 }
-; insert z5:  {     z5     , tuple2.res1 }
-; extract z5:       ^^
-define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple2_nxv8i32_elt0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
-  %ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 0)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple2.res0, tuple2.res1 }
-; insert z5:   { tuple2.res0,     z5      }
-; extract z5:                     ^^
-define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple2_nxv8i32_elt1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
-  %ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 1)
-  ret <vscale x 4 x i32> %ext
-}
-
-; This test checks the elements _not_ being set aren't changed.
-
-; tuple:       { tuple2.res0, tuple2.res1 }
-; insert z5:   { tuple2.res0,     z5      }
-; extract z0:         ^^
-define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt1_ret_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple2_nxv8i32_elt1_ret_elt0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
-  %ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 0)
-  ret <vscale x 4 x i32> %ext
-}
-
-; Test extract of tuple passed into function
-define <vscale x 4 x i32> @get_tuple2_nxv8i32_elt1(<vscale x 8 x i32> %tuple) {
-; CHECK-LABEL: get_tuple2_nxv8i32_elt1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z1.d
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %tuple, i32 1)
-  ret <vscale x 4 x i32> %ext
-}
-
-;
-; Insert into three element tuples
-;
-
-; tuple:       { tuple3.res0, tuple3.res1, tuple3.res2 }
-; insert z5:   {     z5     , tuple3.res0, tuple3.res2 }
-; extract z5:        ^^
-define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple3_nxv12i32_elt0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  %ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 0)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple3.res0, tuple3.res1, tuple3.res2 }
-; insert z5:   { tuple3.res0,     z5     , tuple3.res2 }
-; extract z5:                     ^^
-define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple3_nxv12i32_elt1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  %ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 1)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple3.res0, tuple3.res1, tuple3.res2 }
-; insert z5:   { tuple3.res0, tuple3.res1,     z5      }
-; extract z5:                                  ^^
-define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple3_nxv12i32_elt2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  %ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 2, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 2)
-  ret <vscale x 4 x i32> %ext
-}
-
-; This test checks the elements _not_ being set aren't changed.
-
-; tuple:       { tuple3.res0, tuple3.res1, tuple3.res2 }
-; insert z5:   { tuple3.res0,     z5     , tuple3.res2 }
-; extract z2:                                  ^^
-define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt1_ret_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple3_nxv12i32_elt1_ret_elt2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
-  %ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 2)
-  ret <vscale x 4 x i32> %ext
-}
-
-; Test extract of tuple passed into function
-define <vscale x 4 x i32> @get_tuple3_nxv12i32_elt2(<vscale x 4 x i32> %z0, <vscale x 12 x i32> %tuple) {
-; CHECK-LABEL: get_tuple3_nxv12i32_elt2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %tuple, i32 2)
-  ret <vscale x 4 x i32> %ext
-}
-
-;
-; Insert into four element tuples
-;
-
-; tuple:       { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
-; insert z5:   {     z5     , tuple4.res1, tuple4.res2, tuple4.res3 }
-; extract z5:        ^^
-define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple4_nxv16i32_elt0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  %ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 0)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
-; insert z5:   { tuple4.res0,     z5     , tuple4.res2, tuple4.res3 }
-; extract z5:                     ^^
-define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple4_nxv16i32_elt1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  %ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 1)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
-; insert z5:   { tuple4.res0, tuple4.res1,     z5     , tuple4.res3 }
-; extract z5:                                  ^^
-define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple4_nxv16i32_elt2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  %ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 2, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 2)
-  ret <vscale x 4 x i32> %ext
-}
-
-; tuple:       { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
-; insert z5:   { tuple4.res0, tuple4.res1, tuple4.res2,     z5      }
-; extract z5:                                               ^^
-define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt3(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple4_nxv16i32_elt3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z5.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  %ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 3, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 3)
-  ret <vscale x 4 x i32> %ext
-}
-
-; This test checks the elements _not_ being set aren't changed.
-
-; tuple:       { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
-; insert z5:   { tuple4.res0, tuple4.res1, tuple4.res2,     z5      }
-; extract z2:                                               ^^
-define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt3_ret_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) {
-; CHECK-LABEL: set_tuple4_nxv16i32_elt3_ret_elt2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
-  %ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 3, <vscale x 4 x i32> %z5)
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 2)
-  ret <vscale x 4 x i32> %ext
-}
-
-; Test extract of tuple passed into function
-define <vscale x 4 x i32> @get_tuple4_nxv16i32_elt3(<vscale x 16 x i32> %tuple) {
-; CHECK-LABEL: get_tuple4_nxv16i32_elt3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, z3.d
-; CHECK-NEXT:    ret
-  %ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %tuple, i32 3)
-  ret <vscale x 4 x i32> %ext
-}
-
-declare <vscale x 8 x i32>  @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32>, i32, <vscale x 4 x i32>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32>, i32)
-
-declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32>, i32, <vscale x 4 x i32>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32>, i32)
-
-declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32>, i32, <vscale x 4 x i32>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32>, i32)

llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uqsub z0.d, z0.d, z1.d
 ; CHECK-NEXT:    ret
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a,
                                                                    <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
-; ADD (tuples)
-
-define <vscale x 4 x i64> @add_i64_tuple2(<vscale x 4 x i64>* %out, <vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2) {
-; CHECK-LABEL: add_i64_tuple2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    add z0.d, z0.d, z0.d
-; CHECK-NEXT:    add z1.d, z1.d, z1.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2)
-  %res = add <vscale x 4 x i64> %tuple, %tuple
-  ret <vscale x 4 x i64> %res
-}
-
-define <vscale x 6 x i64> @add_i64_tuple3(<vscale x 6 x i64>* %out, <vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3) {
-; CHECK-LABEL: add_i64_tuple3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    add z1.d, z1.d, z1.d
-; CHECK-NEXT:    add z0.d, z0.d, z0.d
-; CHECK-NEXT:    add z2.d, z2.d, z2.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3)
-  %res = add <vscale x 6 x i64> %tuple, %tuple
-  ret <vscale x 6 x i64> %res
-}
-
-define <vscale x 8 x i64> @add_i64_tuple4(<vscale x 8 x i64>* %out, <vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3, <vscale x 2 x i64> %in4) {
-; CHECK-LABEL: add_i64_tuple4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    add z2.d, z2.d, z2.d
-; CHECK-NEXT:    add z0.d, z0.d, z0.d
-; CHECK-NEXT:    add z1.d, z1.d, z1.d
-; CHECK-NEXT:    add z3.d, z3.d, z3.d
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3, <vscale x 2 x i64> %in4)
-  %res = add <vscale x 8 x i64> %tuple, %tuple
-  ret <vscale x 8 x i64> %res
-}
-
-
 declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
 declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
 
 declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
 declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)

 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
 
 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
 
-declare <vscale x 4 x i64> @llvm.aarch64.sve.tuple.create2.nxv4i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)

llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
                                             <vscale x 2 x i1> %pred,
                                             double* %addr)
   ret void
 }
 
 
-; Stores (tuples)
-
-define void @store_i64_tuple3(<vscale x 6 x i64>* %out, <vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3) {
-; CHECK-LABEL: store_i64_tuple3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3)
-  store <vscale x 6 x i64> %tuple, <vscale x 6 x i64>* %out
-  ret void
-}
-
-define void @store_i64_tuple4(<vscale x 8 x i64>* %out, <vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3, <vscale x 2 x i64> %in4) {
-; CHECK-LABEL: store_i64_tuple4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #3, mul vl]
-; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3, <vscale x 2 x i64> %in4)
-  store <vscale x 8 x i64> %tuple, <vscale x 8 x i64>* %out
-  ret void
-}
-
-define void @store_i16_tuple2(<vscale x 16 x i16>* %out, <vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2) {
-; CHECK-LABEL: store_i16_tuple2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    st1h { z1.h }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2)
-  store <vscale x 16 x i16> %tuple, <vscale x 16 x i16>* %out
-  ret void
-}
-
-define void @store_i16_tuple3(<vscale x 24 x i16>* %out, <vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2, <vscale x 8 x i16> %in3) {
-; CHECK-LABEL: store_i16_tuple3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    st1h { z2.h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2, <vscale x 8 x i16> %in3)
-  store <vscale x 24 x i16> %tuple, <vscale x 24 x i16>* %out
-  ret void
-}
-
-define void @store_f32_tuple3(<vscale x 12 x float>* %out, <vscale x 4 x float> %in1, <vscale x 4 x float> %in2, <vscale x 4 x float> %in3) {
-; CHECK-LABEL: store_f32_tuple3:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    st1w { z2.s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float> %in1, <vscale x 4 x float> %in2, <vscale x 4 x float> %in3)
-  store <vscale x 12 x float> %tuple, <vscale x 12 x float>* %out
-  ret void
-}
-
-define void @store_f32_tuple4(<vscale x 16 x float>* %out, <vscale x 4 x float> %in1, <vscale x 4 x float> %in2, <vscale x 4 x float> %in3, <vscale x 4 x float> %in4) {
-; CHECK-LABEL: store_f32_tuple4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    st1w { z3.s }, p0, [x0, #3, mul vl]
-; CHECK-NEXT:    st1w { z2.s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
-; CHECK-NEXT:    ret
-  %tuple = tail call <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float> %in1, <vscale x 4 x float> %in2, <vscale x 4 x float> %in3, <vscale x 4 x float> %in4)
-  store <vscale x 16 x float> %tuple, <vscale x 16 x float>* %out
-  ret void
-}
-
 declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
 declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
 declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
 declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
 declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
 declare void @llvm.aarch64.sve.st2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
 declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
 declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)

 declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
 declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
 declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
 declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
 declare void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
 declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
 declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)
 
-declare <vscale x 6 x i64> @llvm.aarch64.sve.tuple.create3.nxv6i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 8 x i64> @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
-
-declare <vscale x 16 x i16> @llvm.aarch64.sve.tuple.create2.nxv16i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 24 x i16> @llvm.aarch64.sve.tuple.create3.nxv24i16.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
-
-declare <vscale x 12 x float> @llvm.aarch64.sve.tuple.create3.nxv12f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 16 x float> @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
-
 ; +bf16 is required for the bfloat version.
 attributes #0 = { "target-features"="+bf16" }

llvm/test/CodeGen/AArch64/sve-merging-stores.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 %complex = type { { double, double } }
 
 ; Function Attrs: argmemonly nounwind readonly
-declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double>, i32 immarg) #3
+declare <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double>, i64 immarg) #3
 
 ; Function Attrs: argmemonly nounwind readonly
 declare <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1(<vscale x 2 x i1>, double*) #3
 
 ; Function Attrs: nounwind readnone
 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
 
 define void @foo1(%complex* %outval, <vscale x 2 x i1> %pred, double *%inptr) {
 ; CHECK-LABEL: foo1:
 ; CHECK: ld2d { z0.d, z1.d }, p0/z, [x1]
 ; CHECK-NEXT: faddv d2, p0, z0.d
 ; CHECK-NEXT: faddv d0, p0, z1.d
 ; CHECK-NEXT: mov v2.d[1], v0.d[0]
 ; CHECK-NEXT: str q2, [x0]
   %realp = getelementptr inbounds %complex, %complex* %outval, i64 0, i32 0, i32 0
   %imagp = getelementptr inbounds %complex, %complex* %outval, i64 0, i32 0, i32 1
   %1 = call <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1(<vscale x 2 x i1> %pred, double* nonnull %inptr)
-  %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i32 0)
+  %2 = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i64 0)
   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %2)
-  %4 = call <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i32 1)
+  %4 = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> %1, i64 2)
   %5 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %4)
   store double %3, double* %realp, align 8
   store double %5, double* %imagp, align 8
   ret void
 }
 

llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-tuple-get.ll

-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=instcombine < %s | FileCheck %s
-
-target triple = "aarch64-unknown-linux-gnu"
-
-; This stores %a using st4 after reversing the 4 tuples. Check that the
-; redundant sequences of get/set are eliminated.
-define void @redundant_tuple_get_set(<vscale x 64 x i8> %a, i8* %ptr) #0 {
-; CHECK-LABEL: @redundant_tuple_get_set(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> [[A:%.*]], i32 3)
-; CHECK-NEXT:    [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> [[A]], i32 0)
-; CHECK-NEXT:    [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> [[A]], i32 2)
-; CHECK-NEXT:    [[TMP4:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> [[A]], i32 1)
-; CHECK-NEXT:    call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP4]], <vscale x 16 x i8> [[TMP2]], <vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i32 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer), i8* [[PTR:%.*]])
-; CHECK-NEXT:    ret void
-;
-  %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %a, i32 3)
-  %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %a, i32 0)
-  %3 = call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.set.nxv64i8.nxv16i8(<vscale x 64 x i8> %a, i32 3, <vscale x 16 x i8> %2)
-  %4 = call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.set.nxv64i8.nxv16i8(<vscale x 64 x i8> %3, i32 0, <vscale x 16 x i8> %1)
-  %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %4, i32 2)
-  %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %4, i32 1)
-  %7 = call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.set.nxv64i8.nxv16i8(<vscale x 64 x i8> %4, i32 2, <vscale x 16 x i8> %6)
-  %8 = call <vscale x 64 x i8> @llvm.aarch64.sve.tuple.set.nxv64i8.nxv16i8(<vscale x 64 x i8> %7, i32 1, <vscale x 16 x i8> %5)
-  %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %8, i32 0)
-  %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %8, i32 1)
-  %11 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %8, i32 2)
-  %12 = call <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8> %8, i32 3)
-  call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i32 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer), i8* %ptr)
-  ret void
-}
-
-declare <vscale x 64 x i8> @llvm.aarch64.sve.tuple.set.nxv64i8.nxv16i8(<vscale x 64 x i8>, i32, <vscale x 16 x i8>)
-declare <vscale x 16 x i8> @llvm.aarch64.sve.tuple.get.nxv16i8.nxv64i8(<vscale x 64 x i8>, i32)
-declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
-
-attributes #0 = { "target-features"="+sve" }

llvm/test/Transforms/InstCombine/opts-tuples-extract-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+
+; Check that the redundant sequences of extract/insert are eliminated.
+
+; extract.vector(insert.vector(Tuple, Value, Idx), Idx) --> Value
+define <vscale x 16 x i8> @test_extract_insert_same_idx(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1) {
+; CHECK-LABEL: @test_extract_insert_same_idx(
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[V1:%.*]]
+;
+  %vec.ins = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1, i64 48)
+  %vec.ext = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %vec.ins, i64 48)
+  ret <vscale x 16 x i8> %vec.ext
+}
+
+; extract.vector(insert.vector(Vector, Value, InsertIndex), ExtractIndex)
+;  --> extract.vector(Vector, ExtractIndex)
+define <vscale x 16 x i8> @test_extract_insert_dif_idx(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1) {
+; CHECK-LABEL: @test_extract_insert_dif_idx(
+; CHECK-NEXT:    [[VEC_EXT:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[V0:%.*]], i64 0)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[VEC_EXT]]
+;
+  %vec.ins = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1, i64 48)
+  %vec.ext = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %vec.ins, i64 0)
+  ret <vscale x 16 x i8> %vec.ext
+}
+
+; Negative test
+; The extracted vector-size != inserted vector-size
+define <vscale x 32 x i8> @neg_test_extract_insert_same_idx_dif_ret_size(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1) {
+; CHECK-LABEL: @neg_test_extract_insert_same_idx_dif_ret_size(
+; CHECK-NEXT:    [[VEC_INS:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[V0:%.*]], <vscale x 16 x i8> [[V1:%.*]], i64 32)
+; CHECK-NEXT:    [[VEC_EXT:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[VEC_INS]], i64 32)
+; CHECK-NEXT:    ret <vscale x 32 x i8> [[VEC_EXT]]
+;
+  %vec.ins = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %v0, <vscale x 16 x i8> %v1, i64 32)
+  %vec.ext = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %vec.ins, i64 32)
+  ret <vscale x 32 x i8> %vec.ext
+}
+
+
+declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64)
+declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64)
+declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64)
+