[X86] (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.

[deadalnix]

Summary

This adresses various regression in D131260 , as well as is a useful optimization in itself.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

48437

Can you improve this comment? The codegen doesn't seem to pattern matching below.

48445

auto *CN =

[deadalnix]

Update comment and use auto

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

48439

Limit this to legal i32/i64 cases? Add test coverage for other types as well.

48455

Not sure if we should use X86ISD::MUL_IMM here?

[deadalnix]

llvm/lib/Target/X86/X86ISelLowering.cpp

48439

That make sense.

48455

combineSelectOfTwoContants uses a mul, so I did the same.

[deadalnix]

• Limit the transform to 32bits and 64bits.
• Add 64 bits test cases.

[RKSimon]

Alive2: https://alive2.llvm.org/ce/z/XFyAFx

[deadalnix]

Alive is happy with the correctness of the transform, should we land this or are there extra concerns to be addressed?

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

     return R;
 
   if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
     return R;
 
   if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
     return R;
 
+  // (sext Cond) | C -> (zext (not Cond)) * (C + 1) - 1 if we can get a LEA out of it.
+  if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
+        isNullConstant(N0.getOperand(0))) {
+    SDValue Cond = N0.getOperand(1);
+    if (Cond.getOpcode() == ISD::ZERO_EXTEND && Cond.hasOneUse())
+      Cond = Cond.getOperand(0);
+
+    if (Cond.getOpcode() == X86ISD::SETCC && Cond.hasOneUse()) {
+      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N1)) {
+        unsigned Val = CN->getZExtValue();
+        if (Val == 1 || Val == 2 || Val == 3 || Val == 4 || Val == 7 || Val == 8) {
+          unsigned Scale = Val + 1;
+
+          X86::CondCode CCode = (X86::CondCode)Cond.getConstantOperandVal(0);
+          CCode = X86::GetOppositeBranchCondition(CCode);
+          SDValue NotCond = getSETCC(CCode, Cond.getOperand(1), SDLoc(Cond), DAG);
+
+          SDValue R = DAG.getZExtOrTrunc(NotCond, dl, VT);
+          R = DAG.getNode(ISD::MUL, dl, VT, R, DAG.getConstant(Scale, dl, VT));
+          R = DAG.getNode(ISD::SUB, dl, VT, R, DAG.getConstant(1, dl, VT));
+          return R;
+        }
+      }
+    }
+  }
+
   // Combine OR(X,KSHIFTL(Y,Elts/2)) -> CONCAT_VECTORS(X,Y) == KUNPCK(X,Y).
   // Combine OR(KSHIFTL(X,Elts/2),Y) -> CONCAT_VECTORS(Y,X) == KUNPCK(Y,X).
   // iff the upper elements of the non-shifted arg are zero.
   // KUNPCK require 16+ bool vector elements.
   if (N0.getOpcode() == X86ISD::KSHIFTL || N1.getOpcode() == X86ISD::KSHIFTL) {
     unsigned NumElts = VT.getVectorNumElements();
     unsigned HalfElts = NumElts / 2;
     APInt UpperElts = APInt::getHighBitsSet(NumElts, HalfElts);

llvm/test/CodeGen/X86/or-lea.ll

entry:
   ret i64 %inc
 }
 
 define i32 @or_sext1(i32 %x) {
 ; CHECK-LABEL: or_sext1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $1, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(%rax,%rax), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 1
   ret i32 %or
 }
 
 define i32 @or_sext2(i32 %x) {
 ; CHECK-LABEL: or_sext2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $2, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(%rax,%rax,2), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 2
   ret i32 %or
 }
 
 define i32 @or_sext3(i32 %x) {
 ; CHECK-LABEL: or_sext3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $3, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(,%rax,4), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 3
   ret i32 %or
 }
 
 define i32 @or_sext4(i32 %x) {
 ; CHECK-LABEL: or_sext4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $4, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(%rax,%rax,4), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 4
   ret i32 %or
 }
 
 define i32 @or_sext7(i32 %x) {
 ; CHECK-LABEL: or_sext7:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $7, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(,%rax,8), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 7
   ret i32 %or
 }
 
 define i32 @or_sext8(i32 %x) {
 ; CHECK-LABEL: or_sext8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $43, %edi
-; CHECK-NEXT:    setge %al
-; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    orl $8, %eax
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    leal -1(%rax,%rax,8), %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 8
   ret i32 %or
 }