[X86] (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.

[deadalnix]

Summary

This adresses various regression in D131260 , as well as is a useful optimization in itself.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

48437

Can you improve this comment? The codegen doesn't seem to pattern matching below.

48445

auto *CN =

[deadalnix]

Update comment and use auto

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

48439

Limit this to legal i32/i64 cases? Add test coverage for other types as well.

48455

Not sure if we should use X86ISD::MUL_IMM here?

[deadalnix]

llvm/lib/Target/X86/X86ISelLowering.cpp

48439

That make sense.

48455

combineSelectOfTwoContants uses a mul, so I did the same.

[deadalnix]

• Limit the transform to 32bits and 64bits.
• Add 64 bits test cases.

[RKSimon]

Alive2: https://alive2.llvm.org/ce/z/XFyAFx

[deadalnix]

Alive is happy with the correctness of the transform, should we land this or are there extra concerns to be addressed?

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

 }
 
 static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
                          TargetLowering::DAGCombinerInfo &DCI,
                          const X86Subtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
   SDLoc dl(N);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
   // If this is SSE1 only convert to FOR to avoid scalarization.
   if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) {
     return DAG.getBitcast(MVT::v4i32,
                           DAG.getNode(X86ISD::FOR, dl, MVT::v4f32,
                                       DAG.getBitcast(MVT::v4f32, N0),
                                       DAG.getBitcast(MVT::v4f32, N1)));
   }
 
   // Match any-of bool scalar reductions into a bitcast/movmsk + cmp.
   // TODO: Support multiple SrcOps.
   if (VT == MVT::i1) {
     SmallVector<SDValue, 2> SrcOps;
     SmallVector<APInt, 2> SrcPartials;
     if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps, &SrcPartials) &&
         SrcOps.size() == 1) {
       unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
       EVT MaskVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
       SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget);
       if (!Mask && TLI.isTypeLegal(SrcOps[0].getValueType()))
         Mask = DAG.getBitcast(MaskVT, SrcOps[0]);
       if (Mask) {
         assert(SrcPartials[0].getBitWidth() == NumElts &&
                "Unexpected partial reduction mask");
         SDValue ZeroBits = DAG.getConstant(0, dl, MaskVT);
if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
     return R;
 
   if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
     return R;
 
   if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
     return R;
 
+  // (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.
+  if ((VT == MVT::i32 || VT == MVT::i64) &&
+      N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
+      isNullConstant(N0.getOperand(0))) {
+    SDValue Cond = N0.getOperand(1);
+    if (Cond.getOpcode() == ISD::ZERO_EXTEND && Cond.hasOneUse())
+      Cond = Cond.getOperand(0);
+
+    if (Cond.getOpcode() == X86ISD::SETCC && Cond.hasOneUse()) {
+      if (auto *CN = dyn_cast<ConstantSDNode>(N1)) {
+        unsigned Val = CN->getZExtValue();
+        if (Val == 1 || Val == 2 || Val == 3 || Val == 4 || Val == 7 || Val == 8) {
+          X86::CondCode CCode = (X86::CondCode)Cond.getConstantOperandVal(0);
+          CCode = X86::GetOppositeBranchCondition(CCode);
+          SDValue NotCond = getSETCC(CCode, Cond.getOperand(1), SDLoc(Cond), DAG);
+
+          SDValue R = DAG.getZExtOrTrunc(NotCond, dl, VT);
+          R = DAG.getNode(ISD::MUL, dl, VT, R, DAG.getConstant(Val + 1, dl, VT));
+          R = DAG.getNode(ISD::SUB, dl, VT, R, DAG.getConstant(1, dl, VT));
+          return R;
+        }
+      }
+    }
+  }
+
   // Combine OR(X,KSHIFTL(Y,Elts/2)) -> CONCAT_VECTORS(X,Y) == KUNPCK(X,Y).
   // Combine OR(KSHIFTL(X,Elts/2),Y) -> CONCAT_VECTORS(Y,X) == KUNPCK(Y,X).
   // iff the upper elements of the non-shifted arg are zero.
   // KUNPCK require 16+ bool vector elements.
   if (N0.getOpcode() == X86ISD::KSHIFTL || N1.getOpcode() == X86ISD::KSHIFTL) {
     unsigned NumElts = VT.getVectorNumElements();
     unsigned HalfElts = NumElts / 2;
     APInt UpperElts = APInt::getHighBitsSet(NumElts, HalfElts);

llvm/test/CodeGen/X86/or-lea.ll

entry:
   ret i64 %inc
 }
 
 define i32 @or_sext1(i32 %x) {
 ; X86-LABEL: or_sext1:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $1, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(%eax,%eax), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $1, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(%rax,%rax), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 1
   ret i32 %or
 }
 
 define i64 @or_sext1_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $1, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext1_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $1, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(%rax,%rax), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 1
   ret i64 %or
 }
 
 define i32 @or_sext2(i32 %x) {
 ; X86-LABEL: or_sext2:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $2, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(%eax,%eax,2), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext2:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $2, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(%rax,%rax,2), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 2
   ret i32 %or
 }
 
 define i64 @or_sext2_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $2, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext2_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $2, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(%rax,%rax,2), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 2
   ret i64 %or
 }
 
 define i32 @or_sext3(i32 %x) {
 ; X86-LABEL: or_sext3:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $3, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(,%eax,4), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext3:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $3, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(,%rax,4), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 3
   ret i32 %or
 }
 
 define i64 @or_sext3_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $3, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext3_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $3, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(,%rax,4), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 3
   ret i64 %or
 }
 
 define i32 @or_sext4(i32 %x) {
 ; X86-LABEL: or_sext4:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $4, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(%eax,%eax,4), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext4:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $4, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(%rax,%rax,4), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 4
   ret i32 %or
 }
 
 define i64 @or_sext4_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $4, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext4_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $4, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(%rax,%rax,4), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 4
   ret i64 %or
 }
 
 define i32 @or_sext7(i32 %x) {
 ; X86-LABEL: or_sext7:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $7, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(,%eax,8), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext7:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $7, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(,%rax,8), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 7
   ret i32 %or
 }
 
 define i64 @or_sext7_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $7, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext7_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $7, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(,%rax,8), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 7
   ret i64 %or
 }
 
 define i32 @or_sext8(i32 %x) {
 ; X86-LABEL: or_sext8:
 ; X86:       # %bb.0:
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl $43, {{[0-9]+}}(%esp)
-; X86-NEXT:    setge %al
-; X86-NEXT:    negl %eax
-; X86-NEXT:    orl $8, %eax
+; X86-NEXT:    setl %al
+; X86-NEXT:    leal -1(%eax,%eax,8), %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl $43, %edi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negl %eax
-; X64-NEXT:    orl $8, %eax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leal -1(%rax,%rax,8), %eax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i32 %x, 42
   %sext = sext i1 %cmp to i32
   %or = or i32 %sext, 8
   ret i32 %or
 }
 
 define i64 @or_sext8_64(i64 %x) {

 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    orl $8, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_sext8_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpq $43, %rdi
-; X64-NEXT:    setge %al
-; X64-NEXT:    negq %rax
-; X64-NEXT:    orq $8, %rax
+; X64-NEXT:    setl %al
+; X64-NEXT:    leaq -1(%rax,%rax,8), %rax
 ; X64-NEXT:    retq
   %cmp = icmp sgt i64 %x, 42
   %sext = sext i1 %cmp to i64
   %or = or i64 %sext, 8
   ret i64 %or
 }