[mlir][spirv] Migrate to use specalized enum attributes

[antiagainst]

Summary

Previously we are using IntegerAttr to back all SPIR-V enum
attributes. Therefore we all such attributes are showed like
IntegerAttr in IRs, which is barely readable and breaks
roundtripability of the IR. This commit changes to use
EnumAttr as the base directly so that we can have separate
attribute definitions and better IR printing.

[kuhar]

Looks fine to me. I'm not very familiar with this part of many of the changed files, so please wait for a second approval before submitting.

mlir/lib/Target/SPIRV/Serialization/Serializer.cpp

197–199

ubernit: auto mm = and auto am = ?

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAvailability.td

class Availability {
 
   // The code for preparing a concrete instance. This should be C++ statements
   // and will be generated before the `mergeAction` logic.
   code instancePreparation = "";
   // The availability requirement carried by a concrete instance.
   string instance = ?;
 }
 
-class MinVersionBase<string name, I32EnumAttr scheme, I32EnumAttrCase min>
+class MinVersionBase<string name, EnumAttr scheme, I32EnumAttrCase min>
     : Availability {
   let interfaceName = name;
 
   let queryFnRetType = "llvm::Optional<" # scheme.returnType # ">";
   let queryFnName = "getMinVersion";
 
   let mergeAction = "{ "
     "if ($overall) { "
       "$overall = static_cast<" # scheme.returnType # ">("
                   "std::max(*$overall, $instance)); "
     "} else { $overall = $instance; }}";
   let initializer = "::llvm::None";
-  let instanceType = scheme.cppNamespace # "::" # scheme.className;
+  let instanceType = scheme.cppNamespace # "::" # scheme.enum.className;
 
-  let instance = scheme.cppNamespace # "::" # scheme.className # "::" #
+  let instance = scheme.cppNamespace # "::" # scheme.enum.className # "::" #
                  min.symbol;
 }
 
-class MaxVersionBase<string name, I32EnumAttr scheme, I32EnumAttrCase max>
+class MaxVersionBase<string name, EnumAttr scheme, I32EnumAttrCase max>
     : Availability {
   let interfaceName = name;
 
   let queryFnRetType = "llvm::Optional<" # scheme.returnType # ">";
   let queryFnName = "getMaxVersion";
 
   let mergeAction = "{ "
     "if ($overall) { "
       "$overall = static_cast<" # scheme.returnType # ">("
                   "std::min(*$overall, $instance)); "
     "} else { $overall = $instance; }}";
   let initializer = "::llvm::None";
-  let instanceType = scheme.cppNamespace # "::" # scheme.className;
+  let instanceType = scheme.cppNamespace # "::" # scheme.enum.className;
 
-  let instance = scheme.cppNamespace # "::" # scheme.className # "::" #
+  let instance = scheme.cppNamespace # "::" # scheme.enum.className # "::" #
                  max.symbol;
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_AVAILABILITY

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td

def SPV_ControlBarrierOp : SPV_Op<"ControlBarrier", []> {
   let arguments = (ins
     SPV_ScopeAttr:$execution_scope,
     SPV_ScopeAttr:$memory_scope,
     SPV_MemorySemanticsAttr:$memory_semantics
   );
 
   let results = (outs);
 
-  let autogenSerialization = 0;
-
   let assemblyFormat = [{
     $execution_scope `,` $memory_scope `,` $memory_semantics attr-dict
   }];
 }
 
 // -----
 
 def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> {
def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> {
 
   let arguments = (ins
     SPV_ScopeAttr:$memory_scope,
     SPV_MemorySemanticsAttr:$memory_semantics
   );
 
   let results = (outs);
 
-  let autogenSerialization = 0;
-
   let assemblyFormat = "$memory_scope `,` $memory_semantics attr-dict";
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_BARRIER_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

def SPIRV_Dialect : Dialect {
   // prefixed. Fix and update to _Both & then _Prefixed.
   let emitAccessorPrefix = kEmitAccessorPrefix_Raw;
 }
 
 //===----------------------------------------------------------------------===//
 // Utility definitions
 //===----------------------------------------------------------------------===//
 
-// A predicate that checks whether `$_self` is a known enum case for the
-// enum class with `name`.
-class SPV_IsKnownEnumCaseFor<string name> :
-    CPred<"::mlir::spirv::symbolize" # name # "("
-          "$_self.cast<IntegerAttr>().getValue().getZExtValue()).has_value()">;
-
 // Wrapper over base BitEnumAttr to set common fields.
-class SPV_BitEnumAttr<string name, string description,
-                      list<BitEnumAttrCaseBase> cases> :
-    I32BitEnumAttr<name, description, cases> {
-  let predicate = And<[
-    I32Attr.predicate,
-    SPV_IsKnownEnumCaseFor<name>,
-  ]>;
+class SPV_BitEnum<string name, string description,
+                  list<BitEnumAttrCaseBase> cases>
+    : I32BitEnumAttr<name, description, cases> {
+  let genSpecializedAttr = 0;
   let cppNamespace = "::mlir::spirv";
 }
-
-// Wrapper over base I32EnumAttr to set common fields.
-class SPV_I32EnumAttr<string name, string description,
-                      list<I32EnumAttrCase> cases> :
-    I32EnumAttr<name, description, cases> {
-  let predicate = And<[
-    I32Attr.predicate,
-    SPV_IsKnownEnumCaseFor<name>,
-  ]>;
-  let cppNamespace = "::mlir::spirv";
+class SPV_BitEnumAttr<string name, string description, string mnemonic,
+                      list<BitEnumAttrCaseBase> cases> :
+    EnumAttr<SPIRV_Dialect, SPV_BitEnum<name, description, cases>, mnemonic> {
+  let assemblyFormat = "`<` $value `>`";
 }
 
 // Wrapper over base I32EnumAttr to set common fields.
-class SPV_Enum<string name, string description, list<I32EnumAttrCase> cases>
+class SPV_I32Enum<string name, string description,
+                  list<I32EnumAttrCase> cases>
     : I32EnumAttr<name, description, cases> {
   let genSpecializedAttr = 0;
   let cppNamespace = "::mlir::spirv";
 }
-class SPV_EnumAttr<string name, string description, string mnemonic,
+class SPV_I32EnumAttr<string name, string description, string mnemonic,
                       list<I32EnumAttrCase> cases> :
-    EnumAttr<SPIRV_Dialect, SPV_Enum<name, description, cases>, mnemonic>;
+    EnumAttr<SPIRV_Dialect, SPV_I32Enum<name, description, cases>, mnemonic> {
+  let assemblyFormat = "`<` $value `>`";
+}
 
 //===----------------------------------------------------------------------===//
 // SPIR-V availability definitions
 //===----------------------------------------------------------------------===//
 
 def SPV_V_1_0 : I32EnumAttrCase<"V_1_0", 0, "v1.0">;
 def SPV_V_1_1 : I32EnumAttrCase<"V_1_1", 1, "v1.1">;
 def SPV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">;
 def SPV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">;
 def SPV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">;
 def SPV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">;
 def SPV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">;
 
-def SPV_VersionAttr : SPV_I32EnumAttr<"Version", "valid SPIR-V version", [
+def SPV_VersionAttr : SPV_I32EnumAttr<
+  "Version", "valid SPIR-V version", "version", [
     SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5,
     SPV_V_1_6]>;
 
 class MinVersion<I32EnumAttrCase min> : MinVersionBase<
     "QueryMinVersionInterface", SPV_VersionAttr, min> {
   let cppNamespace = "::mlir::spirv";
   let interfaceDescription = [{
     Querying interface for minimal required SPIR-V version.

 def SPV_DT_CPU           : I32EnumAttrCase<"CPU", 0>;
 def SPV_DT_DiscreteGPU   : I32EnumAttrCase<"DiscreteGPU", 1>;
 def SPV_DT_IntegratedGPU : I32EnumAttrCase<"IntegratedGPU", 2>;
 // An accelerator other than GPU or CPU
 def SPV_DT_Other         : I32EnumAttrCase<"Other", 3>;
 // Information missing.
 def SPV_DT_Unknown       : I32EnumAttrCase<"Unknown", 4>;
 
-def SPV_DeviceTypeAttr : SPV_EnumAttr<
+def SPV_DeviceTypeAttr : SPV_I32EnumAttr<
   "DeviceType", "valid SPIR-V device types", "device_type", [
     SPV_DT_Other, SPV_DT_IntegratedGPU, SPV_DT_DiscreteGPU,
     SPV_DT_CPU, SPV_DT_Unknown
   ]>;
 
 def SPV_V_AMD         : I32EnumAttrCase<"AMD", 0>;
 def SPV_V_Apple       : I32EnumAttrCase<"Apple", 1>;
 def SPV_V_ARM         : I32EnumAttrCase<"ARM", 2>;
 def SPV_V_Imagination : I32EnumAttrCase<"Imagination", 3>;
 def SPV_V_Intel       : I32EnumAttrCase<"Intel", 4>;
 def SPV_V_NVIDIA      : I32EnumAttrCase<"NVIDIA", 5>;
 def SPV_V_Qualcomm    : I32EnumAttrCase<"Qualcomm", 6>;
 def SPV_V_SwiftShader : I32EnumAttrCase<"SwiftShader", 7>;
 def SPV_V_Unknown     : I32EnumAttrCase<"Unknown", 0xff>;
 
-def SPV_VendorAttr : SPV_EnumAttr<
+def SPV_VendorAttr : SPV_I32EnumAttr<
   "Vendor", "recognized SPIR-V vendor strings", "vendor", [
     SPV_V_AMD, SPV_V_Apple, SPV_V_ARM, SPV_V_Imagination,
     SPV_V_Intel, SPV_V_NVIDIA, SPV_V_Qualcomm, SPV_V_SwiftShader,
     SPV_V_Unknown
   ]>;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V extension definitions

 def SPV_NV_stereo_view_rendering         : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 5011>;
 def SPV_NV_viewport_array2               : I32EnumAttrCase<"SPV_NV_viewport_array2", 5012>;
 def SPV_NV_bindless_texture              : I32EnumAttrCase<"SPV_NV_bindless_texture", 5013>;
 def SPV_NV_ray_tracing_motion_blur       : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 5014>;
 
 def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 5015>;
 
 def SPV_ExtensionAttr :
-    SPV_EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
+    SPV_I32EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
       SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_device_group,
       SPV_KHR_float_controls, SPV_KHR_physical_storage_buffer, SPV_KHR_multiview,
       SPV_KHR_no_integer_wrap_decoration, SPV_KHR_post_depth_coverage,
       SPV_KHR_shader_atomic_counter_ops, SPV_KHR_shader_ballot,
       SPV_KHR_shader_clock, SPV_KHR_shader_draw_parameters,
       SPV_KHR_storage_buffer_storage_class, SPV_KHR_subgroup_vote,
       SPV_KHR_variable_pointers, SPV_KHR_vulkan_memory_model, SPV_KHR_expect_assume,
       SPV_KHR_integer_dot_product, SPV_KHR_bit_instructions, SPV_KHR_fragment_shading_rate,

 def SPV_C_ShaderStereoViewNV                          : I32EnumAttrCase<"ShaderStereoViewNV", 5259> {
   list<I32EnumAttrCase> implies = [SPV_C_ShaderViewportMaskNV];
   list<Availability> availability = [
     Extension<[SPV_NV_stereo_view_rendering]>
   ];
 }
 
 def SPV_CapabilityAttr :
-    SPV_I32EnumAttr<"Capability", "valid SPIR-V Capability", [
+    SPV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [
       SPV_C_Matrix, SPV_C_Addresses, SPV_C_Linkage, SPV_C_Kernel, SPV_C_Float16,
       SPV_C_Float64, SPV_C_Int64, SPV_C_Groups, SPV_C_Int16, SPV_C_Int8,
       SPV_C_Sampled1D, SPV_C_SampledBuffer, SPV_C_GroupNonUniform, SPV_C_ShaderLayer,
       SPV_C_ShaderViewportIndex, SPV_C_UniformDecoration, SPV_C_SubgroupBallotKHR,
       SPV_C_SubgroupVoteKHR, SPV_C_StorageBuffer16BitAccess,
       SPV_C_StoragePushConstant16, SPV_C_StorageInputOutput16, SPV_C_DeviceGroup,
       SPV_C_AtomicStorageOps, SPV_C_SampleMaskPostDepthCoverage,
       SPV_C_StorageBuffer8BitAccess, SPV_C_StoragePushConstant8,

 def SPV_AM_PhysicalStorageBuffer64 : I32EnumAttrCase<"PhysicalStorageBuffer64", 5348> {
   list<Availability> availability = [
     Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
     Capability<[SPV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 
 def SPV_AddressingModelAttr :
-    SPV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", [
+    SPV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", "addressing_model", [
       SPV_AM_Logical, SPV_AM_Physical32, SPV_AM_Physical64,
       SPV_AM_PhysicalStorageBuffer64
     ]>;
 
 def SPV_BI_Position                    : I32EnumAttrCase<"Position", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];

 def SPV_BI_CullMaskKHR                 : I32EnumAttrCase<"CullMaskKHR", 6021> {
   list<Availability> availability = [
     Extension<[SPV_KHR_ray_cull_mask]>,
     Capability<[SPV_C_RayCullMaskKHR]>
   ];
 }
 
 def SPV_BuiltInAttr :
-    SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", [
+    SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", "built_in", [
       SPV_BI_Position, SPV_BI_PointSize, SPV_BI_ClipDistance, SPV_BI_CullDistance,
       SPV_BI_VertexId, SPV_BI_InstanceId, SPV_BI_PrimitiveId, SPV_BI_InvocationId,
       SPV_BI_Layer, SPV_BI_ViewportIndex, SPV_BI_TessLevelOuter,
       SPV_BI_TessLevelInner, SPV_BI_TessCoord, SPV_BI_PatchVertices,
       SPV_BI_FragCoord, SPV_BI_PointCoord, SPV_BI_FrontFacing, SPV_BI_SampleId,
       SPV_BI_SamplePosition, SPV_BI_SampleMask, SPV_BI_FragDepth,
       SPV_BI_HelperInvocation, SPV_BI_NumWorkgroups, SPV_BI_WorkgroupSize,
       SPV_BI_WorkgroupId, SPV_BI_LocalInvocationId, SPV_BI_GlobalInvocationId,

 }
 def SPV_D_MediaBlockIOINTEL                  : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> {
   list<Availability> availability = [
     Capability<[SPV_C_VectorComputeINTEL]>
   ];
 }
 
 def SPV_DecorationAttr :
-    SPV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", [
+    SPV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", "decoration", [
       SPV_D_RelaxedPrecision, SPV_D_SpecId, SPV_D_Block, SPV_D_BufferBlock,
       SPV_D_RowMajor, SPV_D_ColMajor, SPV_D_ArrayStride, SPV_D_MatrixStride,
       SPV_D_GLSLShared, SPV_D_GLSLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
       SPV_D_NoPerspective, SPV_D_Flat, SPV_D_Patch, SPV_D_Centroid, SPV_D_Sample,
       SPV_D_Invariant, SPV_D_Restrict, SPV_D_Aliased, SPV_D_Volatile, SPV_D_Constant,
       SPV_D_Coherent, SPV_D_NonWritable, SPV_D_NonReadable, SPV_D_Uniform,
       SPV_D_UniformId, SPV_D_SaturatedConversion, SPV_D_Stream, SPV_D_Location,
       SPV_D_Component, SPV_D_Index, SPV_D_Binding, SPV_D_DescriptorSet, SPV_D_Offset,

 }
 def SPV_D_SubpassData : I32EnumAttrCase<"SubpassData", 6> {
   list<Availability> availability = [
     Capability<[SPV_C_InputAttachment]>
   ];
 }
 
 def SPV_DimAttr :
-    SPV_I32EnumAttr<"Dim", "valid SPIR-V Dim", [
+    SPV_I32EnumAttr<"Dim", "valid SPIR-V Dim", "dim", [
       SPV_D_1D, SPV_D_2D, SPV_D_3D, SPV_D_Cube, SPV_D_Rect, SPV_D_Buffer,
       SPV_D_SubpassData
     ]>;
 
 def SPV_EM_Invocations                      : I32EnumAttrCase<"Invocations", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Geometry]>
   ];

 }
 def SPV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
   list<Availability> availability = [
     Capability<[SPV_C_VectorComputeINTEL]>
   ];
 }
 
 def SPV_ExecutionModeAttr :
-    SPV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", [
+    SPV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [
       SPV_EM_Invocations, SPV_EM_SpacingEqual, SPV_EM_SpacingFractionalEven,
       SPV_EM_SpacingFractionalOdd, SPV_EM_VertexOrderCw, SPV_EM_VertexOrderCcw,
       SPV_EM_PixelCenterInteger, SPV_EM_OriginUpperLeft, SPV_EM_OriginLowerLeft,
       SPV_EM_EarlyFragmentTests, SPV_EM_PointMode, SPV_EM_Xfb, SPV_EM_DepthReplacing,
       SPV_EM_DepthGreater, SPV_EM_DepthLess, SPV_EM_DepthUnchanged, SPV_EM_LocalSize,
       SPV_EM_LocalSizeHint, SPV_EM_InputPoints, SPV_EM_InputLines,
       SPV_EM_InputLinesAdjacency, SPV_EM_Triangles, SPV_EM_InputTrianglesAdjacency,
       SPV_EM_Quads, SPV_EM_Isolines, SPV_EM_OutputVertices, SPV_EM_OutputPoints,

 }
 def SPV_EM_CallableKHR            : I32EnumAttrCase<"CallableKHR", 5318> {
   list<Availability> availability = [
     Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
   ];
 }
 
 def SPV_ExecutionModelAttr :
-    SPV_I32EnumAttr<"ExecutionModel", "valid SPIR-V ExecutionModel", [
+    SPV_I32EnumAttr<"ExecutionModel", "valid SPIR-V ExecutionModel", "execution_model", [
       SPV_EM_Vertex, SPV_EM_TessellationControl, SPV_EM_TessellationEvaluation,
       SPV_EM_Geometry, SPV_EM_Fragment, SPV_EM_GLCompute, SPV_EM_Kernel,
       SPV_EM_TaskNV, SPV_EM_MeshNV, SPV_EM_RayGenerationKHR, SPV_EM_IntersectionKHR,
       SPV_EM_AnyHitKHR, SPV_EM_ClosestHitKHR, SPV_EM_MissKHR, SPV_EM_CallableKHR
     ]>;
 
 def SPV_FC_None         : I32BitEnumAttrCaseNone<"None">;
 def SPV_FC_Inline       : I32BitEnumAttrCaseBit<"Inline", 0>;
 def SPV_FC_DontInline   : I32BitEnumAttrCaseBit<"DontInline", 1>;
 def SPV_FC_Pure         : I32BitEnumAttrCaseBit<"Pure", 2>;
 def SPV_FC_Const        : I32BitEnumAttrCaseBit<"Const", 3>;
 def SPV_FC_OptNoneINTEL : I32BitEnumAttrCaseBit<"OptNoneINTEL", 16> {
   list<Availability> availability = [
     Capability<[SPV_C_OptNoneINTEL]>
   ];
 }
 
 def SPV_FunctionControlAttr :
-    SPV_BitEnumAttr<"FunctionControl", "valid SPIR-V FunctionControl", [
+    SPV_BitEnumAttr<"FunctionControl", "valid SPIR-V FunctionControl", "function_control", [
       SPV_FC_None, SPV_FC_Inline, SPV_FC_DontInline, SPV_FC_Pure, SPV_FC_Const,
       SPV_FC_OptNoneINTEL
     ]>;
 
 def SPV_GO_Reduce                     : I32EnumAttrCase<"Reduce", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot, SPV_C_Kernel]>
   ];

 def SPV_GO_PartitionedExclusiveScanNV : I32EnumAttrCase<"PartitionedExclusiveScanNV", 8> {
   list<Availability> availability = [
     Extension<[SPV_NV_shader_subgroup_partitioned]>,
     Capability<[SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 def SPV_GroupOperationAttr :
-    SPV_I32EnumAttr<"GroupOperation", "valid SPIR-V GroupOperation", [
+    SPV_I32EnumAttr<"GroupOperation", "valid SPIR-V GroupOperation", "group_operation", [
       SPV_GO_Reduce, SPV_GO_InclusiveScan, SPV_GO_ExclusiveScan,
       SPV_GO_ClusteredReduce, SPV_GO_PartitionedReduceNV,
       SPV_GO_PartitionedInclusiveScanNV, SPV_GO_PartitionedExclusiveScanNV
     ]>;
 
 def SPV_IF_Unknown      : I32EnumAttrCase<"Unknown", 0>;
 def SPV_IF_Rgba32f      : I32EnumAttrCase<"Rgba32f", 1> {
   list<Availability> availability = [

 }
 def SPV_IF_R64i         : I32EnumAttrCase<"R64i", 41> {
   list<Availability> availability = [
     Capability<[SPV_C_Int64ImageEXT]>
   ];
 }
 
 def SPV_ImageFormatAttr :
-    SPV_I32EnumAttr<"ImageFormat", "valid SPIR-V ImageFormat", [
+    SPV_I32EnumAttr<"ImageFormat", "valid SPIR-V ImageFormat", "image_format", [
       SPV_IF_Unknown, SPV_IF_Rgba32f, SPV_IF_Rgba16f, SPV_IF_R32f, SPV_IF_Rgba8,
       SPV_IF_Rgba8Snorm, SPV_IF_Rg32f, SPV_IF_Rg16f, SPV_IF_R11fG11fB10f,
       SPV_IF_R16f, SPV_IF_Rgba16, SPV_IF_Rgb10A2, SPV_IF_Rg16, SPV_IF_Rg8,
       SPV_IF_R16, SPV_IF_R8, SPV_IF_Rgba16Snorm, SPV_IF_Rg16Snorm, SPV_IF_Rg8Snorm,
       SPV_IF_R16Snorm, SPV_IF_R8Snorm, SPV_IF_Rgba32i, SPV_IF_Rgba16i, SPV_IF_Rgba8i,
       SPV_IF_R32i, SPV_IF_Rg32i, SPV_IF_Rg16i, SPV_IF_Rg8i, SPV_IF_R16i, SPV_IF_R8i,
       SPV_IF_Rgba32ui, SPV_IF_Rgba16ui, SPV_IF_Rgba8ui, SPV_IF_R32ui,
       SPV_IF_Rgb10a2ui, SPV_IF_Rg32ui, SPV_IF_Rg16ui, SPV_IF_Rg8ui, SPV_IF_R16ui,

 }
 def SPV_IO_Nontemporal        : I32BitEnumAttrCaseBit<"Nontemporal", 14> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_6>
   ];
 }
 
 def SPV_ImageOperandsAttr :
-    SPV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", [
+    SPV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", "image_operands", [
       SPV_IO_None, SPV_IO_Bias, SPV_IO_Lod, SPV_IO_Grad, SPV_IO_ConstOffset,
       SPV_IO_Offset, SPV_IO_ConstOffsets, SPV_IO_Sample, SPV_IO_MinLod,
       SPV_IO_MakeTexelAvailable, SPV_IO_MakeTexelVisible, SPV_IO_NonPrivateTexel,
       SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend,
       SPV_IO_Nontemporal
     ]>;
 
 def SPV_LT_Export      : I32EnumAttrCase<"Export", 0> {

 def SPV_LT_LinkOnceODR : I32EnumAttrCase<"LinkOnceODR", 2> {
   list<Availability> availability = [
     Extension<[SPV_KHR_linkonce_odr]>,
     Capability<[SPV_C_Linkage]>
   ];
 }
 
 def SPV_LinkageTypeAttr :
-    SPV_I32EnumAttr<"LinkageType", "valid SPIR-V LinkageType", [
+    SPV_I32EnumAttr<"LinkageType", "valid SPIR-V LinkageType", "linkage_type", [
       SPV_LT_Export, SPV_LT_Import, SPV_LT_LinkOnceODR
     ]>;
 
 def SPV_LC_None                      : I32BitEnumAttrCaseNone<"None">;
 def SPV_LC_Unroll                    : I32BitEnumAttrCaseBit<"Unroll", 0>;
 def SPV_LC_DontUnroll                : I32BitEnumAttrCaseBit<"DontUnroll", 1>;
 def SPV_LC_DependencyInfinite        : I32BitEnumAttrCaseBit<"DependencyInfinite", 2> {
   list<Availability> availability = [

 def SPV_LC_NoFusionINTEL             : I32BitEnumAttrCaseBit<"NoFusionINTEL", 23> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_fpga_loop_controls]>,
     Capability<[SPV_C_FPGALoopControlsINTEL]>
   ];
 }
 
 def SPV_LoopControlAttr :
-    SPV_BitEnumAttr<"LoopControl", "valid SPIR-V LoopControl", [
+    SPV_BitEnumAttr<"LoopControl", "valid SPIR-V LoopControl", "loop_control", [
       SPV_LC_None, SPV_LC_Unroll, SPV_LC_DontUnroll, SPV_LC_DependencyInfinite,
       SPV_LC_DependencyLength, SPV_LC_MinIterations, SPV_LC_MaxIterations,
       SPV_LC_IterationMultiple, SPV_LC_PeelCount, SPV_LC_PartialCount,
       SPV_LC_InitiationIntervalINTEL, SPV_LC_LoopCoalesceINTEL,
       SPV_LC_MaxConcurrencyINTEL, SPV_LC_MaxInterleavingINTEL,
       SPV_LC_DependencyArrayINTEL, SPV_LC_SpeculatedIterationsINTEL,
       SPV_LC_PipelineEnableINTEL, SPV_LC_NoFusionINTEL
     ]>;

 def SPV_MA_NoAliasINTELMask     : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_memory_access_aliasing]>,
     Capability<[SPV_C_MemoryAccessAliasingINTEL]>
   ];
 }
 
 def SPV_MemoryAccessAttr :
-    SPV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", [
+    SPV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", "memory_access", [
       SPV_MA_None, SPV_MA_Volatile, SPV_MA_Aligned, SPV_MA_Nontemporal,
       SPV_MA_MakePointerAvailable, SPV_MA_MakePointerVisible,
       SPV_MA_NonPrivatePointer, SPV_MA_AliasScopeINTELMask, SPV_MA_NoAliasINTELMask
     ]>;
 
 def SPV_MM_Simple  : I32EnumAttrCase<"Simple", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>

 def SPV_MM_Vulkan  : I32EnumAttrCase<"Vulkan", 3> {
   list<Availability> availability = [
     Extension<[SPV_KHR_vulkan_memory_model]>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
 
 def SPV_MemoryModelAttr :
-    SPV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", [
+    SPV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", "memory_model", [
       SPV_MM_Simple, SPV_MM_GLSL450, SPV_MM_OpenCL, SPV_MM_Vulkan
     ]>;
 
 def SPV_MS_None                   : I32BitEnumAttrCaseNone<"None">;
 def SPV_MS_Acquire                : I32BitEnumAttrCaseBit<"Acquire", 1>;
 def SPV_MS_Release                : I32BitEnumAttrCaseBit<"Release", 2>;
 def SPV_MS_AcquireRelease         : I32BitEnumAttrCaseBit<"AcquireRelease", 3>;
 def SPV_MS_SequentiallyConsistent : I32BitEnumAttrCaseBit<"SequentiallyConsistent", 4>;

 def SPV_MS_Volatile               : I32BitEnumAttrCaseBit<"Volatile", 15> {
   list<Availability> availability = [
     Extension<[SPV_KHR_vulkan_memory_model]>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
 
 def SPV_MemorySemanticsAttr :
-    SPV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", [
+    SPV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", "memory_semantics", [
       SPV_MS_None, SPV_MS_Acquire, SPV_MS_Release, SPV_MS_AcquireRelease,
       SPV_MS_SequentiallyConsistent, SPV_MS_UniformMemory, SPV_MS_SubgroupMemory,
       SPV_MS_WorkgroupMemory, SPV_MS_CrossWorkgroupMemory,
       SPV_MS_AtomicCounterMemory, SPV_MS_ImageMemory, SPV_MS_OutputMemory,
       SPV_MS_MakeAvailable, SPV_MS_MakeVisible, SPV_MS_Volatile
     ]>;
 
 def SPV_S_CrossDevice   : I32EnumAttrCase<"CrossDevice", 0>;

 }
 def SPV_S_ShaderCallKHR : I32EnumAttrCase<"ShaderCallKHR", 6> {
   list<Availability> availability = [
     Capability<[SPV_C_RayTracingKHR]>
   ];
 }
 
 def SPV_ScopeAttr :
-    SPV_I32EnumAttr<"Scope", "valid SPIR-V Scope", [
+    SPV_I32EnumAttr<"Scope", "valid SPIR-V Scope", "scope", [
       SPV_S_CrossDevice, SPV_S_Device, SPV_S_Workgroup, SPV_S_Subgroup,
       SPV_S_Invocation, SPV_S_QueueFamily, SPV_S_ShaderCallKHR
     ]>;
 
 def SPV_SC_None        : I32BitEnumAttrCaseNone<"None">;
 def SPV_SC_Flatten     : I32BitEnumAttrCaseBit<"Flatten", 0>;
 def SPV_SC_DontFlatten : I32BitEnumAttrCaseBit<"DontFlatten", 1>;
 
 def SPV_SelectionControlAttr :
-    SPV_BitEnumAttr<"SelectionControl", "valid SPIR-V SelectionControl", [
+    SPV_BitEnumAttr<"SelectionControl", "valid SPIR-V SelectionControl", "selection_control", [
       SPV_SC_None, SPV_SC_Flatten, SPV_SC_DontFlatten
     ]>;
 
 def SPV_SC_UniformConstant         : I32EnumAttrCase<"UniformConstant", 0>;
 def SPV_SC_Input                   : I32EnumAttrCase<"Input", 1>;
 def SPV_SC_Uniform                 : I32EnumAttrCase<"Uniform", 2> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>

 def SPV_SC_HostOnlyINTEL           : I32EnumAttrCase<"HostOnlyINTEL", 5937> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_usm_storage_classes]>,
     Capability<[SPV_C_USMStorageClassesINTEL]>
   ];
 }
 
 def SPV_StorageClassAttr :
-    SPV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", [
+    SPV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", "storage_class", [
       SPV_SC_UniformConstant, SPV_SC_Input, SPV_SC_Uniform, SPV_SC_Output,
       SPV_SC_Workgroup, SPV_SC_CrossWorkgroup, SPV_SC_Private, SPV_SC_Function,
       SPV_SC_Generic, SPV_SC_PushConstant, SPV_SC_AtomicCounter, SPV_SC_Image,
       SPV_SC_StorageBuffer, SPV_SC_CallableDataKHR, SPV_SC_IncomingCallableDataKHR,
       SPV_SC_RayPayloadKHR, SPV_SC_HitAttributeKHR, SPV_SC_IncomingRayPayloadKHR,
       SPV_SC_ShaderRecordBufferKHR, SPV_SC_PhysicalStorageBuffer,
       SPV_SC_CodeSectionINTEL, SPV_SC_DeviceOnlyINTEL, SPV_SC_HostOnlyINTEL
     ]>;
 
 // End enum section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 // Enums added manually that are not part of SPIR-V spec
 
 def SPV_IDI_NoDepth      : I32EnumAttrCase<"NoDepth", 0>;
 def SPV_IDI_IsDepth      : I32EnumAttrCase<"IsDepth", 1>;
 def SPV_IDI_DepthUnknown : I32EnumAttrCase<"DepthUnknown", 2>;
 
-def SPV_DepthAttr :
-    SPV_I32EnumAttr<"ImageDepthInfo", "valid SPIR-V Image Depth specification",
-      [SPV_IDI_NoDepth, SPV_IDI_IsDepth, SPV_IDI_DepthUnknown]>;
+def SPV_DepthAttr : SPV_I32EnumAttr<
+  "ImageDepthInfo", "valid SPIR-V Image Depth specification",
+  "image_depth_info", [SPV_IDI_NoDepth, SPV_IDI_IsDepth, SPV_IDI_DepthUnknown]>;
 
 def SPV_IAI_NonArrayed : I32EnumAttrCase<"NonArrayed", 0>;
 def SPV_IAI_Arrayed    : I32EnumAttrCase<"Arrayed", 1>;
 
-def SPV_ArrayedAttr :
-    SPV_I32EnumAttr<
-      "ImageArrayedInfo", "valid SPIR-V Image Arrayed specification",
-      [SPV_IAI_NonArrayed, SPV_IAI_Arrayed]>;
+def SPV_ArrayedAttr : SPV_I32EnumAttr<
+  "image_arrayed_info", [SPV_IAI_NonArrayed, SPV_IAI_Arrayed]>;
 
 def SPV_ISI_SingleSampled : I32EnumAttrCase<"SingleSampled", 0>;
 def SPV_ISI_MultiSampled  : I32EnumAttrCase<"MultiSampled", 1>;
 
-def SPV_SamplingAttr:
-    SPV_I32EnumAttr<
-      "ImageSamplingInfo", "valid SPIR-V Image Sampling specification",
-      [SPV_ISI_SingleSampled, SPV_ISI_MultiSampled]>;
+def SPV_SamplingAttr: SPV_I32EnumAttr<
+  "image_sampling_info", [SPV_ISI_SingleSampled, SPV_ISI_MultiSampled]>;
 
 def SPV_ISUI_SamplerUnknown : I32EnumAttrCase<"SamplerUnknown", 0>;
 def SPV_ISUI_NeedSampler    : I32EnumAttrCase<"NeedSampler", 1>;
 def SPV_ISUI_NoSampler      : I32EnumAttrCase<"NoSampler", 2>;
 
-def SPV_SamplerUseAttr:
-    SPV_I32EnumAttr<
-      "ImageSamplerUseInfo", "valid SPIR-V Sampler Use specification",
-      [SPV_ISUI_SamplerUnknown, SPV_ISUI_NeedSampler, SPV_ISUI_NoSampler]>;
+def SPV_SamplerUseAttr: SPV_I32EnumAttr<
+  "image_sampler_use_info",
 
 //===----------------------------------------------------------------------===//
 // SPIR-V attribute definitions
 //===----------------------------------------------------------------------===//
 
 def SPV_VerCapExtAttr : DialectAttr<
     SPIRV_Dialect,
     CPred<"$_self.isa<::mlir::spirv::VerCapExtAttr>()">,

 def SPV_OC_OpCooperativeMatrixMulAddNV : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
 def SPV_OC_OpCooperativeMatrixLengthNV : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
 def SPV_OC_OpSubgroupBlockReadINTEL    : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
 def SPV_OC_OpSubgroupBlockWriteINTEL   : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
 def SPV_OC_OpAssumeTrueKHR             : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
 def SPV_OC_OpAtomicFAddEXT             : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
 
 def SPV_OpcodeAttr :
-    SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", [
+    SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
       SPV_OC_OpNop, SPV_OC_OpUndef, SPV_OC_OpSourceContinued, SPV_OC_OpSource,
       SPV_OC_OpSourceExtension, SPV_OC_OpName, SPV_OC_OpMemberName, SPV_OC_OpString,
       SPV_OC_OpLine, SPV_OC_OpExtension, SPV_OC_OpExtInstImport, SPV_OC_OpExtInst,
       SPV_OC_OpMemoryModel, SPV_OC_OpEntryPoint, SPV_OC_OpExecutionMode,
       SPV_OC_OpCapability, SPV_OC_OpTypeVoid, SPV_OC_OpTypeBool, SPV_OC_OpTypeInt,
       SPV_OC_OpTypeFloat, SPV_OC_OpTypeVector, SPV_OC_OpTypeMatrix,
       SPV_OC_OpTypeImage, SPV_OC_OpTypeSampledImage, SPV_OC_OpTypeArray,
       SPV_OC_OpTypeRuntimeArray, SPV_OC_OpTypeStruct, SPV_OC_OpTypePointer,

mlir/include/mlir/TableGen/Attribute.h

public:
   StringRef getAttrDefName() const;
 
   // Returns the code body for derived attribute. Aborts if this is not a
   // derived attribute.
   StringRef getDerivedCodeBody() const;
 
   // Returns the dialect for the attribute if defined.
   Dialect getDialect() const;
+
+  // Returns the TableGen definition this Attribute was constructed from.
+  const llvm::Record &getDef() const;
 };
 
 // Wrapper class providing helper methods for accessing MLIR constant attribute
 // defined in TableGen. This class should closely reflect what is defined as
 // class `ConstantAttr` in TableGen.
 class ConstantAttr {
 public:
   explicit ConstantAttr(const llvm::DefInit *init);

mlir/lib/Conversion/MemRefToSPIRV/MapMemRefStorageClassPass.cpp

 // symbolic ones defined in the SPIR-V specification.
 //
 //===----------------------------------------------------------------------===//
 
 #include "../PassDetail.h"
 #include "mlir/Conversion/MemRefToSPIRV/MemRefToSPIRV.h"
 #include "mlir/Conversion/MemRefToSPIRV/MemRefToSPIRVPass.h"
 #include "mlir/Dialect/Func/IR/FuncOps.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVAttributes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
-#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/Transforms/DialectConversion.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "mlir-map-memref-storage-class"
 
 using namespace mlir;

mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h"
 #include "mlir/Conversion/LLVMCommon/Pattern.h"
 #include "mlir/Conversion/LLVMCommon/TypeConverter.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/Dialect/SPIRV/Utils/LayoutUtils.h"
 #include "mlir/IR/BuiltinOps.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/Support/LogicalResult.h"
 #include "mlir/Transforms/DialectConversion.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FormatVariadic.h"
public:
 
   LogicalResult
   matchAndRewrite(spirv::ExecutionModeOp op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     // First, create the global struct's name that would be associated with
     // this entry point's execution mode. We set it to be:
     //   __spv__{SPIR-V module name}_{function name}_execution_mode_info_{mode}
     ModuleOp module = op->getParentOfType<ModuleOp>();
-    IntegerAttr executionModeAttr = op.execution_modeAttr();
+    spirv::ExecutionModeAttr executionModeAttr = op.execution_modeAttr();
     std::string moduleName;
     if (module.getName().has_value())
       moduleName = "_" + module.getName().value().str();
     else
       moduleName = "";
-    std::string executionModeInfoName =
-        llvm::formatv("__spv_{0}_{1}_execution_mode_info_{2}", moduleName,
-                      op.fn().str(), executionModeAttr.getValue());
+    std::string executionModeInfoName = llvm::formatv(
+        "__spv_{0}_{1}_execution_mode_info_{2}", moduleName, op.fn().str(),
+        static_cast<uint32_t>(executionModeAttr.getValue()));
 
     MLIRContext *context = rewriter.getContext();
     OpBuilder::InsertionGuard guard(rewriter);
     rewriter.setInsertionPointToStart(module.getBody());
 
     // Create a struct type, corresponding to the C struct below.
     // struct {
     //   int32_t executionMode;
auto global = rewriter.create<LLVM::GlobalOp>(
         /*alignment=*/0);
     Location loc = global.getLoc();
     Region &region = global.getInitializerRegion();
     Block *block = rewriter.createBlock(&region);
 
     // Initialize the struct and set the execution mode value.
     rewriter.setInsertionPoint(block, block->begin());
     Value structValue = rewriter.create<LLVM::UndefOp>(loc, structType);
-    Value executionMode =
-        rewriter.create<LLVM::ConstantOp>(loc, llvmI32Type, executionModeAttr);
+    Value executionMode = rewriter.create<LLVM::ConstantOp>(
+        loc, llvmI32Type,
+        rewriter.getI32IntegerAttr(
+            static_cast<uint32_t>(executionModeAttr.getValue())));
     structValue = rewriter.create<LLVM::InsertValueOp>(
         loc, structType, structValue, executionMode,
         ArrayAttr::get(context,
                        {rewriter.getIntegerAttr(rewriter.getI32Type(), 0)}));
 
     // Insert extra operands if they exist into execution mode info struct.
     for (unsigned i = 0, e = values.size(); i < e; ++i) {
       auto attr = values.getValue()[i];
matchAndRewrite(spirv::VectorShuffleOp op, OpAdaptor adaptor,
 
     auto dstType = typeConverter.convertType(op.getType());
     auto scalarType = dstType.cast<VectorType>().getElementType();
     auto componentsArray = components.getValue();
     auto *context = rewriter.getContext();
     auto llvmI32Type = IntegerType::get(context, 32);
     Value targetOp = rewriter.create<LLVM::UndefOp>(loc, dstType);
     for (unsigned i = 0; i < componentsArray.size(); i++) {
-      if (componentsArray[i].isa<IntegerAttr>())
-        op.emitError("unable to support non-constant component");
+      if (!componentsArray[i].isa<IntegerAttr>())
+        return op.emitError("unable to support non-constant component");
 
       int indexVal = componentsArray[i].cast<IntegerAttr>().getInt();
       if (indexVal == -1)
         continue;
 
       int offsetVal = 0;
       Value baseVector = vector1;
       if (indexVal >= vector1Size) {

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 
 #include "mlir/Dialect/SPIRV/IR/ParserUtils.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVAttributes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOpTraits.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
 #include "mlir/Dialect/SPIRV/IR/TargetAndABI.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/FunctionImplementation.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/IR/OpImplementation.h"

 template <typename EnumClass>
 static ParseResult
 parseEnumStrAttr(EnumClass &value, OpAsmParser &parser,
                  StringRef attrName = spirv::attributeName<EnumClass>()) {
   Attribute attrVal;
   NamedAttrList attr;
   auto loc = parser.getCurrentLocation();
   if (parser.parseAttribute(attrVal, parser.getBuilder().getNoneType(),
-                            attrName, attr)) {
+                            attrName, attr))
     return failure();
-  }
-  if (!attrVal.isa<StringAttr>()) {
+  if (!attrVal.isa<StringAttr>())
     return parser.emitError(loc, "expected ")
            << attrName << " attribute specified as string";
-  }
   auto attrOptional =
       spirv::symbolizeEnum<EnumClass>(attrVal.cast<StringAttr>().getValue());
-  if (!attrOptional) {
+  if (!attrOptional)
     return parser.emitError(loc, "invalid ")
            << attrName << " attribute specification: " << attrVal;
-  }
   value = *attrOptional;
   return success();
 }
 
 /// Parses the next string attribute in `parser` as an enumerant of the given
 /// `EnumClass` and inserts the enumerant into `state` as an 32-bit integer
 /// attribute with the enum class's name as attribute name.
-template <typename EnumClass>
+template <typename EnumAttrClass,
+          typename EnumClass = typename EnumAttrClass::ValueType>
 static ParseResult
 parseEnumStrAttr(EnumClass &value, OpAsmParser &parser, OperationState &state,
                  StringRef attrName = spirv::attributeName<EnumClass>()) {
-  if (parseEnumStrAttr(value, parser)) {
+  if (parseEnumStrAttr(value, parser))
     return failure();
-  }
-  state.addAttribute(attrName, parser.getBuilder().getI32IntegerAttr(
-                                   llvm::bit_cast<int32_t>(value)));
+  state.addAttribute(attrName,
+                     parser.getBuilder().getAttr<EnumAttrClass>(value));
   return success();
 }
 
 /// Parses the next keyword in `parser` as an enumerant of the given `EnumClass`
 /// and inserts the enumerant into `state` as an 32-bit integer attribute with
 /// the enum class's name as attribute name.
-template <typename EnumClass>
+template <typename EnumAttrClass,
+          typename EnumClass = typename EnumAttrClass::ValueType>
 static ParseResult
 parseEnumKeywordAttr(EnumClass &value, OpAsmParser &parser,
                      OperationState &state,
                      StringRef attrName = spirv::attributeName<EnumClass>()) {
-  if (parseEnumKeywordAttr(value, parser)) {
+  if (parseEnumKeywordAttr(value, parser))
     return failure();
-  }
-  state.addAttribute(attrName, parser.getBuilder().getI32IntegerAttr(
-                                   llvm::bit_cast<int32_t>(value)));
+  state.addAttribute(attrName,
+                     parser.getBuilder().getAttr<EnumAttrClass>(value));
   return success();
 }
 
 /// Parses Function, Selection and Loop control attributes. If no control is
 /// specified, "None" is used as a default.
-template <typename EnumClass>
+template <typename EnumAttrClass, typename EnumClass>
 static ParseResult
 parseControlAttribute(OpAsmParser &parser, OperationState &state,
                       StringRef attrName = spirv::attributeName<EnumClass>()) {
   if (succeeded(parser.parseOptionalKeyword(kControl))) {
     EnumClass control;
-    if (parser.parseLParen() || parseEnumKeywordAttr(control, parser, state) ||
+    if (parser.parseLParen() ||
+        parseEnumKeywordAttr<EnumAttrClass>(control, parser, state) ||
         parser.parseRParen())
       return failure();
     return success();
   }
   // Set control to "None" otherwise.
   Builder builder = parser.getBuilder();
-  state.addAttribute(attrName, builder.getI32IntegerAttr(0));
+  state.addAttribute(attrName,
+                     builder.getAttr<EnumAttrClass>(static_cast<EnumClass>(0)));
   return success();
 }
 
 /// Parses optional memory access attributes attached to a memory access
 /// operand/pointer. Specifically, parses the following syntax:
 ///     (`[` memory-access `]`)?
 /// where:
 ///     memory-access ::= `"None"` | `"Volatile"` | `"Aligned", `
 ///         integer-literal | `"NonTemporal"`
 static ParseResult parseMemoryAccessAttributes(OpAsmParser &parser,
                                                OperationState &state) {
   // Parse an optional list of attributes staring with '['
   if (parser.parseOptionalLSquare()) {
     // Nothing to do
     return success();
   }
 
   spirv::MemoryAccess memoryAccessAttr;
-  if (parseEnumStrAttr(memoryAccessAttr, parser, state,
-                       kMemoryAccessAttrName)) {
+  if (parseEnumStrAttr<spirv::MemoryAccessAttr>(memoryAccessAttr, parser, state,
+                                                kMemoryAccessAttrName))
     return failure();
-  }
 
   if (spirv::bitEnumContains(memoryAccessAttr, spirv::MemoryAccess::Aligned)) {
     // Parse integer attribute for alignment.
     Attribute alignmentAttr;
     Type i32Type = parser.getBuilder().getIntegerType(32);
     if (parser.parseComma() ||
         parser.parseAttribute(alignmentAttr, i32Type, kAlignmentAttrName,
                               state.attributes)) {
static ParseResult parseSourceMemoryAccessAttributes(OpAsmParser &parser,
                                                      OperationState &state) {
   // Parse an optional list of attributes staring with '['
   if (parser.parseOptionalLSquare()) {
     // Nothing to do
     return success();
   }
 
   spirv::MemoryAccess memoryAccessAttr;
-  if (parseEnumStrAttr(memoryAccessAttr, parser, state,
-                       kSourceMemoryAccessAttrName)) {
+  if (parseEnumStrAttr<spirv::MemoryAccessAttr>(memoryAccessAttr, parser, state,
+                                                kSourceMemoryAccessAttrName))
     return failure();
-  }
 
   if (spirv::bitEnumContains(memoryAccessAttr, spirv::MemoryAccess::Aligned)) {
     // Parse integer attribute for alignment.
     Attribute alignmentAttr;
     Type i32Type = parser.getBuilder().getIntegerType(32);
     if (parser.parseComma() ||
         parser.parseAttribute(alignmentAttr, i32Type, kSourceAlignmentAttrName,
                               state.attributes)) {
if (!memAccessAttr) {
     if (op->getAttr(kAlignmentAttrName)) {
       return memoryOp.emitOpError(
           "invalid alignment specification without aligned memory access "
           "specification");
     }
     return success();
   }
 
-  auto memAccessVal = memAccessAttr.template cast<IntegerAttr>();
-  auto memAccess = spirv::symbolizeMemoryAccess(memAccessVal.getInt());
+  auto memAccess = memAccessAttr.template cast<spirv::MemoryAccessAttr>();
 
   if (!memAccess) {
     return memoryOp.emitOpError("invalid memory access specifier: ")
-           << memAccessVal;
+           << memAccessAttr;
   }
 
-  if (spirv::bitEnumContains(*memAccess, spirv::MemoryAccess::Aligned)) {
+  if (spirv::bitEnumContains(memAccess.getValue(),
+                             spirv::MemoryAccess::Aligned)) {
     if (!op->getAttr(kAlignmentAttrName)) {
       return memoryOp.emitOpError("missing alignment value");
     }
   } else {
     if (op->getAttr(kAlignmentAttrName)) {
       return memoryOp.emitOpError(
           "invalid alignment specification with non-aligned memory access "
           "specification");
if (!memAccessAttr) {
     if (op->getAttr(kSourceAlignmentAttrName)) {
       return memoryOp.emitOpError(
           "invalid alignment specification without aligned memory access "
           "specification");
     }
     return success();
   }
 
-  auto memAccessVal = memAccessAttr.template cast<IntegerAttr>();
-  auto memAccess = spirv::symbolizeMemoryAccess(memAccessVal.getInt());
+  auto memAccess = memAccessAttr.template cast<spirv::MemoryAccessAttr>();
 
   if (!memAccess) {
     return memoryOp.emitOpError("invalid memory access specifier: ")
-           << memAccessVal;
+           << memAccess;
   }
 
-  if (spirv::bitEnumContains(*memAccess, spirv::MemoryAccess::Aligned)) {
+  if (spirv::bitEnumContains(memAccess.getValue(),
+                             spirv::MemoryAccess::Aligned)) {
     if (!op->getAttr(kSourceAlignmentAttrName)) {
       return memoryOp.emitOpError("missing alignment value");
     }
   } else {
     if (op->getAttr(kSourceAlignmentAttrName)) {
       return memoryOp.emitOpError(
           "invalid alignment specification with non-aligned memory access "
           "specification");

 static ParseResult parseAtomicUpdateOp(OpAsmParser &parser,
                                        OperationState &state, bool hasValue) {
   spirv::Scope scope;
   spirv::MemorySemantics memoryScope;
   SmallVector<OpAsmParser::UnresolvedOperand, 2> operandInfo;
   OpAsmParser::UnresolvedOperand ptrInfo, valueInfo;
   Type type;
   SMLoc loc;
-  if (parseEnumStrAttr(scope, parser, state, kMemoryScopeAttrName) ||
-      parseEnumStrAttr(memoryScope, parser, state, kSemanticsAttrName) ||
+  if (parseEnumStrAttr<spirv::ScopeAttr>(scope, parser, state,
+                                         kMemoryScopeAttrName) ||
+      parseEnumStrAttr<spirv::MemorySemanticsAttr>(memoryScope, parser, state,
+                                                   kSemanticsAttrName) ||
       parser.parseOperandList(operandInfo, (hasValue ? 2 : 1)) ||
       parser.getCurrentLocation(&loc) || parser.parseColonType(type))
     return failure();
 
   auto ptrType = type.dyn_cast<spirv::PointerType>();
   if (!ptrType)
     return parser.emitError(loc, "expected pointer type");
 
   SmallVector<Type, 2> operandTypes;
   operandTypes.push_back(ptrType);
   if (hasValue)
     operandTypes.push_back(ptrType.getPointeeType());
   if (parser.resolveOperands(operandInfo, operandTypes, parser.getNameLoc(),
                              state.operands))
     return failure();
   return parser.addTypeToList(ptrType.getPointeeType(), state.types);
 }
 
 // Prints an atomic update op.
 static void printAtomicUpdateOp(Operation *op, OpAsmPrinter &printer) {
   printer << " \"";
-  auto scopeAttr = op->getAttrOfType<IntegerAttr>(kMemoryScopeAttrName);
-  printer << spirv::stringifyScope(
-                 static_cast<spirv::Scope>(scopeAttr.getInt()))
-          << "\" \"";
-  auto memorySemanticsAttr = op->getAttrOfType<IntegerAttr>(kSemanticsAttrName);
-  printer << spirv::stringifyMemorySemantics(
-                 static_cast<spirv::MemorySemantics>(
-                     memorySemanticsAttr.getInt()))
+  auto scopeAttr = op->getAttrOfType<spirv::ScopeAttr>(kMemoryScopeAttrName);
+  printer << spirv::stringifyScope(scopeAttr.getValue()) << "\" \"";
+  auto memorySemanticsAttr =
+      op->getAttrOfType<spirv::MemorySemanticsAttr>(kSemanticsAttrName);
+  printer << spirv::stringifyMemorySemantics(memorySemanticsAttr.getValue())
           << "\" " << op->getOperands() << " : " << op->getOperand(0).getType();
 }
 
 template <typename T>
 static StringRef stringifyTypeName();
 
 template <>
 StringRef stringifyTypeName<IntegerType>() {
static LogicalResult verifyAtomicUpdateOp(Operation *op) {
 
   if (op->getNumOperands() > 1) {
     auto valueType = op->getOperand(1).getType();
     if (valueType != elementType)
       return op->emitOpError("expected value to have the same type as the "
                              "pointer operand's pointee type ")
              << elementType << ", but found " << valueType;
   }
-  auto memorySemantics = static_cast<spirv::MemorySemantics>(
-      op->getAttrOfType<IntegerAttr>(kSemanticsAttrName).getInt());
+  auto memorySemantics =
+      op->getAttrOfType<spirv::MemorySemanticsAttr>(kSemanticsAttrName)
+          .getValue();
   if (failed(verifyMemorySemantics(op, memorySemantics))) {
     return failure();
   }
   return success();
 }
 
 static ParseResult parseGroupNonUniformArithmeticOp(OpAsmParser &parser,
                                                     OperationState &state) {
   spirv::Scope executionScope;
   spirv::GroupOperation groupOperation;
   OpAsmParser::UnresolvedOperand valueInfo;
-  if (parseEnumStrAttr(executionScope, parser, state,
+  if (parseEnumStrAttr<spirv::ScopeAttr>(executionScope, parser, state,
                                          kExecutionScopeAttrName) ||
-      parseEnumStrAttr(groupOperation, parser, state,
+      parseEnumStrAttr<spirv::GroupOperationAttr>(groupOperation, parser, state,
                                                   kGroupOperationAttrName) ||
       parser.parseOperand(valueInfo))
     return failure();
 
   Optional<OpAsmParser::UnresolvedOperand> clusterSizeInfo;
   if (succeeded(parser.parseOptionalKeyword(kClusterSize))) {
     clusterSizeInfo = OpAsmParser::UnresolvedOperand();
     if (parser.parseLParen() || parser.parseOperand(*clusterSizeInfo) ||
         parser.parseRParen())
if (parser.resolveOperand(*clusterSizeInfo, i32Type, state.operands))
       return failure();
   }
 
   return parser.addTypeToList(resultType, state.types);
 }
 
 static void printGroupNonUniformArithmeticOp(Operation *groupOp,
                                              OpAsmPrinter &printer) {
-  printer << " \""
-          << stringifyScope(static_cast<spirv::Scope>(
-                 groupOp->getAttrOfType<IntegerAttr>(kExecutionScopeAttrName)
-                     .getInt()))
-          << "\" \""
-          << stringifyGroupOperation(static_cast<spirv::GroupOperation>(
-                 groupOp->getAttrOfType<IntegerAttr>(kGroupOperationAttrName)
-                     .getInt()))
-          << "\" " << groupOp->getOperand(0);
+  printer
+      << " \""
+      << stringifyScope(
+             groupOp->getAttrOfType<spirv::ScopeAttr>(kExecutionScopeAttrName)
+                 .getValue())
+      << stringifyGroupOperation(groupOp
+                                     ->getAttrOfType<spirv::GroupOperationAttr>(
+                                         kGroupOperationAttrName)
+                                     .getValue())
 
   if (groupOp->getNumOperands() > 1)
     printer << " " << kClusterSize << '(' << groupOp->getOperand(1) << ')';
   printer << " : " << groupOp->getResult(0).getType();
 }
 
 static LogicalResult verifyGroupNonUniformArithmeticOp(Operation *groupOp) {
-  spirv::Scope scope = static_cast<spirv::Scope>(
-      groupOp->getAttrOfType<IntegerAttr>(kExecutionScopeAttrName).getInt());
+  spirv::Scope scope =
+      groupOp->getAttrOfType<spirv::ScopeAttr>(kExecutionScopeAttrName)
+          .getValue();
   if (scope != spirv::Scope::Workgroup && scope != spirv::Scope::Subgroup)
     return groupOp->emitOpError(
         "execution scope must be 'Workgroup' or 'Subgroup'");
 
-  spirv::GroupOperation operation = static_cast<spirv::GroupOperation>(
-      groupOp->getAttrOfType<IntegerAttr>(kGroupOperationAttrName).getInt());
+  spirv::GroupOperation operation =
+      groupOp->getAttrOfType<spirv::GroupOperationAttr>(kGroupOperationAttrName)
+          .getValue();
   if (operation == spirv::GroupOperation::ClusteredReduce &&
       groupOp->getNumOperands() == 1)
     return groupOp->emitOpError("cluster size operand must be provided for "
                                 "'ClusteredReduce' group operation");
   if (groupOp->getNumOperands() > 1) {
     Operation *sizeOp = groupOp->getOperand(1).getDefiningOp();
     int32_t clusterSize = 0;
 

 }
 
 static ParseResult parseAtomicCompareExchangeImpl(OpAsmParser &parser,
                                                   OperationState &state) {
   spirv::Scope memoryScope;
   spirv::MemorySemantics equalSemantics, unequalSemantics;
   SmallVector<OpAsmParser::UnresolvedOperand, 3> operandInfo;
   Type type;
-  if (parseEnumStrAttr(memoryScope, parser, state, kMemoryScopeAttrName) ||
-      parseEnumStrAttr(equalSemantics, parser, state,
-                       kEqualSemanticsAttrName) ||
-      parseEnumStrAttr(unequalSemantics, parser, state,
-                       kUnequalSemanticsAttrName) ||
+  if (parseEnumStrAttr<spirv::ScopeAttr>(memoryScope, parser, state,
+                                         kMemoryScopeAttrName) ||
+      parseEnumStrAttr<spirv::MemorySemanticsAttr>(
+          equalSemantics, parser, state, kEqualSemanticsAttrName) ||
+      parseEnumStrAttr<spirv::MemorySemanticsAttr>(
+          unequalSemantics, parser, state, kUnequalSemanticsAttrName) ||
       parser.parseOperandList(operandInfo, 3))
     return failure();
 
   auto loc = parser.getCurrentLocation();
   if (parser.parseColonType(type))
     return failure();
 
   auto ptrType = type.dyn_cast<spirv::PointerType>();

 }
 
 ParseResult spirv::AtomicExchangeOp::parse(OpAsmParser &parser,
                                            OperationState &state) {
   spirv::Scope memoryScope;
   spirv::MemorySemantics semantics;
   SmallVector<OpAsmParser::UnresolvedOperand, 2> operandInfo;
   Type type;
-  if (parseEnumStrAttr(memoryScope, parser, state, kMemoryScopeAttrName) ||
-      parseEnumStrAttr(semantics, parser, state, kSemanticsAttrName) ||
+  if (parseEnumStrAttr<spirv::ScopeAttr>(memoryScope, parser, state,
+                                         kMemoryScopeAttrName) ||
+      parseEnumStrAttr<spirv::MemorySemanticsAttr>(semantics, parser, state,
+                                                   kSemanticsAttrName) ||
       parser.parseOperandList(operandInfo, 2))
     return failure();
 
   auto loc = parser.getCurrentLocation();
   if (parser.parseColonType(type))
     return failure();
 
   auto ptrType = type.dyn_cast<spirv::PointerType>();

 ParseResult spirv::EntryPointOp::parse(OpAsmParser &parser,
                                        OperationState &state) {
   spirv::ExecutionModel execModel;
   SmallVector<OpAsmParser::UnresolvedOperand, 0> identifiers;
   SmallVector<Type, 0> idTypes;
   SmallVector<Attribute, 4> interfaceVars;
 
   FlatSymbolRefAttr fn;
-  if (parseEnumStrAttr(execModel, parser, state) ||
+  if (parseEnumStrAttr<spirv::ExecutionModelAttr>(execModel, parser, state) ||
       parser.parseAttribute(fn, Type(), kFnNameAttrName, state.attributes)) {
     return failure();
   }
 
   if (!parser.parseOptionalComma()) {
     // Parse the interface variables
     if (parser.parseCommaSeparatedList([&]() -> ParseResult {
           // The name of the interface variable attribute isnt important
build(builder, state, SymbolRefAttr::get(function),
         builder.getI32ArrayAttr(params));
 }
 
 ParseResult spirv::ExecutionModeOp::parse(OpAsmParser &parser,
                                           OperationState &state) {
   spirv::ExecutionMode execMode;
   Attribute fn;
   if (parser.parseAttribute(fn, kFnNameAttrName, state.attributes) ||
-      parseEnumStrAttr(execMode, parser, state)) {
+      parseEnumStrAttr<spirv::ExecutionModeAttr>(execMode, parser, state)) {
     return failure();
   }
 
   SmallVector<int32_t, 4> values;
   Type i32Type = parser.getBuilder().getIntegerType(32);
   while (!parser.parseOptionalComma()) {
     NamedAttrList attr;
     Attribute value;
ParseResult spirv::FuncOp::parse(OpAsmParser &parser, OperationState &state) {
   for (auto &arg : entryArgs)
     argTypes.push_back(arg.type);
   auto fnType = builder.getFunctionType(argTypes, resultTypes);
   state.addAttribute(FunctionOpInterface::getTypeAttrName(),
                      TypeAttr::get(fnType));
 
   // Parse the optional function control keyword.
   spirv::FunctionControl fnControl;
-  if (parseEnumStrAttr(fnControl, parser, state))
+  if (parseEnumStrAttr<spirv::FunctionControlAttr>(fnControl, parser, state))
     return failure();
 
   // If additional attributes are present, parse them.
   if (parser.parseOptionalAttrDictWithKeyword(state.attributes))
     return failure();
 
   // Add the attributes to the function arguments.
   assert(resultAttrs.size() == resultTypes.size());

 void spirv::FuncOp::build(OpBuilder &builder, OperationState &state,
                           StringRef name, FunctionType type,
                           spirv::FunctionControl control,
                           ArrayRef<NamedAttribute> attrs) {
   state.addAttribute(SymbolTable::getSymbolAttrName(),
                      builder.getStringAttr(name));
   state.addAttribute(getTypeAttrName(), TypeAttr::get(type));
   state.addAttribute(spirv::attributeName<spirv::FunctionControl>(),
-                     builder.getI32IntegerAttr(static_cast<uint32_t>(control)));
+                     builder.getAttr<spirv::FunctionControlAttr>(control));
   state.attributes.append(attrs.begin(), attrs.end());
   state.addRegion();
 }
 
 // CallableOpInterface
 Region *spirv::FuncOp::getCallableRegion() {
   return isExternal() ? nullptr : &body();
 }
LogicalResult spirv::LoadOp::verify() {
   return verifyMemoryAccessAttribute(*this);
 }
 
 //===----------------------------------------------------------------------===//
 // spv.mlir.loop
 //===----------------------------------------------------------------------===//
 
 void spirv::LoopOp::build(OpBuilder &builder, OperationState &state) {
-  state.addAttribute("loop_control",
-                     builder.getI32IntegerAttr(
-                         static_cast<uint32_t>(spirv::LoopControl::None)));
+  state.addAttribute("loop_control", builder.getAttr<spirv::LoopControlAttr>(
+                                         spirv::LoopControl::None));
   state.addRegion();
 }
 
 ParseResult spirv::LoopOp::parse(OpAsmParser &parser, OperationState &state) {
-  if (parseControlAttribute<spirv::LoopControl>(parser, state))
+  if (parseControlAttribute<spirv::LoopControlAttr, spirv::LoopControl>(parser,
+                                                                        state))
     return failure();
   return parser.parseRegion(*state.addRegion(), /*arguments=*/{},
                             /*argTypes=*/{});
 }
 
 void spirv::LoopOp::print(OpAsmPrinter &printer) {
   auto control = loop_control();
   if (control != spirv::LoopControl::None)

 
 void spirv::ModuleOp::build(OpBuilder &builder, OperationState &state,
                             spirv::AddressingModel addressingModel,
                             spirv::MemoryModel memoryModel,
                             Optional<VerCapExtAttr> vceTriple,
                             Optional<StringRef> name) {
   state.addAttribute(
       "addressing_model",
-      builder.getI32IntegerAttr(static_cast<int32_t>(addressingModel)));
-  state.addAttribute("memory_model", builder.getI32IntegerAttr(
-                                         static_cast<int32_t>(memoryModel)));
+      builder.getAttr<spirv::AddressingModelAttr>(addressingModel));
+  state.addAttribute("memory_model",
+                     builder.getAttr<spirv::MemoryModelAttr>(memoryModel));
   OpBuilder::InsertionGuard guard(builder);
   builder.createBlock(state.addRegion());
   if (vceTriple)
     state.addAttribute(getVCETripleAttrName(), *vceTriple);
   if (name)
     state.addAttribute(mlir::SymbolTable::getSymbolAttrName(),
                        builder.getStringAttr(*name));
 }
 
 ParseResult spirv::ModuleOp::parse(OpAsmParser &parser, OperationState &state) {
   Region *body = state.addRegion();
 
   // If the name is present, parse it.
   StringAttr nameAttr;
   (void)parser.parseOptionalSymbolName(
       nameAttr, mlir::SymbolTable::getSymbolAttrName(), state.attributes);
 
   // Parse attributes
   spirv::AddressingModel addrModel;
   spirv::MemoryModel memoryModel;
-  if (::parseEnumKeywordAttr(addrModel, parser, state) ||
-      ::parseEnumKeywordAttr(memoryModel, parser, state))
+  if (::parseEnumKeywordAttr<spirv::AddressingModelAttr>(addrModel, parser,
+                                                         state) ||
+      ::parseEnumKeywordAttr<spirv::MemoryModelAttr>(memoryModel, parser,
+                                                     state))
     return failure();
 
   if (succeeded(parser.parseOptionalKeyword("requires"))) {
     spirv::VerCapExtAttr vceTriple;
     if (parser.parseAttribute(vceTriple,
                               spirv::ModuleOp::getVCETripleAttrName(),
                               state.attributes))
       return failure();

 }
 
 //===----------------------------------------------------------------------===//
 // spv.mlir.selection
 //===----------------------------------------------------------------------===//
 
 ParseResult spirv::SelectionOp::parse(OpAsmParser &parser,
                                       OperationState &state) {
-  if (parseControlAttribute<spirv::SelectionControl>(parser, state))
+  if (parseControlAttribute<spirv::SelectionControlAttr,
+                            spirv::SelectionControl>(parser, state))
     return failure();
   return parser.parseRegion(*state.addRegion(), /*arguments=*/{},
                             /*argTypes=*/{});
 }
 
 void spirv::SelectionOp::print(OpAsmPrinter &printer) {
   auto control = selection_control();
   if (control != spirv::SelectionControl::None)
ParseResult spirv::VariableOp::parse(OpAsmParser &parser,
 
   // Resolve the initializer operand
   if (initInfo) {
     if (parser.resolveOperand(*initInfo, ptrType.getPointeeType(),
                               state.operands))
       return failure();
   }
 
-  auto attr = parser.getBuilder().getI32IntegerAttr(
-      llvm::bit_cast<int32_t>(ptrType.getStorageClass()));
+  auto attr = parser.getBuilder().getAttr<spirv::StorageClassAttr>(
+      ptrType.getStorageClass());
   state.addAttribute(spirv::attributeName<spirv::StorageClass>(), attr);
 
   return success();
 }
 
 void spirv::VariableOp::print(OpAsmPrinter &printer) {
   SmallVector<StringRef, 4> elidedAttrs{
       spirv::attributeName<spirv::StorageClass>()};

mlir/lib/TableGen/Attribute.cpp

Dialect Attribute::getDialect() const {
   const llvm::RecordVal *record = def->getValue("dialect");
   if (record && record->getValue()) {
     if (DefInit *init = dyn_cast<DefInit>(record->getValue()))
       return Dialect(init->getDef());
   }
   return Dialect(nullptr);
 }
 
+const llvm::Record &Attribute::getDef() const { return *def; }
+
 ConstantAttr::ConstantAttr(const DefInit *init) : def(init->getDef()) {
   assert(def->isSubClassOf("ConstantAttr") &&
          "must be subclass of TableGen 'ConstantAttr' class");
 }
 
 Attribute ConstantAttr::getAttribute() const {
   return Attribute(def->getValueAsDef("attr"));
 }

mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp

 //===- DeserializeOps.cpp - MLIR SPIR-V Deserialization (Ops) -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the Deserializer methods for SPIR-V binary instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Deserializer.h"
 
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/Location.h"
 #include "mlir/Target/SPIRV/SPIRVBinaryUtils.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
Deserializer::processOp<spirv::ExecutionModeOp>(ArrayRef<uint32_t> words) {
   opBuilder.create<spirv::ExecutionModeOp>(
       unknownLoc, SymbolRefAttr::get(opBuilder.getContext(), fn.getName()),
       execMode, values);
   return success();
 }
 
 template <>
 LogicalResult
-Deserializer::processOp<spirv::ControlBarrierOp>(ArrayRef<uint32_t> operands) {
-  if (operands.size() != 3) {
-    return emitError(
-        unknownLoc,
-        "OpControlBarrier must have execution scope <id>, memory scope <id> "
-        "and memory semantics <id>");
-  }
-
-  SmallVector<IntegerAttr, 3> argAttrs;
-  for (auto operand : operands) {
-    auto argAttr = getConstantInt(operand);
-    if (!argAttr) {
-      return emitError(unknownLoc,
-                       "expected 32-bit integer constant from <id> ")
-             << operand << " for OpControlBarrier";
-    }
-    argAttrs.push_back(argAttr);
-  }
-
-  opBuilder.create<spirv::ControlBarrierOp>(
-      unknownLoc, argAttrs[0].cast<spirv::ScopeAttr>(),
-      argAttrs[1].cast<spirv::ScopeAttr>(),
-      argAttrs[2].cast<spirv::MemorySemanticsAttr>());
-
-  return success();
-}
-
-template <>
-LogicalResult
 Deserializer::processOp<spirv::FunctionCallOp>(ArrayRef<uint32_t> operands) {
   if (operands.size() < 3) {
     return emitError(unknownLoc,
                      "OpFunctionCall must have at least 3 operands");
   }
 
   Type resultType = getType(operands[0]);
   if (!resultType) {
Deserializer::processOp<spirv::FunctionCallOp>(ArrayRef<uint32_t> operands) {
 
   if (resultType)
     valueMap[resultID] = opFunctionCall.getResult(0);
   return success();
 }
 
 template <>
 LogicalResult
-Deserializer::processOp<spirv::MemoryBarrierOp>(ArrayRef<uint32_t> operands) {
-  if (operands.size() != 2) {
-    return emitError(unknownLoc, "OpMemoryBarrier must have memory scope <id> "
-                                 "and memory semantics <id>");
-  }
-
-  SmallVector<IntegerAttr, 2> argAttrs;
-  for (auto operand : operands) {
-    auto argAttr = getConstantInt(operand);
-    if (!argAttr) {
-      return emitError(unknownLoc,
-                       "expected 32-bit integer constant from <id> ")
-             << operand << " for OpMemoryBarrier";
-    }
-    argAttrs.push_back(argAttr);
-  }
-
-  opBuilder.create<spirv::MemoryBarrierOp>(
-      unknownLoc, argAttrs[0].cast<spirv::ScopeAttr>(),
-      argAttrs[1].cast<spirv::MemorySemanticsAttr>());
-  return success();
-}
-
-template <>
-LogicalResult
 Deserializer::processOp<spirv::CopyMemoryOp>(ArrayRef<uint32_t> words) {
   SmallVector<Type, 1> resultTypes;
   size_t wordIndex = 0;
   SmallVector<Value, 4> operands;
   SmallVector<NamedAttribute, 4> attributes;
 
   if (wordIndex < words.size()) {
     auto arg = getValue(words[wordIndex]);
if (wordIndex < words.size()) {
     operands.push_back(arg);
     wordIndex++;
   }
 
   bool isAlignedAttr = false;
 
   if (wordIndex < words.size()) {
     auto attrValue = words[wordIndex++];
-    attributes.push_back(opBuilder.getNamedAttr(
-        "memory_access", opBuilder.getI32IntegerAttr(attrValue)));
+    auto attr = opBuilder.getAttr<spirv::MemoryAccessAttr>(
+        static_cast<spirv::MemoryAccess>(attrValue));
+    attributes.push_back(opBuilder.getNamedAttr("memory_access", attr));
     isAlignedAttr = (attrValue == 2);
   }
 
   if (isAlignedAttr && wordIndex < words.size()) {
     attributes.push_back(opBuilder.getNamedAttr(
         "alignment", opBuilder.getI32IntegerAttr(words[wordIndex++])));
   }
 
   if (wordIndex < words.size()) {
-    attributes.push_back(opBuilder.getNamedAttr(
-        "source_memory_access",
-        opBuilder.getI32IntegerAttr(words[wordIndex++])));
+    auto attrValue = words[wordIndex++];
+    auto attr = opBuilder.getAttr<spirv::MemoryAccessAttr>(
+        static_cast<spirv::MemoryAccess>(attrValue));
+    attributes.push_back(opBuilder.getNamedAttr("source_memory_access", attr));
   }
 
   if (wordIndex < words.size()) {
     attributes.push_back(opBuilder.getNamedAttr(
         "source_alignment", opBuilder.getI32IntegerAttr(words[wordIndex++])));
   }
 
   if (wordIndex != words.size()) {

mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp

 
 LogicalResult
 spirv::Deserializer::processMemoryModel(ArrayRef<uint32_t> operands) {
   if (operands.size() != 2)
     return emitError(unknownLoc, "OpMemoryModel must have two operands");
 
   (*module)->setAttr(
       "addressing_model",
-      opBuilder.getI32IntegerAttr(llvm::bit_cast<int32_t>(operands.front())));
-  (*module)->setAttr(
-      "memory_model",
-      opBuilder.getI32IntegerAttr(llvm::bit_cast<int32_t>(operands.back())));
+      opBuilder.getAttr<spirv::AddressingModelAttr>(
+          static_cast<spirv::AddressingModel>(operands.front())));
+  (*module)->setAttr("memory_model",
+                     opBuilder.getAttr<spirv::MemoryModelAttr>(
+                         static_cast<spirv::MemoryModel>(operands.back())));
 
   return success();
 }
 
 LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
   // TODO: This function should also be auto-generated. For now, since only a
   // few decorations are processed/handled in a meaningful manner, going with a
   // manual implementation.

mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp

 //===- SerializeOps.cpp - MLIR SPIR-V Serialization (Ops) -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the serialization methods for MLIR SPIR-V module ops.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Serializer.h"
 
 #include "mlir/Dialect/SPIRV/IR/SPIRVAttributes.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/IR/RegionGraphTraits.h"
 #include "mlir/Support/LogicalResult.h"
 #include "mlir/Target/SPIRV/SPIRVBinaryUtils.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "spirv-serialization"
 
if (failed(processType(op.getLoc(), op.getType(), resultTypeID))) {
     return failure();
   }
   operands.push_back(resultTypeID);
   resultID = getNextID();
   valueIDMap[op.getResult()] = resultID;
   operands.push_back(resultID);
   auto attr = op->getAttr(spirv::attributeName<spirv::StorageClass>());
   if (attr) {
-    operands.push_back(static_cast<uint32_t>(
-        attr.cast<IntegerAttr>().getValue().getZExtValue()));
+    operands.push_back(
+        static_cast<uint32_t>(attr.cast<spirv::StorageClassAttr>().getValue()));
   }
   elidedAttrs.push_back(spirv::attributeName<spirv::StorageClass>());
   for (auto arg : op.getODSOperands(0)) {
     auto argID = getValueID(arg);
     if (!argID) {
       return emitError(op.getLoc(), "operand 0 has a use before def");
     }
     operands.push_back(argID);
if (auto interface = op.interface()) {
     }
   }
   encodeInstructionInto(entryPoints, spirv::Opcode::OpEntryPoint, operands);
   return success();
 }
 
 template <>
 LogicalResult
-Serializer::processOp<spirv::ControlBarrierOp>(spirv::ControlBarrierOp op) {
-  StringRef argNames[] = {"execution_scope", "memory_scope",
-                          "memory_semantics"};
-  SmallVector<uint32_t, 3> operands;
-
-  for (auto argName : argNames) {
-    auto argIntAttr = op->getAttrOfType<IntegerAttr>(argName);
-    auto operand = prepareConstantInt(op.getLoc(), argIntAttr);
-    if (!operand) {
-      return failure();
-    }
-    operands.push_back(operand);
-  }
-
-  encodeInstructionInto(functionBody, spirv::Opcode::OpControlBarrier,
-                        operands);
-  return success();
-}
-
-template <>
-LogicalResult
 Serializer::processOp<spirv::ExecutionModeOp>(spirv::ExecutionModeOp op) {
   SmallVector<uint32_t, 4> operands;
   // Add the function <id>.
   auto funcID = getFunctionID(op.fn());
   if (!funcID) {
     return op.emitError("missing <id> for function ")
            << op.fn()
            << "; function needs to be serialized before ExecutionModeOp is "
Serializer::processOp<spirv::ExecutionModeOp>(spirv::ExecutionModeOp op) {
   }
   encodeInstructionInto(executionModes, spirv::Opcode::OpExecutionMode,
                         operands);
   return success();
 }
 
 template <>
 LogicalResult
-Serializer::processOp<spirv::MemoryBarrierOp>(spirv::MemoryBarrierOp op) {
-  StringRef argNames[] = {"memory_scope", "memory_semantics"};
-  SmallVector<uint32_t, 2> operands;
-
-  for (auto argName : argNames) {
-    auto argIntAttr = op->getAttrOfType<IntegerAttr>(argName);
-    auto operand = prepareConstantInt(op.getLoc(), argIntAttr);
-    if (!operand) {
-      return failure();
-    }
-    operands.push_back(operand);
-  }
-
-  encodeInstructionInto(functionBody, spirv::Opcode::OpMemoryBarrier, operands);
-  return success();
-}
-
-template <>
-LogicalResult
 Serializer::processOp<spirv::FunctionCallOp>(spirv::FunctionCallOp op) {
   auto funcName = op.callee();
   uint32_t resTypeID = 0;
 
   Type resultTy = op.getNumResults() ? *op.result_type_begin() : getVoidType();
   if (failed(processType(op.getLoc(), resultTy, resTypeID)))
     return failure();
 
Serializer::processOp<spirv::CopyMemoryOp>(spirv::CopyMemoryOp op) {
 
   for (Value operand : op->getOperands()) {
     auto id = getValueID(operand);
     assert(id && "use before def!");
     operands.push_back(id);
   }
 
   if (auto attr = op->getAttr("memory_access")) {
-    operands.push_back(static_cast<uint32_t>(
-        attr.cast<IntegerAttr>().getValue().getZExtValue()));
+    operands.push_back(
+        static_cast<uint32_t>(attr.cast<spirv::MemoryAccessAttr>().getValue()));
   }
 
   elidedAttrs.push_back("memory_access");
 
   if (auto attr = op->getAttr("alignment")) {
     operands.push_back(static_cast<uint32_t>(
         attr.cast<IntegerAttr>().getValue().getZExtValue()));
   }
 
   elidedAttrs.push_back("alignment");
 
   if (auto attr = op->getAttr("source_memory_access")) {
-    operands.push_back(static_cast<uint32_t>(
-        attr.cast<IntegerAttr>().getValue().getZExtValue()));
+    operands.push_back(
+        static_cast<uint32_t>(attr.cast<spirv::MemoryAccessAttr>().getValue()));
   }
 
   elidedAttrs.push_back("source_memory_access");
 
   if (auto attr = op->getAttr("source_alignment")) {
     operands.push_back(static_cast<uint32_t>(
         attr.cast<IntegerAttr>().getValue().getZExtValue()));
   }

mlir/lib/Target/SPIRV/Serialization/Serializer.cpp

 //===- Serializer.cpp - MLIR SPIR-V Serializer ----------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the MLIR SPIR-V module to SPIR-V binary serializer.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Serializer.h"
 
 #include "mlir/Dialect/SPIRV/IR/SPIRVAttributes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
 #include "mlir/Support/LogicalResult.h"
 #include "mlir/Target/SPIRV/SPIRVBinaryUtils.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/TypeSwitch.h"
 #include "llvm/ADT/bit.h"
 #include "llvm/Support/Debug.h"
+#include <cstdint>
 
 #define DEBUG_TYPE "spirv-serialization"
 
 using namespace mlir;
 
 /// Returns the merge block if the given `op` is a structured control flow op.
 /// Otherwise returns nullptr.
 static Block *getStructuredControlFlowOpMergeBlock(Operation *op) {
void Serializer::processExtension() {
   for (spirv::Extension ext : module.vce_triple()->getExtensions()) {
     extName.clear();
     spirv::encodeStringLiteralInto(extName, spirv::stringifyExtension(ext));
     encodeInstructionInto(extensions, spirv::Opcode::OpExtension, extName);
   }
 }
 
 void Serializer::processMemoryModel() {
-  uint32_t mm = module->getAttrOfType<IntegerAttr>("memory_model").getInt();
-  uint32_t am = module->getAttrOfType<IntegerAttr>("addressing_model").getInt();
+  uint32_t mm = static_cast<uint32_t>(
+      module->getAttrOfType<spirv::MemoryModelAttr>("memory_model").getValue());
+  uint32_t am = static_cast<uint32_t>(
+      module->getAttrOfType<spirv::AddressingModelAttr>("addressing_model")
+          .getValue());
 
   encodeInstructionInto(memoryModel, spirv::Opcode::OpMemoryModel, {am, mm});
 }
 
 LogicalResult Serializer::processDecoration(Location loc, uint32_t resultID,
                                             NamedAttribute attr) {
   auto attrName = attr.getName().strref();
   auto decorationName = llvm::convertToCamelFromSnakeCase(attrName, true);

mlir/test/Conversion/GPUToSPIRV/simple.mlir

 
 // -----
 
 module attributes {gpu.container_module} {
   gpu.module @kernels {
     // CHECK-LABEL: spv.func @barrier
     gpu.func @barrier(%arg0 : f32, %arg1 : memref<12xf32>) kernel
       attributes {spv.entry_point_abi = #spv.entry_point_abi<local_size = dense<[32, 4, 1]>: vector<3xi32>>} {
-      // CHECK: spv.ControlBarrier Workgroup, Workgroup, "AcquireRelease|WorkgroupMemory"
+      // CHECK: spv.ControlBarrier <Workgroup>, <Workgroup>, <AcquireRelease|WorkgroupMemory>
       gpu.barrier
       gpu.return
     }
   }
 
   func.func @main() {
     %0 = "op"() : () -> (f32)
     %1 = "op"() : () -> (memref<12xf32>)
     %cst = arith.constant 1 : index
     gpu.launch_func @kernels::@barrier
         blocks in (%cst, %cst, %cst) threads in (%cst, %cst, %cst)
         args(%0 : f32, %1 : memref<12xf32>)
     return
   }
 }

mlir/test/Conversion/LinalgToSPIRV/linalg-to-spirv.mlir

 // CHECK:        %[[ID:.+]] = spv.Load "Input" %{{.+}} : vector<3xi32>
 // CHECK:        %[[X:.+]] = spv.CompositeExtract %[[ID]][0 : i32]
 
 // CHECK:        %[[INPTR:.+]] = spv.AccessChain %[[INPUT]][%[[ZERO]], %[[X]]]
 // CHECK:        %[[VAL:.+]] = spv.Load "StorageBuffer" %[[INPTR]] : i32
 // CHECK:        %[[ADD:.+]] = spv.GroupNonUniformIAdd "Subgroup" "Reduce" %[[VAL]] : i32
 
 // CHECK:        %[[OUTPTR:.+]] = spv.AccessChain %[[OUTPUT]][%[[ZERO]], %[[ZERO]]]
-// CHECK:        %[[ELECT:.+]] = spv.GroupNonUniformElect Subgroup : i1
+// CHECK:        %[[ELECT:.+]] = spv.GroupNonUniformElect <Subgroup> : i1
 
 // CHECK:        spv.mlir.selection {
 // CHECK:          spv.BranchConditional %[[ELECT]], ^bb1, ^bb2
 // CHECK:        ^bb1:
 // CHECK:          spv.AtomicIAdd "Device" "AcquireRelease" %[[OUTPTR]], %[[ADD]]
 // CHECK:          spv.Branch ^bb2
 // CHECK:        ^bb2:
 // CHECK:          spv.mlir.merge

mlir/test/Conversion/MemRefToSPIRV/map-storage-class.mlir

 // RUN: mlir-opt -split-input-file -allow-unregistered-dialect -map-memref-spirv-storage-class='client-api=vulkan' -verify-diagnostics %s -o - | FileCheck %s --check-prefix=VULKAN
 
 // Vulkan Mappings:
-//   0 -> StorageBuffer (12)
-//   1 -> Generic (8)
-//   3 -> Workgroup (4)
-//   4 -> Uniform (2)
-// TODO: create a StorageClass wrapper class so we can print the symbolc
-// storage class (instead of the backing IntegerAttr) and be able to
-// round trip the IR.
+//   0 -> StorageBuffer
+//   1 -> Generic
+//   2 -> [null]
+//   3 -> Workgroup
+//   4 -> Uniform
 
 // VULKAN-LABEL: func @operand_result
 func.func @operand_result() {
-  // VULKAN: memref<f32, 12 : i32>
+  // VULKAN: memref<f32, #spv.storage_class<StorageBuffer>>
   %0 = "dialect.memref_producer"() : () -> (memref<f32>)
-  // VULKAN: memref<4xi32, 8 : i32>
+  // VULKAN: memref<4xi32, #spv.storage_class<Generic>>
   %1 = "dialect.memref_producer"() : () -> (memref<4xi32, 1>)
-  // VULKAN: memref<?x4xf16, 4 : i32>
+  // VULKAN: memref<?x4xf16, #spv.storage_class<Workgroup>>
   %2 = "dialect.memref_producer"() : () -> (memref<?x4xf16, 3>)
-  // VULKAN: memref<*xf16, 2 : i32>
+  // VULKAN: memref<*xf16, #spv.storage_class<Uniform>>
   %3 = "dialect.memref_producer"() : () -> (memref<*xf16, 4>)
 
 
   "dialect.memref_consumer"(%0) : (memref<f32>) -> ()
-  // VULKAN: memref<4xi32, 8 : i32>
+  // VULKAN: memref<4xi32, #spv.storage_class<Generic>>
   "dialect.memref_consumer"(%1) : (memref<4xi32, 1>) -> ()
-  // VULKAN: memref<?x4xf16, 4 : i32>
+  // VULKAN: memref<?x4xf16, #spv.storage_class<Workgroup>>
   "dialect.memref_consumer"(%2) : (memref<?x4xf16, 3>) -> ()
-  // VULKAN: memref<*xf16, 2 : i32>
+  // VULKAN: memref<*xf16, #spv.storage_class<Uniform>>
   "dialect.memref_consumer"(%3) : (memref<*xf16, 4>) -> ()
 
   return
 }
 
 // -----
 
 // VULKAN-LABEL: func @type_attribute
 func.func @type_attribute() {
-  // VULKAN: attr = memref<i32, 8 : i32>
+  // VULKAN: attr = memref<i32, #spv.storage_class<Generic>>
   "dialect.memref_producer"() { attr = memref<i32, 1> } : () -> ()
   return
 }
 
 // -----
 
 // VULKAN-LABEL: func @function_io
 func.func @function_io
-  // VULKAN-SAME: (%{{.+}}: memref<f64, 8 : i32>, %{{.+}}: memref<4xi32, 4 : i32>)
+  // VULKAN-SAME: (%{{.+}}: memref<f64, #spv.storage_class<Generic>>, %{{.+}}: memref<4xi32, #spv.storage_class<Workgroup>>)
   (%arg0: memref<f64, 1>, %arg1: memref<4xi32, 3>)
-  // VULKAN-SAME: -> (memref<f64, 8 : i32>, memref<4xi32, 4 : i32>)
+  // VULKAN-SAME: -> (memref<f64, #spv.storage_class<Generic>>, memref<4xi32, #spv.storage_class<Workgroup>>)
   -> (memref<f64, 1>, memref<4xi32, 3>) {
   return %arg0, %arg1: memref<f64, 1>, memref<4xi32, 3>
 }
 
 // -----
 
 // VULKAN: func @region
 func.func @region(%cond: i1, %arg0: memref<f32, 1>) {
   scf.if %cond {
-    //      VULKAN: "dialect.memref_consumer"(%{{.+}}) {attr = memref<i64, 4 : i32>}
-    // VULKAN-SAME: (memref<f32, 8 : i32>) -> memref<f32, 8 : i32>
+    //      VULKAN: "dialect.memref_consumer"(%{{.+}}) {attr = memref<i64, #spv.storage_class<Workgroup>>}
+    // VULKAN-SAME: (memref<f32, #spv.storage_class<Generic>>) -> memref<f32, #spv.storage_class<Generic>>
     %0 = "dialect.memref_consumer"(%arg0) { attr = memref<i64, 3> } : (memref<f32, 1>) -> (memref<f32, 1>)
   }
   return
 }
 
 // -----
 
 // VULKAN-LABEL: func @non_memref_types

mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir

 // RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
 
 //===----------------------------------------------------------------------===//
 // spv.AtomicAnd
 //===----------------------------------------------------------------------===//
 
 func.func @atomic_and(%ptr : !spv.ptr<i32, StorageBuffer>, %value : i32) -> i32 {
   // CHECK: spv.AtomicAnd "Device" "None" %{{.*}}, %{{.*}} : !spv.ptr<i32, StorageBuffer>
   %0 = spv.AtomicAnd "Device" "None" %ptr, %value : !spv.ptr<i32, StorageBuffer>
   return %0 : i32
 }
 
 // -----
 
 func.func @atomic_and(%ptr : !spv.ptr<f32, StorageBuffer>, %value : i32) -> i32 {
   // expected-error @+1 {{pointer operand must point to an integer value, found 'f32'}}
-  %0 = "spv.AtomicAnd"(%ptr, %value) {memory_scope = 4: i32, semantics = 0x4 : i32} : (!spv.ptr<f32, StorageBuffer>, i32) -> (i32)
+  %0 = "spv.AtomicAnd"(%ptr, %value) {memory_scope = #spv.scope<Workgroup>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<f32, StorageBuffer>, i32) -> (i32)
   return %0 : i32
 }
 
 
 // -----
 
 func.func @atomic_and(%ptr : !spv.ptr<i32, StorageBuffer>, %value : i64) -> i64 {
   // expected-error @+1 {{expected value to have the same type as the pointer operand's pointee type 'i32', but found 'i64'}}
-  %0 = "spv.AtomicAnd"(%ptr, %value) {memory_scope = 2: i32, semantics = 0x8 : i32} : (!spv.ptr<i32, StorageBuffer>, i64) -> (i64)
+  %0 = "spv.AtomicAnd"(%ptr, %value) {memory_scope = #spv.scope<Workgroup>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, StorageBuffer>, i64) -> (i64)
   return %0 : i64
 }
 
 // -----
 
 func.func @atomic_and(%ptr : !spv.ptr<i32, StorageBuffer>, %value : i32) -> i32 {
   // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
   %0 = spv.AtomicAnd "Device" "Acquire|Release" %ptr, %value : !spv.ptr<i32, StorageBuffer>
func.func @atomic_compare_exchange(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
   %0 = spv.AtomicCompareExchange "Workgroup" "Release" "Acquire" %ptr, %value, %comparator: !spv.ptr<i32, Workgroup>
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange(%ptr: !spv.ptr<i32, Workgroup>, %value: i64, %comparator: i32) -> i32 {
   // expected-error @+1 {{value operand must have the same type as the op result, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i32, Workgroup>, i64, i32) -> (i32)
+  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, Workgroup>, i64, i32) -> (i32)
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i16) -> i32 {
   // expected-error @+1 {{comparator operand must have the same type as the op result, but found 'i16' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i32, Workgroup>, i32, i16) -> (i32)
+  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, Workgroup>, i32, i16) -> (i32)
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange(%ptr: !spv.ptr<i64, Workgroup>, %value: i32, %comparator: i32) -> i32 {
   // expected-error @+1 {{pointer operand's pointee type must have the same as the op result type, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i64, Workgroup>, i32, i32) -> (i32)
+  %0 = "spv.AtomicCompareExchange"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i64, Workgroup>, i32, i32) -> (i32)
   return %0: i32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.AtomicCompareExchangeWeak
 //===----------------------------------------------------------------------===//
 
 func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
   // CHECK: spv.AtomicCompareExchangeWeak "Workgroup" "Release" "Acquire" %{{.*}}, %{{.*}}, %{{.*}} : !spv.ptr<i32, Workgroup>
   %0 = spv.AtomicCompareExchangeWeak "Workgroup" "Release" "Acquire" %ptr, %value, %comparator: !spv.ptr<i32, Workgroup>
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i32, Workgroup>, %value: i64, %comparator: i32) -> i32 {
   // expected-error @+1 {{value operand must have the same type as the op result, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i32, Workgroup>, i64, i32) -> (i32)
+  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, Workgroup>, i64, i32) -> (i32)
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i16) -> i32 {
   // expected-error @+1 {{comparator operand must have the same type as the op result, but found 'i16' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i32, Workgroup>, i32, i16) -> (i32)
+  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, Workgroup>, i32, i16) -> (i32)
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i64, Workgroup>, %value: i32, %comparator: i32) -> i32 {
   // expected-error @+1 {{pointer operand's pointee type must have the same as the op result type, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = 4: i32, equal_semantics = 0x4: i32, unequal_semantics = 0x2:i32} : (!spv.ptr<i64, Workgroup>, i32, i32) -> (i32)
+  %0 = "spv.AtomicCompareExchangeWeak"(%ptr, %value, %comparator) {memory_scope = #spv.scope<Workgroup>, equal_semantics = #spv.memory_semantics<AcquireRelease>, unequal_semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i64, Workgroup>, i32, i32) -> (i32)
   return %0: i32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.AtomicExchange
 //===----------------------------------------------------------------------===//
 
 func.func @atomic_exchange(%ptr: !spv.ptr<i32, Workgroup>, %value: i32) -> i32 {
   // CHECK: spv.AtomicExchange "Workgroup" "Release" %{{.*}}, %{{.*}} : !spv.ptr<i32, Workgroup>
   %0 = spv.AtomicExchange "Workgroup" "Release" %ptr, %value: !spv.ptr<i32, Workgroup>
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_exchange(%ptr: !spv.ptr<i32, Workgroup>, %value: i64) -> i32 {
   // expected-error @+1 {{value operand must have the same type as the op result, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicExchange"(%ptr, %value) {memory_scope = 4: i32, semantics = 0x4: i32} : (!spv.ptr<i32, Workgroup>, i64) -> (i32)
+  %0 = "spv.AtomicExchange"(%ptr, %value) {memory_scope = #spv.scope<Workgroup>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, Workgroup>, i64) -> (i32)
   return %0: i32
 }
 
 // -----
 
 func.func @atomic_exchange(%ptr: !spv.ptr<i64, Workgroup>, %value: i32) -> i32 {
   // expected-error @+1 {{pointer operand's pointee type must have the same as the op result type, but found 'i64' vs 'i32'}}
-  %0 = "spv.AtomicExchange"(%ptr, %value) {memory_scope = 4: i32, semantics = 0x4: i32} : (!spv.ptr<i64, Workgroup>, i32) -> (i32)
+  %0 = "spv.AtomicExchange"(%ptr, %value) {memory_scope = #spv.scope<Workgroup>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i64, Workgroup>, i32) -> (i32)
   return %0: i32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.AtomicIAdd
 //===----------------------------------------------------------------------===//
func.func @atomic_fadd(%ptr : !spv.ptr<f32, StorageBuffer>, %value : f32) -> f32 {
   %0 = spv.AtomicFAddEXT "Device" "None" %ptr, %value : !spv.ptr<f32, StorageBuffer>
   return %0 : f32
 }
 
 // -----
 
 func.func @atomic_fadd(%ptr : !spv.ptr<i32, StorageBuffer>, %value : f32) -> f32 {
   // expected-error @+1 {{pointer operand must point to an float value, found 'i32'}}
-  %0 = "spv.AtomicFAddEXT"(%ptr, %value) {memory_scope = 4: i32, semantics = 0x4 : i32} : (!spv.ptr<i32, StorageBuffer>, f32) -> (f32)
+  %0 = "spv.AtomicFAddEXT"(%ptr, %value) {memory_scope = #spv.scope<Workgroup>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<i32, StorageBuffer>, f32) -> (f32)
   return %0 : f32
 }
 
 // -----
 
 func.func @atomic_fadd(%ptr : !spv.ptr<f32, StorageBuffer>, %value : f64) -> f64 {
   // expected-error @+1 {{expected value to have the same type as the pointer operand's pointee type 'f32', but found 'f64'}}
-  %0 = "spv.AtomicFAddEXT"(%ptr, %value) {memory_scope = 2: i32, semantics = 0x8 : i32} : (!spv.ptr<f32, StorageBuffer>, f64) -> (f64)
+  %0 = "spv.AtomicFAddEXT"(%ptr, %value) {memory_scope = #spv.scope<Device>, semantics = #spv.memory_semantics<AcquireRelease>} : (!spv.ptr<f32, StorageBuffer>, f64) -> (f64)
   return %0 : f64
 }
 
 // -----
 
 func.func @atomic_fadd(%ptr : !spv.ptr<f32, StorageBuffer>, %value : f32) -> f32 {
   // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
   %0 = spv.AtomicFAddEXT "Device" "Acquire|Release" %ptr, %value : !spv.ptr<f32, StorageBuffer>
   return %0 : f32
 }

mlir/test/Dialect/SPIRV/IR/availability.mlir

 }
 
 // CHECK-LABEL: subgroup_ballot
 func.func @subgroup_ballot(%predicate: i1) -> vector<4xi32> {
   // CHECK: min version: v1.3
   // CHECK: max version: v1.6
   // CHECK: extensions: [ ]
   // CHECK: capabilities: [ [GroupNonUniformBallot] ]
-  %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
+  %0 = spv.GroupNonUniformBallot <Workgroup> %predicate : vector<4xi32>
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: module_logical_glsl450
 func.func @module_logical_glsl450() {
   // CHECK: spv.module min version: v1.0
   // CHECK: spv.module max version: v1.6
   // CHECK: spv.module extensions: [ ]

mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir

 // RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
 
 //===----------------------------------------------------------------------===//
 // spv.ControlBarrier
 //===----------------------------------------------------------------------===//
 
 func.func @control_barrier_0() -> () {
-  // CHECK:  spv.ControlBarrier Workgroup, Device, "Acquire|UniformMemory"
-  spv.ControlBarrier Workgroup, Device, "Acquire|UniformMemory"
+  // CHECK: spv.ControlBarrier <Workgroup>, <Device>, <Acquire|UniformMemory>
+  spv.ControlBarrier <Workgroup>, <Device>, <Acquire|UniformMemory>
   return
 }
 
 // -----
 
 func.func @control_barrier_1() -> () {
-  // expected-error @+1 {{expected string or keyword containing one of the following enum values}}
-  spv.ControlBarrier Something, Device, "Acquire|UniformMemory"
+  // expected-error @+2 {{to be one of}}
+  // expected-error @+1 {{failed to parse SPV_ScopeAttr}}
+  spv.ControlBarrier <Something>, <Device>, <Acquire|UniformMemory>
   return
 }
 
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.MemoryBarrier
 //===----------------------------------------------------------------------===//
 
 func.func @memory_barrier_0() -> () {
-  // CHECK: spv.MemoryBarrier Device, "Acquire|UniformMemory"
-  spv.MemoryBarrier Device, "Acquire|UniformMemory"
+  // CHECK: spv.MemoryBarrier <Device>, <Acquire|UniformMemory>
+  spv.MemoryBarrier <Device>, <Acquire|UniformMemory>
   return
 }
 
 // -----
 
 func.func @memory_barrier_1() -> () {
-  // CHECK: spv.MemoryBarrier Workgroup, Acquire
-  spv.MemoryBarrier Workgroup, Acquire
+  // CHECK: spv.MemoryBarrier <Workgroup>, <Acquire>
+  spv.MemoryBarrier <Workgroup>, <Acquire>
   return
 }
 
 // -----
 
 func.func @memory_barrier_2() -> () {
  // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
-  spv.MemoryBarrier Device, "Acquire|Release"
+  spv.MemoryBarrier <Device>, <Acquire|Release>
   return
 }
 

mlir/test/Dialect/SPIRV/IR/group-ops.mlir

 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.GroupBroadcast
 //===----------------------------------------------------------------------===//
 
 func.func @group_broadcast_scalar(%value: f32, %localid: i32 ) -> f32 {
-  // CHECK: spv.GroupBroadcast Workgroup %{{.*}}, %{{.*}} : f32, i32
-  %0 = spv.GroupBroadcast Workgroup %value, %localid : f32, i32
+  // CHECK: spv.GroupBroadcast <Workgroup> %{{.*}}, %{{.*}} : f32, i32
+  %0 = spv.GroupBroadcast <Workgroup> %value, %localid : f32, i32
   return %0: f32
 }
 
 // -----
 
 func.func @group_broadcast_scalar_vector(%value: f32, %localid: vector<3xi32> ) -> f32 {
-  // CHECK: spv.GroupBroadcast Workgroup %{{.*}}, %{{.*}} : f32, vector<3xi32>
-  %0 = spv.GroupBroadcast Workgroup %value, %localid : f32, vector<3xi32>
+  // CHECK: spv.GroupBroadcast <Workgroup> %{{.*}}, %{{.*}} : f32, vector<3xi32>
+  %0 = spv.GroupBroadcast <Workgroup> %value, %localid : f32, vector<3xi32>
   return %0: f32
 }
 
 // -----
 
 func.func @group_broadcast_vector(%value: vector<4xf32>, %localid: vector<3xi32> ) -> vector<4xf32> {
-  // CHECK: spv.GroupBroadcast Subgroup %{{.*}}, %{{.*}} : vector<4xf32>, vector<3xi32>
-  %0 = spv.GroupBroadcast Subgroup %value, %localid : vector<4xf32>, vector<3xi32>
+  // CHECK: spv.GroupBroadcast <Subgroup> %{{.*}}, %{{.*}} : vector<4xf32>, vector<3xi32>
+  %0 = spv.GroupBroadcast <Subgroup> %value, %localid : vector<4xf32>, vector<3xi32>
   return %0: vector<4xf32>
 }
 
 // -----
 
 func.func @group_broadcast_negative_scope(%value: f32, %localid: vector<3xi32> ) -> f32 {
   // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}} 
-  %0 = spv.GroupBroadcast Device %value, %localid : f32, vector<3xi32>
+  %0 = spv.GroupBroadcast <Device> %value, %localid : f32, vector<3xi32>
   return %0: f32
 }
 
 // -----
 
 func.func @group_broadcast_negative_locid_dtype(%value: f32, %localid: vector<3xf32> ) -> f32 {
   // expected-error @+1 {{operand #1 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values}}
-  %0 = spv.GroupBroadcast Subgroup %value, %localid : f32, vector<3xf32>
+  %0 = spv.GroupBroadcast <Subgroup> %value, %localid : f32, vector<3xf32>
   return %0: f32
 }
 
 // -----
 
 func.func @group_broadcast_negative_locid_vec4(%value: f32, %localid: vector<4xi32> ) -> f32 {
   // expected-error @+1 {{localid is a vector and can be with only  2 or 3 components, actual number is 4}}
-  %0 = spv.GroupBroadcast Subgroup %value, %localid : f32, vector<4xi32>
+  %0 = spv.GroupBroadcast <Subgroup> %value, %localid : f32, vector<4xi32>
   return %0: f32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.SubgroupBallotKHR
 //===----------------------------------------------------------------------===//

mlir/test/Dialect/SPIRV/IR/memory-ops.mlir

 
 // -----
 
 // CHECK-LABEL: load_none_access
 func.func @load_none_access() -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Load
   // CHECK-SAME: ["None"]
-  %1 = "spv.Load"(%0) {memory_access = 0 : i32} : (!spv.ptr<f32, Function>) -> (f32)
+  %1 = "spv.Load"(%0) {memory_access = #spv.memory_access<None>} : (!spv.ptr<f32, Function>) -> (f32)
   return
 }
 
 // CHECK-LABEL: volatile_load
 func.func @volatile_load() -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Load
   // CHECK-SAME: ["Volatile"]
-  %1 = "spv.Load"(%0) {memory_access = 1 : i32} : (!spv.ptr<f32, Function>) -> (f32)
+  %1 = "spv.Load"(%0) {memory_access = #spv.memory_access<Volatile>} : (!spv.ptr<f32, Function>) -> (f32)
   return
 }
 
 // CHECK-LABEL: aligned_load
 func.func @aligned_load() -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Load
   // CHECK-SAME: ["Aligned", 4]
-  %1 = "spv.Load"(%0) {memory_access = 2 : i32, alignment = 4 : i32} : (!spv.ptr<f32, Function>) -> (f32)
+  %1 = "spv.Load"(%0) {memory_access = #spv.memory_access<Aligned>, alignment = 4 : i32} : (!spv.ptr<f32, Function>) -> (f32)
   return
 }
 
 // CHECK-LABEL: volatile_aligned_load
 func.func @volatile_aligned_load() -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Load
   // CHECK-SAME: ["Volatile|Aligned", 4]
-  %1 = "spv.Load"(%0) {memory_access = 3 : i32, alignment = 4 : i32} : (!spv.ptr<f32, Function>) -> (f32)
+  %1 = "spv.Load"(%0) {memory_access = #spv.memory_access<Volatile|Aligned>, alignment = 4 : i32} : (!spv.ptr<f32, Function>) -> (f32)
   return
 }
 
 // -----
 
 func.func @simple_load_missing_storageclass() -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // expected-error @+1 {{expected attribute value}}

 }
 
 // -----
 
 func.func @copy_memory_invalid_maa() {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   %1 = spv.Variable : !spv.ptr<f32, Function>
   // expected-error @+1 {{missing alignment value}}
-  "spv.CopyMemory"(%0, %1) {memory_access=0x0002 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {memory_access=#spv.memory_access<Aligned>} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
   spv.Return
 }
 
 // -----
 
 func.func @copy_memory_invalid_source_maa() {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   %1 = spv.Variable : !spv.ptr<f32, Function>
   // expected-error @+1 {{invalid alignment specification with non-aligned memory access specification}}
-  "spv.CopyMemory"(%0, %1) {source_memory_access=0x0001 : i32, memory_access=0x0002 : i32, source_alignment=8 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {source_memory_access=#spv.memory_access<Volatile>, memory_access=#spv.memory_access<Aligned>, source_alignment=8 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
   spv.Return
 }
 
 // -----
 
 func.func @copy_memory_invalid_source_maa2() {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   %1 = spv.Variable : !spv.ptr<f32, Function>
   // expected-error @+1 {{missing alignment value}}
-  "spv.CopyMemory"(%0, %1) {source_memory_access=0x0002 : i32, memory_access=0x0002 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {source_memory_access=#spv.memory_access<Aligned>, memory_access=#spv.memory_access<Aligned>, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
   spv.Return
 }
 
 // -----
 
 func.func @copy_memory_print_maa() {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   %1 = spv.Variable : !spv.ptr<f32, Function>
 
   // CHECK: spv.CopyMemory "Function" %{{.*}}, "Function" %{{.*}} ["Volatile"] : f32
-  "spv.CopyMemory"(%0, %1) {memory_access=0x0001 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {memory_access=#spv.memory_access<Volatile>} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
 
   // CHECK: spv.CopyMemory "Function" %{{.*}}, "Function" %{{.*}} ["Aligned", 4] : f32
-  "spv.CopyMemory"(%0, %1) {memory_access=0x0002 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {memory_access=#spv.memory_access<Aligned>, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
 
   // CHECK: spv.CopyMemory "Function" %{{.*}}, "Function" %{{.*}} ["Aligned", 4], ["Volatile"] : f32
-  "spv.CopyMemory"(%0, %1) {source_memory_access=0x0001 : i32, memory_access=0x0002 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {source_memory_access=#spv.memory_access<Volatile>, memory_access=#spv.memory_access<Aligned>, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
 
   // CHECK: spv.CopyMemory "Function" %{{.*}}, "Function" %{{.*}} ["Aligned", 4], ["Aligned", 8] : f32
-  "spv.CopyMemory"(%0, %1) {source_memory_access=0x0002 : i32, memory_access=0x0002 : i32, source_alignment=8 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
+  "spv.CopyMemory"(%0, %1) {source_memory_access=#spv.memory_access<Aligned>, memory_access=#spv.memory_access<Aligned>, source_alignment=8 : i32, alignment=4 : i32} : (!spv.ptr<f32, Function>, !spv.ptr<f32, Function>) -> ()
 
   spv.Return
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.PtrAccessChain

mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir

 // RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
 
 //===----------------------------------------------------------------------===//
 // spv.GroupNonUniformBallot
 //===----------------------------------------------------------------------===//
 
 func.func @group_non_uniform_ballot(%predicate: i1) -> vector<4xi32> {
-  // CHECK: %{{.*}} = spv.GroupNonUniformBallot Workgroup %{{.*}}: vector<4xi32>
-  %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
+  // CHECK: %{{.*}} = spv.GroupNonUniformBallot <Workgroup> %{{.*}}: vector<4xi32>
+  %0 = spv.GroupNonUniformBallot <Workgroup> %predicate : vector<4xi32>
   return %0: vector<4xi32>
 }
 
 // -----
 
 func.func @group_non_uniform_ballot(%predicate: i1) -> vector<4xi32> {
   // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
-  %0 = spv.GroupNonUniformBallot Device %predicate : vector<4xi32>
+  %0 = spv.GroupNonUniformBallot <Device> %predicate : vector<4xi32>
   return %0: vector<4xi32>
 }
 
 // -----
 
 func.func @group_non_uniform_ballot(%predicate: i1) -> vector<4xsi32> {
   // expected-error @+1 {{op result #0 must be vector of 8/16/32/64-bit signless/unsigned integer values of length 4, but got 'vector<4xsi32>'}}
-  %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xsi32>
+  %0 = spv.GroupNonUniformBallot <Workgroup> %predicate : vector<4xsi32>
   return %0: vector<4xsi32>
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.NonUniformGroupBroadcast
 //===----------------------------------------------------------------------===//
 
 func.func @group_non_uniform_broadcast_scalar(%value: f32) -> f32 {
   %one = spv.Constant 1 : i32
-  // CHECK: spv.GroupNonUniformBroadcast Workgroup %{{.*}}, %{{.*}} : f32, i32
-  %0 = spv.GroupNonUniformBroadcast Workgroup %value, %one : f32, i32
+  // CHECK: spv.GroupNonUniformBroadcast <Workgroup> %{{.*}}, %{{.*}} : f32, i32
+  %0 = spv.GroupNonUniformBroadcast <Workgroup> %value, %one : f32, i32
   return %0: f32
 }
 
 // -----
 
 func.func @group_non_uniform_broadcast_vector(%value: vector<4xf32>) -> vector<4xf32> {
   %one = spv.Constant 1 : i32
-  // CHECK: spv.GroupNonUniformBroadcast Subgroup %{{.*}}, %{{.*}} : vector<4xf32>, i32
-  %0 = spv.GroupNonUniformBroadcast Subgroup %value, %one : vector<4xf32>, i32
+  // CHECK: spv.GroupNonUniformBroadcast <Subgroup> %{{.*}}, %{{.*}} : vector<4xf32>, i32
+  %0 = spv.GroupNonUniformBroadcast <Subgroup> %value, %one : vector<4xf32>, i32
   return %0: vector<4xf32>
 }
 
 // -----
 
 func.func @group_non_uniform_broadcast_negative_scope(%value: f32, %localid: i32 ) -> f32 {
   %one = spv.Constant 1 : i32
   // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}} 
-  %0 = spv.GroupNonUniformBroadcast Device %value, %one : f32, i32
+  %0 = spv.GroupNonUniformBroadcast <Device> %value, %one : f32, i32
   return %0: f32
 }
 
 // -----
 
 func.func @group_non_uniform_broadcast_negative_non_const(%value: f32, %localid: i32) -> f32 {
   // expected-error @+1 {{id must be the result of a constant op}}
-  %0 = spv.GroupNonUniformBroadcast Subgroup %value, %localid : f32, i32
+  %0 = spv.GroupNonUniformBroadcast <Subgroup> %value, %localid : f32, i32
   return %0: f32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.GroupNonUniformElect
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @group_non_uniform_elect
 func.func @group_non_uniform_elect() -> i1 {
-  // CHECK: %{{.+}} = spv.GroupNonUniformElect Workgroup : i1
-  %0 = spv.GroupNonUniformElect Workgroup : i1
+  // CHECK: %{{.+}} = spv.GroupNonUniformElect <Workgroup> : i1
+  %0 = spv.GroupNonUniformElect <Workgroup> : i1
   return %0: i1
 }
 
 // -----
 
 func.func @group_non_uniform_elect() -> i1 {
   // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
-  %0 = spv.GroupNonUniformElect CrossDevice : i1
+  %0 = spv.GroupNonUniformElect <CrossDevice> : i1
   return %0: i1
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.GroupNonUniformFAdd
 //===----------------------------------------------------------------------===//

mlir/test/Dialect/SPIRV/IR/structure-ops.mlir

 
 // -----
 
 spv.module Logical GLSL450 {
   spv.func @foo() -> () "None" {
     %0 = spv.Variable : !spv.ptr<i32, Function>
 
     // expected-error @+1 {{invalid enclosed op}}
-    %1 = spv.SpecConstantOperation wraps "spv.Load"(%0) {memory_access = 0 : i32} : (!spv.ptr<i32, Function>) -> i32
+    %1 = spv.SpecConstantOperation wraps "spv.Load"(%0) {memory_access = #spv.memory_access<None>} : (!spv.ptr<i32, Function>) -> i32
     spv.Return
   }
 }
 
 // -----
 
 spv.module Logical GLSL450 {
   spv.func @foo() -> () "None" {

mlir/test/Dialect/SPIRV/IR/target-and-abi.mlir

 // -----
 
 func.func @target_env_cooperative_matrix() attributes{
   // CHECK:      spv.target_env = #spv.target_env<
   // CHECK-SAME:   SPV_NV_cooperative_matrix
   // CHECK-SAME: #spv.coop_matrix_props<
   // CHECK-SAME:   m_size = 8, n_size = 8, k_size = 32,
   // CHECK-SAME:   a_type = i8, b_type = i8, c_type = i32,
-  // CHECK-SAME:   result_type = i32, scope = 3 : i32>
+  // CHECK-SAME:   result_type = i32, scope = <Subgroup>>
   // CHECK-SAME: #spv.coop_matrix_props<
   // CHECK-SAME:   m_size = 8, n_size = 8, k_size = 16,
   // CHECK-SAME:   a_type = f16, b_type = f16, c_type = f16,
-  // CHECK-SAME:   result_type = f16, scope = 3 : i32>
+  // CHECK-SAME:   result_type = f16, scope = <Subgroup>>
   spv.target_env = #spv.target_env<
   #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class,
                             SPV_NV_cooperative_matrix]>,
   #spv.resource_limits<
     cooperative_matrix_properties_nv = [#spv.coop_matrix_props<
       m_size = 8,
       n_size = 8,
       k_size = 32,
       a_type = i8,
       b_type = i8,
       c_type = i32,
       result_type = i32,
-      scope = 3 : i32
+      scope = #spv.scope<Subgroup>
     >, #spv.coop_matrix_props<
       m_size = 8,
       n_size = 8,
       k_size = 16,
       a_type = f16,
       b_type = f16,
       c_type = f16,
       result_type = f16,
-      scope = 3 : i32
+      scope = #spv.scope<Subgroup>
     >]
   >>
 } { return }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.vce

mlir/test/Dialect/SPIRV/IR/target-env.mlir

 //===----------------------------------------------------------------------===//
 // MinVersion
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @group_non_uniform_ballot_suitable_version
 func.func @group_non_uniform_ballot_suitable_version(%predicate: i1) -> vector<4xi32> attributes {
   spv.target_env = #spv.target_env<#spv.vce<v1.4, [GroupNonUniformBallot], []>, #spv.resource_limits<>>
 } {
-  // CHECK: spv.GroupNonUniformBallot Workgroup
+  // CHECK: spv.GroupNonUniformBallot <Workgroup>
   %0 = "test.convert_to_group_non_uniform_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: @group_non_uniform_ballot_unsupported_version
 func.func @group_non_uniform_ballot_unsupported_version(%predicate: i1) -> vector<4xi32> attributes {
   spv.target_env = #spv.target_env<#spv.vce<v1.1, [GroupNonUniformBallot], []>, #spv.resource_limits<>>
 } {

mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir

 // spv.GroupNonUniformBallot is available since v1.3.
 
 // CHECK: requires #spv.vce<v1.3, [GroupNonUniformBallot, Shader], []>
 spv.module Logical GLSL450 attributes {
   spv.target_env = #spv.target_env<
     #spv.vce<v1.5, [Shader, GroupNonUniformBallot], []>, #spv.resource_limits<>>
 } {
   spv.func @group_non_uniform_ballot(%predicate : i1) -> vector<4xi32> "None" {
-    %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
+    %0 = spv.GroupNonUniformBallot <Workgroup> %predicate : vector<4xi32>
     spv.ReturnValue %0: vector<4xi32>
   }
 }
 
 //===----------------------------------------------------------------------===//
 // Capability
 //===----------------------------------------------------------------------===//
 

mlir/test/Target/SPIRV/barrier-ops.mlir

 // RUN: mlir-translate -test-spirv-roundtrip %s | FileCheck %s
 
 spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   spv.func @memory_barrier_0() -> () "None" {
-    // CHECK: spv.MemoryBarrier Device, "Release|UniformMemory"
-    spv.MemoryBarrier Device, "Release|UniformMemory"
+    // CHECK: spv.MemoryBarrier <Device>, <Release|UniformMemory>
+    spv.MemoryBarrier <Device>, <Release|UniformMemory>
     spv.Return
   }
   spv.func @memory_barrier_1() -> () "None" {
-    // CHECK: spv.MemoryBarrier Subgroup, "AcquireRelease|SubgroupMemory"
-    spv.MemoryBarrier Subgroup, "AcquireRelease|SubgroupMemory"
+    // CHECK: spv.MemoryBarrier <Subgroup>, <AcquireRelease|SubgroupMemory>
+    spv.MemoryBarrier <Subgroup>, <AcquireRelease|SubgroupMemory>
     spv.Return
   }
   spv.func @control_barrier_0() -> () "None" {
-    // CHECK: spv.ControlBarrier Device, Workgroup, "Release|UniformMemory"
-    spv.ControlBarrier Device, Workgroup, "Release|UniformMemory"
+    // CHECK: spv.ControlBarrier <Device>, <Workgroup>, <Release|UniformMemory>
+    spv.ControlBarrier <Device>, <Workgroup>, <Release|UniformMemory>
     spv.Return
   }
   spv.func @control_barrier_1() -> () "None" {
-    // CHECK: spv.ControlBarrier Workgroup, Invocation, "AcquireRelease|UniformMemory"
-    spv.ControlBarrier Workgroup, Invocation, "AcquireRelease|UniformMemory"
+    // CHECK: spv.ControlBarrier <Workgroup>, <Invocation>, <AcquireRelease|UniformMemory>
+    spv.ControlBarrier <Workgroup>, <Invocation>, <AcquireRelease|UniformMemory>
     spv.Return
   }
 }

mlir/test/Target/SPIRV/group-ops.mlir

 // RUN: mlir-translate -test-spirv-roundtrip -split-input-file %s | FileCheck %s
 
 spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   // CHECK-LABEL: @subgroup_ballot
   spv.func @subgroup_ballot(%predicate: i1) -> vector<4xi32> "None" {
     // CHECK: %{{.*}} = spv.SubgroupBallotKHR %{{.*}}: vector<4xi32>
     %0 = spv.SubgroupBallotKHR %predicate: vector<4xi32>
     spv.ReturnValue %0: vector<4xi32>
   }
   // CHECK-LABEL: @group_broadcast_1
   spv.func @group_broadcast_1(%value: f32, %localid: i32 ) -> f32 "None" {
-    // CHECK: spv.GroupBroadcast Workgroup %{{.*}}, %{{.*}} : f32, i32
-    %0 = spv.GroupBroadcast Workgroup %value, %localid : f32, i32
+    // CHECK: spv.GroupBroadcast <Workgroup> %{{.*}}, %{{.*}} : f32, i32
+    %0 = spv.GroupBroadcast <Workgroup> %value, %localid : f32, i32
     spv.ReturnValue %0: f32
   }
   // CHECK-LABEL: @group_broadcast_2
   spv.func @group_broadcast_2(%value: f32, %localid: vector<3xi32> ) -> f32 "None" {
-    // CHECK: spv.GroupBroadcast Workgroup %{{.*}}, %{{.*}} : f32, vector<3xi32>
-    %0 = spv.GroupBroadcast Workgroup %value, %localid : f32, vector<3xi32>
+    // CHECK: spv.GroupBroadcast <Workgroup> %{{.*}}, %{{.*}} : f32, vector<3xi32>
+    %0 = spv.GroupBroadcast <Workgroup> %value, %localid : f32, vector<3xi32>
     spv.ReturnValue %0: f32
   }
   // CHECK-LABEL: @subgroup_block_read_intel
   spv.func @subgroup_block_read_intel(%ptr : !spv.ptr<i32, StorageBuffer>) -> i32 "None" {
     // CHECK: spv.SubgroupBlockReadINTEL %{{.*}} : i32
     %0 = spv.SubgroupBlockReadINTEL "StorageBuffer" %ptr : i32
     spv.ReturnValue %0: i32
   }

mlir/test/Target/SPIRV/non-uniform-ops.mlir

 // RUN: mlir-translate -test-spirv-roundtrip -split-input-file %s | FileCheck %s
 
 spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   // CHECK-LABEL: @group_non_uniform_ballot
   spv.func @group_non_uniform_ballot(%predicate: i1) -> vector<4xi32> "None" {
-    // CHECK: %{{.*}} = spv.GroupNonUniformBallot Workgroup %{{.*}}: vector<4xi32>
-  %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
+    // CHECK: %{{.*}} = spv.GroupNonUniformBallot <Workgroup> %{{.*}}: vector<4xi32>
+  %0 = spv.GroupNonUniformBallot <Workgroup> %predicate : vector<4xi32>
     spv.ReturnValue %0: vector<4xi32>
   }
 
   // CHECK-LABEL: @group_non_uniform_broadcast
   spv.func @group_non_uniform_broadcast(%value: f32) -> f32 "None" {
     %one = spv.Constant 1 : i32
-    // CHECK: spv.GroupNonUniformBroadcast Subgroup %{{.*}}, %{{.*}} : f32, i32
-    %0 = spv.GroupNonUniformBroadcast Subgroup %value, %one : f32, i32
+    // CHECK: spv.GroupNonUniformBroadcast <Subgroup> %{{.*}}, %{{.*}} : f32, i32
+    %0 = spv.GroupNonUniformBroadcast <Subgroup> %value, %one : f32, i32
     spv.ReturnValue %0: f32
   }
 
   // CHECK-LABEL: @group_non_uniform_elect
   spv.func @group_non_uniform_elect() -> i1 "None" {
-    // CHECK: %{{.+}} = spv.GroupNonUniformElect Workgroup : i1
-    %0 = spv.GroupNonUniformElect Workgroup : i1
+    // CHECK: %{{.+}} = spv.GroupNonUniformElect <Workgroup> : i1
+    %0 = spv.GroupNonUniformElect <Workgroup> : i1
     spv.ReturnValue %0: i1
   }
 
   // CHECK-LABEL: @group_non_uniform_fadd_reduce
   spv.func @group_non_uniform_fadd_reduce(%val: f32) -> f32 "None" {
     // CHECK: %{{.+}} = spv.GroupNonUniformFAdd "Workgroup" "Reduce" %{{.+}} : f32
     %0 = spv.GroupNonUniformFAdd "Workgroup" "Reduce" %val : f32
     spv.ReturnValue %0: f32

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

 static void emitAttributeSerialization(const Attribute &attr,
                                        ArrayRef<SMLoc> loc, StringRef tabs,
                                        StringRef opVar, StringRef operandList,
                                        StringRef attrName, raw_ostream &os) {
   os << tabs
      << formatv("if (auto attr = {0}->getAttr(\"{1}\")) {{\n", opVar, attrName);
   if (attr.getAttrDefName() == "SPV_ScopeAttr" ||
       attr.getAttrDefName() == "SPV_MemorySemanticsAttr") {
+    // These two enums are encoded as <id> to constant values in SPIR-V blob,
+    // but we directly use the constant value as attribute in SPIR-V dialect. So
+    // need to handle them separately from normal enum attributes.
+    EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("  {0}.push_back(prepareConstantInt({1}.getLoc(), "
-                  "attr.cast<IntegerAttr>()));\n",
-                  operandList, opVar);
+                  "Builder({1}).getI32IntegerAttr(static_cast<uint32_t>("
+                  "attr.cast<{2}::{3}Attr>().getValue()))));\n",
+                  operandList, opVar, baseEnum.getCppNamespace(),
+                  baseEnum.getEnumClassName());
+  } else if (attr.isSubClassOf("SPV_BitEnumAttr") ||
+             attr.isSubClassOf("SPV_I32EnumAttr")) {
+    EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
+    os << tabs
+       << formatv("  {0}.push_back(static_cast<uint32_t>("
+                  "attr.cast<{1}::{2}Attr>().getValue()));\n",
+                  operandList, baseEnum.getCppNamespace(),
+                  baseEnum.getEnumClassName());
   } else if (attr.getAttrDefName() == "I32ArrayAttr") {
     // Serialize all the elements of the array
     os << tabs << "  for (auto attrElem : attr.cast<ArrayAttr>()) {\n";
     os << tabs
        << formatv("    {0}.push_back(static_cast<uint32_t>("
                   "attrElem.cast<IntegerAttr>().getValue().getZExtValue()));\n",
                   operandList);
     os << tabs << "  }\n";
-  } else if (attr.isEnumAttr() || attr.getAttrDefName() == "I32Attr") {
+  } else if (attr.getAttrDefName() == "I32Attr") {
     os << tabs
        << formatv("  {0}.push_back(static_cast<uint32_t>("
                   "attr.cast<IntegerAttr>().getValue().getZExtValue()));\n",
                   operandList);
   } else if (attr.isEnumAttr() || attr.getAttrDefName() == "TypeAttr") {
     os << tabs
        << formatv("  {0}.push_back(static_cast<uint32_t>("
                   "getTypeID(attr.cast<TypeAttr>().getValue())));\n",

 /// position `wordIndex` and adds the deserialized attribute into `attrList`.
 static void emitAttributeDeserialization(const Attribute &attr,
                                          ArrayRef<SMLoc> loc, StringRef tabs,
                                          StringRef attrList, StringRef attrName,
                                          StringRef words, StringRef wordIndex,
                                          raw_ostream &os) {
   if (attr.getAttrDefName() == "SPV_ScopeAttr" ||
       attr.getAttrDefName() == "SPV_MemorySemanticsAttr") {
+    // These two enums are encoded as <id> to constant values in SPIR-V blob,
+    // but we directly use the constant value as attribute in SPIR-V dialect. So
+    // need to handle them separately from normal enum attributes.
+    EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
-                  "getConstantInt({2}[{3}++])));\n",
-                  attrList, attrName, words, wordIndex);
+                  "opBuilder.getAttr<{2}::{3}Attr>(static_cast<{2}::{3}>("
+                  "getConstantInt({4}[{5}++]).getValue().getZExtValue()))));\n",
+                  attrList, attrName, baseEnum.getCppNamespace(),
+                  baseEnum.getEnumClassName(), words, wordIndex);
+  } else if (attr.isSubClassOf("SPV_BitEnumAttr") ||
+             attr.isSubClassOf("SPV_I32EnumAttr")) {
+    EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
+    os << tabs
+       << formatv("  {0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
+                  "opBuilder.getAttr<{2}::{3}Attr>("
+                  "static_cast<{2}::{3}>({4}[{5}++]))));\n",
+                  attrList, attrName, baseEnum.getCppNamespace(),
+                  baseEnum.getEnumClassName(), words, wordIndex);
   } else if (attr.getAttrDefName() == "I32ArrayAttr") {
     os << tabs << "SmallVector<Attribute, 4> attrListElems;\n";
     os << tabs << formatv("while ({0} < {1}.size()) {{\n", wordIndex, words);
     os << tabs
        << formatv(
               "  "
               "attrListElems.push_back(opBuilder.getI32IntegerAttr({0}[{1}++]))"
               ";\n",
               words, wordIndex);
     os << tabs << "}\n";
     os << tabs
        << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
                   "opBuilder.getArrayAttr(attrListElems)));\n",
                   attrList, attrName);
-  } else if (attr.isEnumAttr() || attr.getAttrDefName() == "I32Attr") {
+  } else if (attr.getAttrDefName() == "I32Attr") {
     os << tabs
        << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
                   "opBuilder.getI32IntegerAttr({2}[{3}++])));\n",
                   attrList, attrName, words, wordIndex);
   } else if (attr.isEnumAttr() || attr.getAttrDefName() == "TypeAttr") {
     os << tabs
        << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
                   "TypeAttr::get(getType({2}[{3}++]))));\n",
static void emitAvailabilityImpl(const Operator &srcOp, raw_ostream &os) {
   // First collect all availability classes this op should implement.
   // All availability instances keep information for the generated interface and
   // the instance's specific requirement. Here we remember a random instance so
   // we can get the information regarding the generated interface.
   llvm::StringMap<Availability> availClasses;
   for (const Availability &avail : opAvailabilities)
     availClasses.try_emplace(avail.getClass(), avail);
   for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
-    const auto *enumAttr = llvm::dyn_cast<EnumAttr>(&namedAttr.attr);
-    if (!enumAttr)
+    if (!namedAttr.attr.isSubClassOf("SPV_BitEnumAttr") &&
+        !namedAttr.attr.isSubClassOf("SPV_I32EnumAttr"))
       continue;
+    EnumAttr enumAttr(namedAttr.attr.getDef().getValueAsDef("enum"));
 
-    for (const EnumAttrCase &enumerant : enumAttr->getAllCases())
+    for (const EnumAttrCase &enumerant : enumAttr.getAllCases())
       for (const Availability &caseAvail :
            getAvailabilities(enumerant.getDef()))
         availClasses.try_emplace(caseAvail.getClass(), caseAvail);
   }
 
   // Then generate implementation for each availability class.
   for (const auto &availClass : availClasses) {
     StringRef availClassName = availClass.getKey();
for (const Availability &avail : opAvailabilities)
            << std::string(
                   tgfmt(avail.getMergeActionCode(),
                         &fctx.addSubst("instance", avail.getMergeInstance())))
            << ";\n  }\n";
       }
 
     // Update with enum attributes' specific availability spec.
     for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
-      const auto *enumAttr = llvm::dyn_cast<EnumAttr>(&namedAttr.attr);
-      if (!enumAttr)
+      if (!namedAttr.attr.isSubClassOf("SPV_BitEnumAttr") &&
+          !namedAttr.attr.isSubClassOf("SPV_I32EnumAttr"))
         continue;
+      EnumAttr enumAttr(namedAttr.attr.getDef().getValueAsDef("enum"));
 
       // (enumerant, availability specification) pairs for this availability
       // class.
       SmallVector<std::pair<EnumAttrCase, Availability>, 1> caseSpecs;
 
       // Collect all cases' availability specs.
-      for (const EnumAttrCase &enumerant : enumAttr->getAllCases())
+      for (const EnumAttrCase &enumerant : enumAttr.getAllCases())
         for (const Availability &caseAvail :
              getAvailabilities(enumerant.getDef()))
           if (availClassName == caseAvail.getClass())
             caseSpecs.push_back({enumerant, caseAvail});
 
       // If this attribute kind does not have any availability spec from any of
       // its cases, no more work to do.
       if (caseSpecs.empty())
         continue;
 
-      if (enumAttr->isBitEnum()) {
+      if (enumAttr.isBitEnum()) {
         // For BitEnumAttr, we need to iterate over each bit to query its
         // availability spec.
         os << formatv("  for (unsigned i = 0; "
                       "i < std::numeric_limits<{0}>::digits; ++i) {{\n",
-                      enumAttr->getUnderlyingType());
+                      enumAttr.getUnderlyingType());
         os << formatv("    {0}::{1} tblgen_attrVal = this->{2}() & "
                       "static_cast<{0}::{1}>(1 << i);\n",
-                      enumAttr->getCppNamespace(), enumAttr->getEnumClassName(),
+                      enumAttr.getCppNamespace(), enumAttr.getEnumClassName(),
                       namedAttr.name);
         os << formatv(
             "    if (static_cast<{0}>(tblgen_attrVal) == 0) continue;\n",
-            enumAttr->getUnderlyingType());
+            enumAttr.getUnderlyingType());
       } else {
         // For IntEnumAttr, we just need to query the value as a whole.
         os << "  {\n";
         os << formatv("    auto tblgen_attrVal = this->{0}();\n",
                       namedAttr.name);
       }
       os << formatv("    auto tblgen_instance = {0}::{1}(tblgen_attrVal);\n",
-                    enumAttr->getCppNamespace(), avail.getQueryFnName());
+                    enumAttr.getCppNamespace(), avail.getQueryFnName());
       os << "    if (tblgen_instance) "
          // TODO` here once ODS supports
          // dialect-specific contents so that we can use not implementing the
          // availability interface as indication of no requirements.
          << std::string(tgfmt(caseSpecs.front().second.getMergeActionCode(),
                               &fctx.addSubst("instance", "*tblgen_instance")))
          << ";\n";
       os << "  }\n";

 //===----------------------------------------------------------------------===//
 // SPIR-V Capability Implication AutoGen
 //===----------------------------------------------------------------------===//
 
 static bool emitCapabilityImplication(const RecordKeeper &recordKeeper,
                                       raw_ostream &os) {
   llvm::emitSourceFileHeader("SPIR-V Capability Implication", os);
 
-  EnumAttr enumAttr(recordKeeper.getDef("SPV_CapabilityAttr"));
+  EnumAttr enumAttr(
+      recordKeeper.getDef("SPV_CapabilityAttr")->getValueAsDef("enum"));
 
   os << "ArrayRef<spirv::Capability> "
         "spirv::getDirectImpliedCapabilities(spirv::Capability cap) {\n"
      << "  switch (cap) {\n"
      << "  default: return {};\n";
   for (const EnumAttrCase &enumerant : enumAttr.getAllCases()) {
     const Record &def = enumerant.getDef();
     if (!def.getValue("implies"))

mlir/unittests/Dialect/SPIRV/SerializationTest.cpp

 //===- SerializationTest.cpp - SPIR-V Serialization Tests -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains corner case tests for the SPIR-V serializer that are not
 // covered by normal serialization and deserialization roundtripping.
 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Target/SPIRV/Serialization.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVAttributes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVEnums.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/Location.h"
 #include "mlir/IR/MLIRContext.h"
 #include "mlir/Target/SPIRV/SPIRVBinaryUtils.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
protected:
   }
 
   /// Initializes an empty SPIR-V module op.
   void initModuleOp() {
     OpBuilder builder(&context);
     OperationState state(UnknownLoc::get(&context),
                          spirv::ModuleOp::getOperationName());
     state.addAttribute("addressing_model",
-                       builder.getI32IntegerAttr(static_cast<uint32_t>(
-                           spirv::AddressingModel::Logical)));
-    state.addAttribute("memory_model",
-                       builder.getI32IntegerAttr(
-                           static_cast<uint32_t>(spirv::MemoryModel::GLSL450)));
+                       builder.getAttr<spirv::AddressingModelAttr>(
+                           spirv::AddressingModel::Logical));
+    state.addAttribute("memory_model", builder.getAttr<spirv::MemoryModelAttr>(
+                                           spirv::MemoryModel::GLSL450));
     state.addAttribute("vce_triple",
                        spirv::VerCapExtAttr::get(
                            spirv::Version::V_1_0, ArrayRef<spirv::Capability>(),
                            ArrayRef<spirv::Extension>(), &context));
     spirv::ModuleOp::build(builder, state);
     module = cast<spirv::ModuleOp>(Operation::create(state));
   }
 

mlir/utils/spirv/gen_spirv_dialect.py

def gen_operand_kind_enum_attr(operand_kind, capability_mapping):
   case_names = split_list_into_sublists(case_names)
   case_names = ['{:6}'.format('') + ', '.join(sublist)
                 for sublist in case_names]
   case_names = ',\n'.join(case_names)
 
   # Generate the enum attribute definition
   kind_category = 'Bit' if is_bit_enum else 'I32'
   enum_attr = '''def SPV_{name}Attr :
-    SPV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", [
+    SPV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", "{snake_name}", [
 {cases}
     ]>;'''.format(
-          name=kind_name, category=kind_category, cases=case_names)
+          name=kind_name,
+          snake_name=snake_casify(kind_name),
+          category=kind_category,
+          cases=case_names)
   return kind_name, case_defs + '\n\n' + enum_attr
 
 
 def gen_opcode(instructions):
   """ Generates the TableGen definition to map opname to opcode
 
   Returns:
     - A string containing the TableGen SPV_OpCode definition
opcode_list = [
       decl_fmt_str.format(name=inst['opname']) for inst in instructions
   ]
   opcode_list = split_list_into_sublists(opcode_list)
   opcode_list = [
       '{:6}'.format('') + ', '.join(sublist) for sublist in opcode_list
   ]
   opcode_list = ',\n'.join(opcode_list)
   enum_attr = 'def SPV_OpcodeAttr :\n'\
-              '    SPV_I32EnumAttr<"{name}", "valid SPIR-V instructions", [\n'\
+              '    SPV_I32EnumAttr<"{name}", "valid SPIR-V instructions", '\
+              '"opcode", [\n'\
               '{lst}\n'\
               '    ]>;'.format(name='Opcode', lst=opcode_list)
   return opcode_str + '\n\n' + enum_attr
 
 def map_cap_to_opnames(instructions):
   """Maps capabilities to instructions enabled by those capabilities
 
   Arguments:
content = content[0] + AUTOGEN_ENUM_SECTION_MARKER + '\n\n' + \
       + content[2];
 
   with open(path, 'w') as f:
     f.write(content)
 
 
 def snake_casify(name):
   """Turns the given name to follow snake_case convention."""
-  name = re.sub('\W+', '', name).split()
-  name = [s.lower() for s in name]
-  return '_'.join(name)
+  return re.sub(r'(?<!^)(?=[A-Z])', '_', name).lower()
 
 
 def map_spec_operand_to_ods_argument(operand):
   """Maps an operand in SPIR-V JSON spec to an op argument in ODS.
 
   Arguments:
     - A dict containing the operand's kind, quantifier, and name