[mlir][spirv] Refresh base definitions to latest spec (v1.6)

[antiagainst]

Summary

This commit updates all SPIR-V enum definitions to match the latest
specification (v1.6 revision 2). Along the way, fixed some issues
in gen_spirv_dialect.py and added a new script for refreshing
all op definitions for such cases.

[antiagainst]

Rebase

[kuhar]

mlir/utils/spirv/refresh_inst.sh

16

Don't we need to quote current_dir in case there are spaces? I'm used to quoting all paths: https://google.github.io/styleguide/shellguide.html#quoting

27

Same here

[antiagainst]

mlir/utils/spirv/refresh_inst.sh

16

Good point. Done.

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td

let description = [{
     ```mlir
     %0 = spv.AtomicFAddEXT "Device" "None" %pointer, %value :
                            !spv.ptr<f32, StorageBuffer>
     ```mlir
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_EXT_shader_atomic_float_add]>,
     Capability<[SPV_C_AtomicFloat16AddEXT, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$pointer,
     SPV_ScopeAttr:$memory_scope,
     SPV_MemorySemanticsAttr:$semantics,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

 //===----------------------------------------------------------------------===//
 
 def SPV_V_1_0 : I32EnumAttrCase<"V_1_0", 0, "v1.0">;
 def SPV_V_1_1 : I32EnumAttrCase<"V_1_1", 1, "v1.1">;
 def SPV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">;
 def SPV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">;
 def SPV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">;
 def SPV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">;
+def SPV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">;
 
 def SPV_VersionAttr : SPV_I32EnumAttr<"Version", "valid SPIR-V version", [
-    SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5]>;
+    SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5,
+    SPV_V_1_6]>;
 
 class MinVersion<I32EnumAttrCase min> : MinVersionBase<
     "QueryMinVersionInterface", SPV_VersionAttr, min> {
   let cppNamespace = "::mlir::spirv";
   let interfaceDescription = [{
     Querying interface for minimal required SPIR-V version.
 
     This interface provides a `getMinVersion()` method to query the minimal

 def SPV_KHR_integer_dot_product              : I32EnumAttrCase<"SPV_KHR_integer_dot_product", 17>;
 def SPV_KHR_bit_instructions                 : I32EnumAttrCase<"SPV_KHR_bit_instructions", 18>;
 def SPV_KHR_fragment_shading_rate            : I32EnumAttrCase<"SPV_KHR_fragment_shading_rate", 19>;
 def SPV_KHR_workgroup_memory_explicit_layout : I32EnumAttrCase<"SPV_KHR_workgroup_memory_explicit_layout", 20>;
 def SPV_KHR_ray_query                        : I32EnumAttrCase<"SPV_KHR_ray_query", 21>;
 def SPV_KHR_ray_tracing                      : I32EnumAttrCase<"SPV_KHR_ray_tracing", 22>;
 def SPV_KHR_subgroup_uniform_control_flow    : I32EnumAttrCase<"SPV_KHR_subgroup_uniform_control_flow", 23>;
 def SPV_KHR_linkonce_odr                     : I32EnumAttrCase<"SPV_KHR_linkonce_odr", 24>;
+def SPV_KHR_fragment_shader_barycentric      : I32EnumAttrCase<"SPV_KHR_fragment_shader_barycentric", 25>;
+def SPV_KHR_ray_cull_mask                    : I32EnumAttrCase<"SPV_KHR_ray_cull_mask", 26>;
+def SPV_KHR_uniform_group_instructions       : I32EnumAttrCase<"SPV_KHR_uniform_group_instructions", 27>;
+def SPV_KHR_subgroup_rotate                  : I32EnumAttrCase<"SPV_KHR_subgroup_rotate", 28>;
+
+def SPV_EXT_demote_to_helper_invocation  : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 1000>;
+def SPV_EXT_descriptor_indexing          : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 1001>;
+def SPV_EXT_fragment_fully_covered       : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 1002>;
+def SPV_EXT_fragment_invocation_density  : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 1003>;
+def SPV_EXT_fragment_shader_interlock    : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 1004>;
+def SPV_EXT_physical_storage_buffer      : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 1005>;
+def SPV_EXT_shader_stencil_export        : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 1006>;
+def SPV_EXT_shader_viewport_index_layer  : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 1007>;
+def SPV_EXT_shader_atomic_float_add      : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 1008>;
+def SPV_EXT_shader_atomic_float_min_max  : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 1009>;
+def SPV_EXT_shader_image_int64           : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 1010>;
+def SPV_EXT_shader_atomic_float16_add    : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 1011>;
+
+def SPV_AMD_gpu_shader_half_float_fetch          : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 2000>;
+def SPV_AMD_shader_ballot                        : I32EnumAttrCase<"SPV_AMD_shader_ballot", 2001>;
+def SPV_AMD_shader_explicit_vertex_parameter     : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 2002>;
+def SPV_AMD_shader_fragment_mask                 : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 2003>;
+def SPV_AMD_shader_image_load_store_lod          : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 2004>;
+def SPV_AMD_texture_gather_bias_lod              : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 2005>;
+def SPV_AMD_shader_early_and_late_fragment_tests : I32EnumAttrCase<"SPV_AMD_shader_early_and_late_fragment_tests", 2006>;
+
+def SPV_GOOGLE_decorate_string           : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 3000>;
+def SPV_GOOGLE_hlsl_functionality1       : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 3001>;
+def SPV_GOOGLE_user_type                 : I32EnumAttrCase<"SPV_GOOGLE_user_type", 3002>;
+
+def SPV_INTEL_device_side_avc_motion_estimation  : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 4000>;
+def SPV_INTEL_media_block_io                     : I32EnumAttrCase<"SPV_INTEL_media_block_io", 4001>;
+def SPV_INTEL_shader_integer_functions2          : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 4002>;
+def SPV_INTEL_subgroups                          : I32EnumAttrCase<"SPV_INTEL_subgroups", 4003>;
+def SPV_INTEL_float_controls2                    : I32EnumAttrCase<"SPV_INTEL_float_controls2", 4004>;
+def SPV_INTEL_function_pointers                  : I32EnumAttrCase<"SPV_INTEL_function_pointers", 4005>;
+def SPV_INTEL_inline_assembly                    : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 4006>;
+def SPV_INTEL_vector_compute                     : I32EnumAttrCase<"SPV_INTEL_vector_compute", 4007>;
+def SPV_INTEL_variable_length_array              : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 4008>;
+def SPV_INTEL_fpga_memory_attributes             : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 4009>;
+def SPV_INTEL_arbitrary_precision_integers       : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 4010>;
+def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 4011>;
+def SPV_INTEL_unstructured_loop_controls         : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 4012>;
+def SPV_INTEL_fpga_loop_controls                 : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 4013>;
+def SPV_INTEL_kernel_attributes                  : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 4014>;
+def SPV_INTEL_fpga_memory_accesses               : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 4015>;
+def SPV_INTEL_fpga_cluster_attributes            : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 4016>;
+def SPV_INTEL_loop_fuse                          : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 4017>;
+def SPV_INTEL_fpga_buffer_location               : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 4018>;
+def SPV_INTEL_arbitrary_precision_fixed_point    : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 4019>;
+def SPV_INTEL_usm_storage_classes                : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 4020>;
+def SPV_INTEL_io_pipes                           : I32EnumAttrCase<"SPV_INTEL_io_pipes", 4021>;
+def SPV_INTEL_blocking_pipes                     : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 4022>;
+def SPV_INTEL_fpga_reg                           : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>;
+def SPV_INTEL_long_constant_composite            : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>;
+def SPV_INTEL_optnone                            : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>;
+def SPV_INTEL_debug_module                       : I32EnumAttrCase<"SPV_INTEL_debug_module", 4026>;
+def SPV_INTEL_fp_fast_math_mode                  : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 4027>;
+def SPV_INTEL_memory_access_aliasing             : I32EnumAttrCase<"SPV_INTEL_memory_access_aliasing", 4028>;
+def SPV_INTEL_split_barrier                      : I32EnumAttrCase<"SPV_INTEL_split_barrier", 4029>;
+
+def SPV_NV_compute_shader_derivatives    : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 5000>;
+def SPV_NV_cooperative_matrix            : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 5001>;
+def SPV_NV_fragment_shader_barycentric   : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 5002>;
+def SPV_NV_geometry_shader_passthrough   : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 5003>;
+def SPV_NV_mesh_shader                   : I32EnumAttrCase<"SPV_NV_mesh_shader", 5004>;
+def SPV_NV_ray_tracing                   : I32EnumAttrCase<"SPV_NV_ray_tracing", 5005>;
+def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 5006>;
+def SPV_NV_shader_image_footprint        : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 5007>;
+def SPV_NV_shader_sm_builtins            : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 5008>;
+def SPV_NV_shader_subgroup_partitioned   : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 5009>;
+def SPV_NV_shading_rate                  : I32EnumAttrCase<"SPV_NV_shading_rate", 5010>;
+def SPV_NV_stereo_view_rendering         : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 5011>;
+def SPV_NV_viewport_array2               : I32EnumAttrCase<"SPV_NV_viewport_array2", 5012>;
+def SPV_NV_bindless_texture              : I32EnumAttrCase<"SPV_NV_bindless_texture", 5013>;
+def SPV_NV_ray_tracing_motion_blur       : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 5014>;
 
-def SPV_EXT_demote_to_helper_invocation  : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 25>;
-def SPV_EXT_descriptor_indexing          : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 26>;
-def SPV_EXT_fragment_fully_covered       : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 27>;
-def SPV_EXT_fragment_invocation_density  : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 28>;
-def SPV_EXT_fragment_shader_interlock    : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 29>;
-def SPV_EXT_physical_storage_buffer      : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 30>;
-def SPV_EXT_shader_stencil_export        : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 31>;
-def SPV_EXT_shader_viewport_index_layer  : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 32>;
-def SPV_EXT_shader_atomic_float_add      : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 33>;
-def SPV_EXT_shader_atomic_float_min_max  : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 34>;
-def SPV_EXT_shader_image_int64           : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 35>;
-def SPV_EXT_shader_atomic_float16_add    : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 36>;
-
-def SPV_AMD_gpu_shader_half_float_fetch      : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 37>;
-def SPV_AMD_shader_ballot                    : I32EnumAttrCase<"SPV_AMD_shader_ballot", 38>;
-def SPV_AMD_shader_explicit_vertex_parameter : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 39>;
-def SPV_AMD_shader_fragment_mask             : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 40>;
-def SPV_AMD_shader_image_load_store_lod      : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 41>;
-def SPV_AMD_texture_gather_bias_lod          : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 42>;
-
-def SPV_GOOGLE_decorate_string           : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 43>;
-def SPV_GOOGLE_hlsl_functionality1       : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 44>;
-def SPV_GOOGLE_user_type                 : I32EnumAttrCase<"SPV_GOOGLE_user_type", 45>;
-
-def SPV_INTEL_device_side_avc_motion_estimation  : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 46>;
-def SPV_INTEL_media_block_io                     : I32EnumAttrCase<"SPV_INTEL_media_block_io", 47>;
-def SPV_INTEL_shader_integer_functions2          : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 48>;
-def SPV_INTEL_subgroups                          : I32EnumAttrCase<"SPV_INTEL_subgroups", 49>;
-def SPV_INTEL_float_controls2                    : I32EnumAttrCase<"SPV_INTEL_float_controls2", 50>;
-def SPV_INTEL_function_pointers                  : I32EnumAttrCase<"SPV_INTEL_function_pointers", 51>;
-def SPV_INTEL_inline_assembly                    : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 52>;
-def SPV_INTEL_vector_compute                     : I32EnumAttrCase<"SPV_INTEL_vector_compute", 53>;
-def SPV_INTEL_variable_length_array              : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 54>;
-def SPV_INTEL_fpga_memory_attributes             : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 55>;
-def SPV_INTEL_arbitrary_precision_integers       : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 56>;
-def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 57>;
-def SPV_INTEL_unstructured_loop_controls         : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 58>;
-def SPV_INTEL_fpga_loop_controls                 : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 59>;
-def SPV_INTEL_kernel_attributes                  : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 60>;
-def SPV_INTEL_fpga_memory_accesses               : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 61>;
-def SPV_INTEL_fpga_cluster_attributes            : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 62>;
-def SPV_INTEL_loop_fuse                          : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 63>;
-def SPV_INTEL_fpga_buffer_location               : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 64>;
-def SPV_INTEL_arbitrary_precision_fixed_point    : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 65>;
-def SPV_INTEL_usm_storage_classes                : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 66>;
-def SPV_INTEL_io_pipes                           : I32EnumAttrCase<"SPV_INTEL_io_pipes", 67>;
-def SPV_INTEL_blocking_pipes                     : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 68>;
-def SPV_INTEL_fpga_reg                           : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 69>;
-def SPV_INTEL_long_constant_composite            : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 70>;
-def SPV_INTEL_optnone                            : I32EnumAttrCase<"SPV_INTEL_optnone", 71>;
-def SPV_INTEL_debug_module                       : I32EnumAttrCase<"SPV_INTEL_debug_module", 72>;
-def SPV_INTEL_fp_fast_math_mode                  : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 73>;
-
-def SPV_NV_compute_shader_derivatives    : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 74>;
-def SPV_NV_cooperative_matrix            : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 75>;
-def SPV_NV_fragment_shader_barycentric   : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 76>;
-def SPV_NV_geometry_shader_passthrough   : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 77>;
-def SPV_NV_mesh_shader                   : I32EnumAttrCase<"SPV_NV_mesh_shader", 78>;
-def SPV_NV_ray_tracing                   : I32EnumAttrCase<"SPV_NV_ray_tracing", 79>;
-def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 80>;
-def SPV_NV_shader_image_footprint        : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 81>;
-def SPV_NV_shader_sm_builtins            : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 82>;
-def SPV_NV_shader_subgroup_partitioned   : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 83>;
-def SPV_NV_shading_rate                  : I32EnumAttrCase<"SPV_NV_shading_rate", 84>;
-def SPV_NV_stereo_view_rendering         : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 85>;
-def SPV_NV_viewport_array2               : I32EnumAttrCase<"SPV_NV_viewport_array2", 86>;
-def SPV_NV_bindless_texture              : I32EnumAttrCase<"SPV_NV_bindless_texture", 87>;
-def SPV_NV_ray_tracing_motion_blur       : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 88>;
-
-def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 89>;
+def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 5015>;
 
 def SPV_ExtensionAttr :
     SPV_EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
       SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_device_group,
       SPV_KHR_float_controls, SPV_KHR_physical_storage_buffer, SPV_KHR_multiview,
       SPV_KHR_no_integer_wrap_decoration, SPV_KHR_post_depth_coverage,
       SPV_KHR_shader_atomic_counter_ops, SPV_KHR_shader_ballot,
       SPV_KHR_shader_clock, SPV_KHR_shader_draw_parameters,
       SPV_KHR_storage_buffer_storage_class, SPV_KHR_subgroup_vote,
       SPV_KHR_variable_pointers, SPV_KHR_vulkan_memory_model, SPV_KHR_expect_assume,
       SPV_KHR_integer_dot_product, SPV_KHR_bit_instructions, SPV_KHR_fragment_shading_rate,
       SPV_KHR_workgroup_memory_explicit_layout, SPV_KHR_ray_query,
       SPV_KHR_ray_tracing, SPV_KHR_subgroup_uniform_control_flow, SPV_KHR_linkonce_odr,
+      SPV_KHR_fragment_shader_barycentric, SPV_KHR_ray_cull_mask,
+      SPV_KHR_uniform_group_instructions, SPV_KHR_subgroup_rotate,
       SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_indexing,
       SPV_EXT_fragment_fully_covered, SPV_EXT_fragment_invocation_density,
       SPV_EXT_fragment_shader_interlock, SPV_EXT_physical_storage_buffer,
       SPV_EXT_shader_stencil_export, SPV_EXT_shader_viewport_index_layer,
       SPV_EXT_shader_atomic_float_add, SPV_EXT_shader_atomic_float_min_max,
       SPV_EXT_shader_image_int64, SPV_EXT_shader_atomic_float16_add,
       SPV_AMD_gpu_shader_half_float_fetch, SPV_AMD_shader_ballot,
       SPV_AMD_shader_explicit_vertex_parameter, SPV_AMD_shader_fragment_mask,
       SPV_AMD_shader_image_load_store_lod, SPV_AMD_texture_gather_bias_lod,
+      SPV_AMD_shader_early_and_late_fragment_tests,
       SPV_GOOGLE_decorate_string, SPV_GOOGLE_hlsl_functionality1, SPV_GOOGLE_user_type,
       SPV_INTEL_device_side_avc_motion_estimation, SPV_INTEL_media_block_io,
       SPV_INTEL_shader_integer_functions2, SPV_INTEL_subgroups, SPV_INTEL_vector_compute,
       SPV_INTEL_float_controls2, SPV_INTEL_function_pointers, SPV_INTEL_inline_assembly,
       SPV_INTEL_variable_length_array, SPV_INTEL_fpga_memory_attributes,
       SPV_INTEL_unstructured_loop_controls, SPV_INTEL_fpga_loop_controls,
       SPV_INTEL_arbitrary_precision_integers, SPV_INTEL_arbitrary_precision_floating_point,
       SPV_INTEL_kernel_attributes, SPV_INTEL_fpga_memory_accesses,
       SPV_INTEL_fpga_cluster_attributes, SPV_INTEL_loop_fuse,
       SPV_INTEL_fpga_buffer_location, SPV_INTEL_arbitrary_precision_fixed_point,
       SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes,
       SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone,
       SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode,
+      SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier,
       SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix,
       SPV_NV_fragment_shader_barycentric, SPV_NV_geometry_shader_passthrough,
       SPV_NV_mesh_shader, SPV_NV_ray_tracing, SPV_NV_sample_mask_override_coverage,
       SPV_NV_shader_image_footprint, SPV_NV_shader_sm_builtins,
       SPV_NV_shader_subgroup_partitioned, SPV_NV_shading_rate,
       SPV_NV_stereo_view_rendering, SPV_NV_viewport_array2, SPV_NV_bindless_texture,
       SPV_NV_ray_tracing_motion_blur, SPV_NVX_multiview_per_view_attributes
     ]>;
list<Availability> availability = [
     MinVersion<SPV_V_1_5>
   ];
 }
 def SPV_C_ShaderViewportIndex                         : I32EnumAttrCase<"ShaderViewportIndex", 70> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>
   ];
 }
+def SPV_C_UniformDecoration                           : I32EnumAttrCase<"UniformDecoration", 71> {
+  list<Availability> availability = [
+    MinVersion<SPV_V_1_6>
+  ];
+}
 def SPV_C_SubgroupBallotKHR                           : I32EnumAttrCase<"SubgroupBallotKHR", 4423> {
   list<Availability> availability = [
     Extension<[SPV_KHR_shader_ballot]>
   ];
 }
 def SPV_C_SubgroupVoteKHR                             : I32EnumAttrCase<"SubgroupVoteKHR", 4431> {
   list<Availability> availability = [
     Extension<[SPV_KHR_subgroup_vote]>
list<Availability> availability = [
     Extension<[SPV_KHR_float_controls]>
   ];
 }
 def SPV_C_ImageFootprintNV                            : I32EnumAttrCase<"ImageFootprintNV", 5282> {
   list<Availability> availability = [
     Extension<[SPV_NV_shader_image_footprint]>
   ];
 }
-def SPV_C_FragmentBarycentricNV                       : I32EnumAttrCase<"FragmentBarycentricNV", 5284> {
+def SPV_C_FragmentBarycentricKHR                      : I32EnumAttrCase<"FragmentBarycentricKHR", 5284> {
   list<Availability> availability = [
-    Extension<[SPV_NV_fragment_shader_barycentric]>
+    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>
   ];
 }
 def SPV_C_ComputeDerivativeGroupQuadsNV               : I32EnumAttrCase<"ComputeDerivativeGroupQuadsNV", 5288> {
   list<Availability> availability = [
     Extension<[SPV_NV_compute_shader_derivatives]>
   ];
 }
 def SPV_C_GroupNonUniformPartitionedNV                : I32EnumAttrCase<"GroupNonUniformPartitionedNV", 5297> {
list<Availability> availability = [
     Extension<[SPV_INTEL_fpga_cluster_attributes]>
   ];
 }
 def SPV_C_LoopFuseINTEL                               : I32EnumAttrCase<"LoopFuseINTEL", 5906> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_loop_fuse]>
   ];
 }
+def SPV_C_MemoryAccessAliasingINTEL                   : I32EnumAttrCase<"MemoryAccessAliasingINTEL", 5910> {
+  list<Availability> availability = [
+    Extension<[SPV_INTEL_memory_access_aliasing]>
+  ];
+}
 def SPV_C_FPGABufferLocationINTEL                     : I32EnumAttrCase<"FPGABufferLocationINTEL", 5920> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_fpga_buffer_location]>
   ];
 }
 def SPV_C_ArbitraryPrecisionFixedPointINTEL           : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_arbitrary_precision_fixed_point]>
list<Availability> availability = [
     Extension<[SPV_INTEL_blocking_pipes]>
   ];
 }
 def SPV_C_FPGARegINTEL                                : I32EnumAttrCase<"FPGARegINTEL", 5948> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_fpga_reg]>
   ];
 }
-def SPV_C_DotProductInputAllKHR                       : I32EnumAttrCase<"DotProductInputAllKHR", 6016> {
+def SPV_C_DotProductInputAll                          : I32EnumAttrCase<"DotProductInputAll", 6016> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_integer_dot_product]>
+    MinVersion<SPV_V_1_6>
   ];
 }
-def SPV_C_DotProductInput4x8BitPackedKHR              : I32EnumAttrCase<"DotProductInput4x8BitPackedKHR", 6018> {
+def SPV_C_DotProductInput4x8BitPacked                 : I32EnumAttrCase<"DotProductInput4x8BitPacked", 6018> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_integer_dot_product]>
+    MinVersion<SPV_V_1_6>
   ];
 }
-def SPV_C_DotProductKHR                               : I32EnumAttrCase<"DotProductKHR", 6019> {
+def SPV_C_DotProduct                                  : I32EnumAttrCase<"DotProduct", 6019> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_integer_dot_product]>
+    MinVersion<SPV_V_1_6>
+  ];
+}
+def SPV_C_RayCullMaskKHR                              : I32EnumAttrCase<"RayCullMaskKHR", 6020> {
+  list<Availability> availability = [
+    Extension<[SPV_KHR_ray_cull_mask]>
   ];
 }
 def SPV_C_BitInstructions                             : I32EnumAttrCase<"BitInstructions", 6025> {
   list<Availability> availability = [
     Extension<[SPV_KHR_bit_instructions]>
   ];
 }
+def SPV_C_AtomicFloat32AddEXT                         : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
+  list<Availability> availability = [
+    Extension<[SPV_EXT_shader_atomic_float_add]>
+  ];
+}
+def SPV_C_AtomicFloat64AddEXT                         : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
+  list<Availability> availability = [
+    Extension<[SPV_EXT_shader_atomic_float_add]>
+  ];
+}
 def SPV_C_LongConstantCompositeINTEL                  : I32EnumAttrCase<"LongConstantCompositeINTEL", 6089> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_long_constant_composite]>
   ];
 }
 def SPV_C_OptNoneINTEL                                : I32EnumAttrCase<"OptNoneINTEL", 6094> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_optnone]>
   ];
 }
+def SPV_C_AtomicFloat16AddEXT                         : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
+  list<Availability> availability = [
+    Extension<[SPV_EXT_shader_atomic_float16_add]>
+  ];
+}
 def SPV_C_DebugInfoModuleINTEL                        : I32EnumAttrCase<"DebugInfoModuleINTEL", 6114> {
   list<Availability> availability = [
     Extension<[SPV_INTEL_debug_module]>
   ];
 }
+def SPV_C_SplitBarrierINTEL                           : I32EnumAttrCase<"SplitBarrierINTEL", 6141> {
+  list<Availability> availability = [
+    Extension<[SPV_INTEL_split_barrier]>
+  ];
+}
+def SPV_C_GroupUniformArithmeticKHR                   : I32EnumAttrCase<"GroupUniformArithmeticKHR", 6400> {
+  list<Availability> availability = [
+    Extension<[SPV_KHR_uniform_group_instructions]>
+  ];
+}
 def SPV_C_Shader                                      : I32EnumAttrCase<"Shader", 1> {
   list<I32EnumAttrCase> implies = [SPV_C_Matrix];
 }
 def SPV_C_Vector16                                    : I32EnumAttrCase<"Vector16", 7> {
   list<I32EnumAttrCase> implies = [SPV_C_Kernel];
 }
 def SPV_C_Float16Buffer                               : I32EnumAttrCase<"Float16Buffer", 8> {
   list<I32EnumAttrCase> implies = [SPV_C_Kernel];
def SPV_C_VectorComputeINTEL                          : I32EnumAttrCase<"VectorComputeINTEL", 5617> {
   ];
 }
 def SPV_C_FPFastMathModeINTEL                         : I32EnumAttrCase<"FPFastMathModeINTEL", 5837> {
   list<I32EnumAttrCase> implies = [SPV_C_Kernel];
   list<Availability> availability = [
     Extension<[SPV_INTEL_fp_fast_math_mode]>
   ];
 }
-def SPV_C_DotProductInput4x8BitKHR                    : I32EnumAttrCase<"DotProductInput4x8BitKHR", 6017> {
+def SPV_C_DotProductInput4x8Bit                       : I32EnumAttrCase<"DotProductInput4x8Bit", 6017> {
   list<I32EnumAttrCase> implies = [SPV_C_Int8];
   list<Availability> availability = [
-    Extension<[SPV_KHR_integer_dot_product]>
+    MinVersion<SPV_V_1_6>
+  ];
+}
+def SPV_C_GroupNonUniformRotateKHR                    : I32EnumAttrCase<"GroupNonUniformRotateKHR", 6026> {
+  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+  list<Availability> availability = [
+    Extension<[SPV_KHR_subgroup_rotate]>
   ];
 }
 def SPV_C_Geometry                                    : I32EnumAttrCase<"Geometry", 2> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
 }
 def SPV_C_Tessellation                                : I32EnumAttrCase<"Tessellation", 3> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
 }
def SPV_C_ShaderSMBuiltinsNV                          : I32EnumAttrCase<"ShaderSMBuiltinsNV", 5373> {
   ];
 }
 def SPV_C_FragmentShaderPixelInterlockEXT             : I32EnumAttrCase<"FragmentShaderPixelInterlockEXT", 5378> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
     Extension<[SPV_EXT_fragment_shader_interlock]>
   ];
 }
-def SPV_C_DemoteToHelperInvocationEXT                 : I32EnumAttrCase<"DemoteToHelperInvocationEXT", 5379> {
+def SPV_C_DemoteToHelperInvocation                    : I32EnumAttrCase<"DemoteToHelperInvocation", 5379> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_demote_to_helper_invocation]>
+    MinVersion<SPV_V_1_6>
   ];
 }
 def SPV_C_IntegerFunctions2INTEL                      : I32EnumAttrCase<"IntegerFunctions2INTEL", 5584> {
   list<I32EnumAttrCase> implies = [SPV_C_Shader];
   list<Availability> availability = [
     Extension<[SPV_INTEL_shader_integer_functions2]>
   ];
 }
-def SPV_C_AtomicFloat32AddEXT                         : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
-  // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
-  // list<I32EnumAttrCase> implies = [SPV_C_Shader];
-  list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_add]>
-  ];
-}
-def SPV_C_AtomicFloat64AddEXT                         : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
-  // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
-  // list<I32EnumAttrCase> implies = [SPV_C_Shader];
-  list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_add]>
-  ];
-}
-def SPV_C_AtomicFloat16AddEXT                         : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
-  // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
-  // list<I32EnumAttrCase> implies = [SPV_C_Shader];
-  list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float16_add]>
-  ];
-}
 def SPV_C_TessellationPointSize                       : I32EnumAttrCase<"TessellationPointSize", 23> {
   list<I32EnumAttrCase> implies = [SPV_C_Tessellation];
 }
 def SPV_C_GeometryPointSize                           : I32EnumAttrCase<"GeometryPointSize", 24> {
   list<I32EnumAttrCase> implies = [SPV_C_Geometry];
 }
 def SPV_C_ImageCubeArray                              : I32EnumAttrCase<"ImageCubeArray", 34> {
   list<I32EnumAttrCase> implies = [SPV_C_SampledCubeArray];
def SPV_C_ShaderStereoViewNV                          : I32EnumAttrCase<"ShaderStereoViewNV", 5259> {
   ];
 }
 
 def SPV_CapabilityAttr :
     SPV_I32EnumAttr<"Capability", "valid SPIR-V Capability", [
       SPV_C_Matrix, SPV_C_Addresses, SPV_C_Linkage, SPV_C_Kernel, SPV_C_Float16,
       SPV_C_Float64, SPV_C_Int64, SPV_C_Groups, SPV_C_Int16, SPV_C_Int8,
       SPV_C_Sampled1D, SPV_C_SampledBuffer, SPV_C_GroupNonUniform, SPV_C_ShaderLayer,
-      SPV_C_ShaderViewportIndex, SPV_C_SubgroupBallotKHR, SPV_C_SubgroupVoteKHR,
-      SPV_C_StorageBuffer16BitAccess, SPV_C_StoragePushConstant16,
-      SPV_C_StorageInputOutput16, SPV_C_DeviceGroup, SPV_C_AtomicStorageOps,
-      SPV_C_SampleMaskPostDepthCoverage, SPV_C_StorageBuffer8BitAccess,
-      SPV_C_StoragePushConstant8, SPV_C_DenormPreserve, SPV_C_DenormFlushToZero,
-      SPV_C_SignedZeroInfNanPreserve, SPV_C_RoundingModeRTE, SPV_C_RoundingModeRTZ,
-      SPV_C_ImageFootprintNV, SPV_C_FragmentBarycentricNV,
-      SPV_C_ComputeDerivativeGroupQuadsNV, SPV_C_GroupNonUniformPartitionedNV,
-      SPV_C_VulkanMemoryModel, SPV_C_VulkanMemoryModelDeviceScope,
-      SPV_C_ComputeDerivativeGroupLinearNV, SPV_C_BindlessTextureNV,
-      SPV_C_SubgroupShuffleINTEL, SPV_C_SubgroupBufferBlockIOINTEL,
-      SPV_C_SubgroupImageBlockIOINTEL, SPV_C_SubgroupImageMediaBlockIOINTEL,
-      SPV_C_RoundToInfinityINTEL, SPV_C_FloatingPointModeINTEL,
-      SPV_C_FunctionPointersINTEL, SPV_C_IndirectReferencesINTEL, SPV_C_AsmINTEL,
-      SPV_C_AtomicFloat32MinMaxEXT, SPV_C_AtomicFloat64MinMaxEXT,
-      SPV_C_AtomicFloat16MinMaxEXT, SPV_C_VectorAnyINTEL, SPV_C_ExpectAssumeKHR,
+      SPV_C_ShaderViewportIndex, SPV_C_UniformDecoration, SPV_C_SubgroupBallotKHR,
+      SPV_C_SubgroupVoteKHR, SPV_C_StorageBuffer16BitAccess,
+      SPV_C_StoragePushConstant16, SPV_C_StorageInputOutput16, SPV_C_DeviceGroup,
+      SPV_C_AtomicStorageOps, SPV_C_SampleMaskPostDepthCoverage,
+      SPV_C_StorageBuffer8BitAccess, SPV_C_StoragePushConstant8,
+      SPV_C_DenormPreserve, SPV_C_DenormFlushToZero, SPV_C_SignedZeroInfNanPreserve,
+      SPV_C_RoundingModeRTE, SPV_C_RoundingModeRTZ, SPV_C_ImageFootprintNV,
+      SPV_C_FragmentBarycentricKHR, SPV_C_ComputeDerivativeGroupQuadsNV,
+      SPV_C_GroupNonUniformPartitionedNV, SPV_C_VulkanMemoryModel,
+      SPV_C_VulkanMemoryModelDeviceScope, SPV_C_ComputeDerivativeGroupLinearNV,
+      SPV_C_BindlessTextureNV, SPV_C_SubgroupShuffleINTEL,
+      SPV_C_SubgroupBufferBlockIOINTEL, SPV_C_SubgroupImageBlockIOINTEL,
+      SPV_C_SubgroupImageMediaBlockIOINTEL, SPV_C_RoundToInfinityINTEL,
+      SPV_C_FloatingPointModeINTEL, SPV_C_FunctionPointersINTEL,
+      SPV_C_IndirectReferencesINTEL, SPV_C_AsmINTEL, SPV_C_AtomicFloat32MinMaxEXT,
+      SPV_C_AtomicFloat64MinMaxEXT, SPV_C_AtomicFloat16MinMaxEXT,
+      SPV_C_VectorAnyINTEL, SPV_C_ExpectAssumeKHR,
       SPV_C_SubgroupAvcMotionEstimationINTEL,
       SPV_C_SubgroupAvcMotionEstimationIntraINTEL,
       SPV_C_SubgroupAvcMotionEstimationChromaINTEL, SPV_C_VariableLengthArrayINTEL,
       SPV_C_FunctionFloatControlINTEL, SPV_C_FPGAMemoryAttributesINTEL,
       SPV_C_ArbitraryPrecisionIntegersINTEL,
       SPV_C_ArbitraryPrecisionFloatingPointINTEL,
       SPV_C_UnstructuredLoopControlsINTEL, SPV_C_FPGALoopControlsINTEL,
       SPV_C_KernelAttributesINTEL, SPV_C_FPGAKernelAttributesINTEL,
       SPV_C_FPGAMemoryAccessesINTEL, SPV_C_FPGAClusterAttributesINTEL,
-      SPV_C_LoopFuseINTEL, SPV_C_FPGABufferLocationINTEL,
-      SPV_C_ArbitraryPrecisionFixedPointINTEL, SPV_C_USMStorageClassesINTEL,
-      SPV_C_IOPipesINTEL, SPV_C_BlockingPipesINTEL, SPV_C_FPGARegINTEL,
-      SPV_C_DotProductInputAllKHR, SPV_C_DotProductInput4x8BitPackedKHR,
-      SPV_C_DotProductKHR, SPV_C_BitInstructions, SPV_C_LongConstantCompositeINTEL,
-      SPV_C_OptNoneINTEL, SPV_C_DebugInfoModuleINTEL, SPV_C_Shader, SPV_C_Vector16,
+      SPV_C_LoopFuseINTEL, SPV_C_MemoryAccessAliasingINTEL,
+      SPV_C_FPGABufferLocationINTEL, SPV_C_ArbitraryPrecisionFixedPointINTEL,
+      SPV_C_USMStorageClassesINTEL, SPV_C_IOPipesINTEL, SPV_C_BlockingPipesINTEL,
+      SPV_C_FPGARegINTEL, SPV_C_DotProductInputAll,
+      SPV_C_DotProductInput4x8BitPacked, SPV_C_DotProduct, SPV_C_RayCullMaskKHR,
+      SPV_C_BitInstructions, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT,
+      SPV_C_LongConstantCompositeINTEL, SPV_C_OptNoneINTEL,
+      SPV_C_AtomicFloat16AddEXT, SPV_C_DebugInfoModuleINTEL, SPV_C_SplitBarrierINTEL,
+      SPV_C_GroupUniformArithmeticKHR, SPV_C_Shader, SPV_C_Vector16,
       SPV_C_Float16Buffer, SPV_C_Int64Atomics, SPV_C_ImageBasic, SPV_C_Pipes,
       SPV_C_DeviceEnqueue, SPV_C_LiteralSampler, SPV_C_GenericPointer, SPV_C_Image1D,
       SPV_C_ImageBuffer, SPV_C_NamedBarrier, SPV_C_GroupNonUniformVote,
       SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot,
       SPV_C_GroupNonUniformShuffle, SPV_C_GroupNonUniformShuffleRelative,
       SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformQuad,
       SPV_C_StorageUniform16, SPV_C_UniformAndStorageBuffer8BitAccess,
       SPV_C_UniformTexelBufferArrayDynamicIndexing, SPV_C_VectorComputeINTEL,
-      SPV_C_FPFastMathModeINTEL, SPV_C_DotProductInput4x8BitKHR, SPV_C_Geometry,
-      SPV_C_Tessellation, SPV_C_ImageReadWrite, SPV_C_ImageMipmap,
-      SPV_C_AtomicStorage, SPV_C_ImageGatherExtended, SPV_C_StorageImageMultisample,
+      SPV_C_FPFastMathModeINTEL, SPV_C_DotProductInput4x8Bit,
+      SPV_C_GroupNonUniformRotateKHR, SPV_C_Geometry, SPV_C_Tessellation,
+      SPV_C_ImageReadWrite, SPV_C_ImageMipmap, SPV_C_AtomicStorage,
+      SPV_C_ImageGatherExtended, SPV_C_StorageImageMultisample,
       SPV_C_UniformBufferArrayDynamicIndexing,
       SPV_C_SampledImageArrayDynamicIndexing,
       SPV_C_StorageBufferArrayDynamicIndexing,
       SPV_C_StorageImageArrayDynamicIndexing, SPV_C_ClipDistance, SPV_C_CullDistance,
       SPV_C_SampleRateShading, SPV_C_SampledRect, SPV_C_InputAttachment,
       SPV_C_SparseResidency, SPV_C_MinLod, SPV_C_SampledCubeArray,
       SPV_C_ImageMSArray, SPV_C_StorageImageExtendedFormats, SPV_C_ImageQuery,
       SPV_C_DerivativeControl, SPV_C_InterpolationFunction, SPV_C_TransformFeedback,
       SPV_C_StorageImageReadWithoutFormat, SPV_C_StorageImageWriteWithoutFormat,
       SPV_C_SubgroupDispatch, SPV_C_PipeStorage, SPV_C_FragmentShadingRateKHR,
       SPV_C_DrawParameters, SPV_C_WorkgroupMemoryExplicitLayoutKHR,
       SPV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR, SPV_C_MultiView,
       SPV_C_VariablePointersStorageBuffer, SPV_C_RayQueryProvisionalKHR,
       SPV_C_RayQueryKHR, SPV_C_RayTracingKHR, SPV_C_Float16ImageAMD,
       SPV_C_ImageGatherBiasLodAMD, SPV_C_FragmentMaskAMD, SPV_C_StencilExportEXT,
       SPV_C_ImageReadWriteLodAMD, SPV_C_Int64ImageEXT, SPV_C_ShaderClockKHR,
       SPV_C_FragmentFullyCoveredEXT, SPV_C_MeshShadingNV, SPV_C_FragmentDensityEXT,
       SPV_C_ShaderNonUniform, SPV_C_RuntimeDescriptorArray,
       SPV_C_StorageTexelBufferArrayDynamicIndexing, SPV_C_RayTracingNV,
       SPV_C_RayTracingMotionBlurNV, SPV_C_PhysicalStorageBufferAddresses,
       SPV_C_RayTracingProvisionalKHR, SPV_C_CooperativeMatrixNV,
       SPV_C_FragmentShaderSampleInterlockEXT,
       SPV_C_FragmentShaderShadingRateInterlockEXT, SPV_C_ShaderSMBuiltinsNV,
-      SPV_C_FragmentShaderPixelInterlockEXT, SPV_C_DemoteToHelperInvocationEXT,
-      SPV_C_IntegerFunctions2INTEL, SPV_C_AtomicFloat32AddEXT,
-      SPV_C_AtomicFloat64AddEXT, SPV_C_AtomicFloat16AddEXT,
-      SPV_C_TessellationPointSize, SPV_C_GeometryPointSize, SPV_C_ImageCubeArray,
-      SPV_C_ImageRect, SPV_C_GeometryStreams, SPV_C_MultiViewport,
+      SPV_C_FragmentShaderPixelInterlockEXT, SPV_C_DemoteToHelperInvocation,
+      SPV_C_IntegerFunctions2INTEL, SPV_C_TessellationPointSize,
+      SPV_C_GeometryPointSize, SPV_C_ImageCubeArray, SPV_C_ImageRect,
+      SPV_C_GeometryStreams, SPV_C_MultiViewport,
       SPV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR, SPV_C_VariablePointers,
       SPV_C_RayTraversalPrimitiveCullingKHR, SPV_C_SampleMaskOverrideCoverageNV,
       SPV_C_GeometryShaderPassthroughNV, SPV_C_PerViewAttributesNV,
       SPV_C_InputAttachmentArrayDynamicIndexing,
       SPV_C_UniformBufferArrayNonUniformIndexing,
       SPV_C_SampledImageArrayNonUniformIndexing,
       SPV_C_StorageBufferArrayNonUniformIndexing,
       SPV_C_StorageImageArrayNonUniformIndexing,
def SPV_BI_MeshViewCountNV             : I32EnumAttrCase<"MeshViewCountNV", 5280> {
   ];
 }
 def SPV_BI_MeshViewIndicesNV           : I32EnumAttrCase<"MeshViewIndicesNV", 5281> {
   list<Availability> availability = [
     Extension<[SPV_NV_mesh_shader]>,
     Capability<[SPV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_BaryCoordNV                 : I32EnumAttrCase<"BaryCoordNV", 5286> {
+def SPV_BI_BaryCoordKHR                : I32EnumAttrCase<"BaryCoordKHR", 5286> {
   list<Availability> availability = [
-    Extension<[SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricNV]>
+    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+    Capability<[SPV_C_FragmentBarycentricKHR]>
   ];
 }
-def SPV_BI_BaryCoordNoPerspNV          : I32EnumAttrCase<"BaryCoordNoPerspNV", 5287> {
+def SPV_BI_BaryCoordNoPerspKHR         : I32EnumAttrCase<"BaryCoordNoPerspKHR", 5287> {
   list<Availability> availability = [
-    Extension<[SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricNV]>
+    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+    Capability<[SPV_C_FragmentBarycentricKHR]>
   ];
 }
 def SPV_BI_FragSizeEXT                 : I32EnumAttrCase<"FragSizeEXT", 5292> {
   list<Availability> availability = [
     Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>,
     Capability<[SPV_C_FragmentDensityEXT]>
   ];
 }
def SPV_BI_WarpIDNV                    : I32EnumAttrCase<"WarpIDNV", 5376> {
   ];
 }
 def SPV_BI_SMIDNV                      : I32EnumAttrCase<"SMIDNV", 5377> {
   list<Availability> availability = [
     Extension<[SPV_NV_shader_sm_builtins]>,
     Capability<[SPV_C_ShaderSMBuiltinsNV]>
   ];
 }
+def SPV_BI_CullMaskKHR                 : I32EnumAttrCase<"CullMaskKHR", 6021> {
+  list<Availability> availability = [
+    Extension<[SPV_KHR_ray_cull_mask]>,
+    Capability<[SPV_C_RayCullMaskKHR]>
+  ];
+}
 
 def SPV_BuiltInAttr :
     SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", [
       SPV_BI_Position, SPV_BI_PointSize, SPV_BI_ClipDistance, SPV_BI_CullDistance,
       SPV_BI_VertexId, SPV_BI_InstanceId, SPV_BI_PrimitiveId, SPV_BI_InvocationId,
       SPV_BI_Layer, SPV_BI_ViewportIndex, SPV_BI_TessLevelOuter,
       SPV_BI_TessLevelInner, SPV_BI_TessCoord, SPV_BI_PatchVertices,
       SPV_BI_FragCoord, SPV_BI_PointCoord, SPV_BI_FrontFacing, SPV_BI_SampleId,
SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", [
       SPV_BI_BaryCoordNoPerspSampleAMD, SPV_BI_BaryCoordSmoothAMD,
       SPV_BI_BaryCoordSmoothCentroidAMD, SPV_BI_BaryCoordSmoothSampleAMD,
       SPV_BI_BaryCoordPullModelAMD, SPV_BI_FragStencilRefEXT, SPV_BI_ViewportMaskNV,
       SPV_BI_SecondaryPositionNV, SPV_BI_SecondaryViewportMaskNV,
       SPV_BI_PositionPerViewNV, SPV_BI_ViewportMaskPerViewNV, SPV_BI_FullyCoveredEXT,
       SPV_BI_TaskCountNV, SPV_BI_PrimitiveCountNV, SPV_BI_PrimitiveIndicesNV,
       SPV_BI_ClipDistancePerViewNV, SPV_BI_CullDistancePerViewNV,
       SPV_BI_LayerPerViewNV, SPV_BI_MeshViewCountNV, SPV_BI_MeshViewIndicesNV,
-      SPV_BI_BaryCoordNV, SPV_BI_BaryCoordNoPerspNV, SPV_BI_FragSizeEXT,
+      SPV_BI_BaryCoordKHR, SPV_BI_BaryCoordNoPerspKHR, SPV_BI_FragSizeEXT,
       SPV_BI_FragInvocationCountEXT, SPV_BI_LaunchIdKHR, SPV_BI_LaunchSizeKHR,
       SPV_BI_WorldRayOriginKHR, SPV_BI_WorldRayDirectionKHR,
       SPV_BI_ObjectRayOriginKHR, SPV_BI_ObjectRayDirectionKHR, SPV_BI_RayTminKHR,
       SPV_BI_RayTmaxKHR, SPV_BI_InstanceCustomIndexKHR, SPV_BI_ObjectToWorldKHR,
       SPV_BI_WorldToObjectKHR, SPV_BI_HitTNV, SPV_BI_HitKindKHR,
       SPV_BI_CurrentRayTimeNV, SPV_BI_IncomingRayFlagsKHR,
       SPV_BI_RayGeometryIndexKHR, SPV_BI_WarpsPerSMNV, SPV_BI_SMCountNV,
-      SPV_BI_WarpIDNV, SPV_BI_SMIDNV
+      SPV_BI_WarpIDNV, SPV_BI_SMIDNV, SPV_BI_CullMaskKHR
     ]>;
 
 def SPV_D_RelaxedPrecision                   : I32EnumAttrCase<"RelaxedPrecision", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_D_SpecId                             : I32EnumAttrCase<"SpecId", 1> {
list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_D_MatrixStride                       : I32EnumAttrCase<"MatrixStride", 7> {
   list<Availability> availability = [
     Capability<[SPV_C_Matrix]>
   ];
 }
-def SPV_D_GLShared                           : I32EnumAttrCase<"GLShared", 8> {
+def SPV_D_GLSLShared                         : I32EnumAttrCase<"GLSLShared", 8> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
-def SPV_D_GLPacked                           : I32EnumAttrCase<"GLPacked", 9> {
+def SPV_D_GLSLPacked                         : I32EnumAttrCase<"GLSLPacked", 9> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_D_CPacked                            : I32EnumAttrCase<"CPacked", 10> {
   list<Availability> availability = [
     Capability<[SPV_C_Kernel]>
   ];
list<Availability> availability = [
     Capability<[SPV_C_Kernel]>
   ];
 }
 def SPV_D_Coherent                           : I32EnumAttrCase<"Coherent", 23>;
 def SPV_D_NonWritable                        : I32EnumAttrCase<"NonWritable", 24>;
 def SPV_D_NonReadable                        : I32EnumAttrCase<"NonReadable", 25>;
 def SPV_D_Uniform                            : I32EnumAttrCase<"Uniform", 26> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
   ];
 }
 def SPV_D_UniformId                          : I32EnumAttrCase<"UniformId", 27> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_4>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
   ];
 }
 def SPV_D_SaturatedConversion                : I32EnumAttrCase<"SaturatedConversion", 28> {
   list<Availability> availability = [
     Capability<[SPV_C_Kernel]>
   ];
 }
 def SPV_D_Stream                             : I32EnumAttrCase<"Stream", 29> {
def SPV_D_PerViewNV                          : I32EnumAttrCase<"PerViewNV", 5272> {
   ];
 }
 def SPV_D_PerTaskNV                          : I32EnumAttrCase<"PerTaskNV", 5273> {
   list<Availability> availability = [
     Extension<[SPV_NV_mesh_shader]>,
     Capability<[SPV_C_MeshShadingNV]>
   ];
 }
-def SPV_D_PerVertexNV                        : I32EnumAttrCase<"PerVertexNV", 5285> {
+def SPV_D_PerVertexKHR                       : I32EnumAttrCase<"PerVertexKHR", 5285> {
   list<Availability> availability = [
-    Extension<[SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricNV]>
+    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+    Capability<[SPV_C_FragmentBarycentricKHR]>
   ];
 }
 def SPV_D_NonUniform                         : I32EnumAttrCase<"NonUniform", 5300> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>,
     Capability<[SPV_C_ShaderNonUniform]>
   ];
 }
list<Availability> availability = [
     Capability<[SPV_C_FPGAClusterAttributesINTEL]>
   ];
 }
 def SPV_D_FuseLoopsInFunctionINTEL           : I32EnumAttrCase<"FuseLoopsInFunctionINTEL", 5907> {
   list<Availability> availability = [
     Capability<[SPV_C_LoopFuseINTEL]>
   ];
 }
+def SPV_D_AliasScopeINTEL                    : I32EnumAttrCase<"AliasScopeINTEL", 5914> {
+  list<Availability> availability = [
+    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+  ];
+}
+def SPV_D_NoAliasINTEL                       : I32EnumAttrCase<"NoAliasINTEL", 5915> {
+  list<Availability> availability = [
+    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+  ];
+}
 def SPV_D_BufferLocationINTEL                : I32EnumAttrCase<"BufferLocationINTEL", 5921> {
   list<Availability> availability = [
     Capability<[SPV_C_FPGABufferLocationINTEL]>
   ];
 }
 def SPV_D_IOPipeStorageINTEL                 : I32EnumAttrCase<"IOPipeStorageINTEL", 5944> {
   list<Availability> availability = [
     Capability<[SPV_C_IOPipesINTEL]>
list<Availability> availability = [
     Capability<[SPV_C_VectorComputeINTEL]>
   ];
 }
 def SPV_D_VectorComputeCallableFunctionINTEL : I32EnumAttrCase<"VectorComputeCallableFunctionINTEL", 6087> {
   list<Availability> availability = [
     Capability<[SPV_C_VectorComputeINTEL]>
   ];
 }
+def SPV_D_MediaBlockIOINTEL                  : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> {
+  list<Availability> availability = [
+    Capability<[SPV_C_VectorComputeINTEL]>
+  ];
+}
 
 def SPV_DecorationAttr :
     SPV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", [
       SPV_D_RelaxedPrecision, SPV_D_SpecId, SPV_D_Block, SPV_D_BufferBlock,
       SPV_D_RowMajor, SPV_D_ColMajor, SPV_D_ArrayStride, SPV_D_MatrixStride,
-      SPV_D_GLShared, SPV_D_GLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
+      SPV_D_GLSLShared, SPV_D_GLSLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
       SPV_D_NoPerspective, SPV_D_Flat, SPV_D_Patch, SPV_D_Centroid, SPV_D_Sample,
       SPV_D_Invariant, SPV_D_Restrict, SPV_D_Aliased, SPV_D_Volatile, SPV_D_Constant,
       SPV_D_Coherent, SPV_D_NonWritable, SPV_D_NonReadable, SPV_D_Uniform,
       SPV_D_UniformId, SPV_D_SaturatedConversion, SPV_D_Stream, SPV_D_Location,
       SPV_D_Component, SPV_D_Index, SPV_D_Binding, SPV_D_DescriptorSet, SPV_D_Offset,
       SPV_D_XfbBuffer, SPV_D_XfbStride, SPV_D_FuncParamAttr, SPV_D_FPRoundingMode,
       SPV_D_FPFastMathMode, SPV_D_LinkageAttributes, SPV_D_NoContraction,
       SPV_D_InputAttachmentIndex, SPV_D_Alignment, SPV_D_MaxByteOffset,
       SPV_D_AlignmentId, SPV_D_MaxByteOffsetId, SPV_D_NoSignedWrap,
       SPV_D_NoUnsignedWrap, SPV_D_ExplicitInterpAMD, SPV_D_OverrideCoverageNV,
       SPV_D_PassthroughNV, SPV_D_ViewportRelativeNV,
       SPV_D_SecondaryViewportRelativeNV, SPV_D_PerPrimitiveNV, SPV_D_PerViewNV,
-      SPV_D_PerTaskNV, SPV_D_PerVertexNV, SPV_D_NonUniform, SPV_D_RestrictPointer,
+      SPV_D_PerTaskNV, SPV_D_PerVertexKHR, SPV_D_NonUniform, SPV_D_RestrictPointer,
       SPV_D_AliasedPointer, SPV_D_BindlessSamplerNV, SPV_D_BindlessImageNV,
       SPV_D_BoundSamplerNV, SPV_D_BoundImageNV, SPV_D_SIMTCallINTEL,
       SPV_D_ReferencedIndirectlyINTEL, SPV_D_ClobberINTEL, SPV_D_SideEffectsINTEL,
       SPV_D_VectorComputeVariableINTEL, SPV_D_FuncParamIOKindINTEL,
       SPV_D_VectorComputeFunctionINTEL, SPV_D_StackCallINTEL,
       SPV_D_GlobalVariableOffsetINTEL, SPV_D_CounterBuffer, SPV_D_UserSemantic,
       SPV_D_UserTypeGOOGLE, SPV_D_FunctionRoundingModeINTEL,
       SPV_D_FunctionDenormModeINTEL, SPV_D_RegisterINTEL, SPV_D_MemoryINTEL,
       SPV_D_NumbanksINTEL, SPV_D_BankwidthINTEL, SPV_D_MaxPrivateCopiesINTEL,
       SPV_D_SinglepumpINTEL, SPV_D_DoublepumpINTEL, SPV_D_MaxReplicatesINTEL,
       SPV_D_SimpleDualPortINTEL, SPV_D_MergeINTEL, SPV_D_BankBitsINTEL,
       SPV_D_ForcePow2DepthINTEL, SPV_D_BurstCoalesceINTEL, SPV_D_CacheSizeINTEL,
       SPV_D_DontStaticallyCoalesceINTEL, SPV_D_PrefetchINTEL, SPV_D_StallEnableINTEL,
-      SPV_D_FuseLoopsInFunctionINTEL, SPV_D_BufferLocationINTEL,
-      SPV_D_IOPipeStorageINTEL, SPV_D_FunctionFloatingPointModeINTEL,
-      SPV_D_SingleElementVectorINTEL, SPV_D_VectorComputeCallableFunctionINTEL
+      SPV_D_FuseLoopsInFunctionINTEL, SPV_D_AliasScopeINTEL, SPV_D_NoAliasINTEL,
+      SPV_D_BufferLocationINTEL, SPV_D_IOPipeStorageINTEL,
+      SPV_D_FunctionFloatingPointModeINTEL, SPV_D_SingleElementVectorINTEL,
+      SPV_D_VectorComputeCallableFunctionINTEL, SPV_D_MediaBlockIOINTEL
     ]>;
 
 def SPV_D_1D          : I32EnumAttrCase<"Dim1D", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Image1D, SPV_C_Sampled1D]>
   ];
 }
 def SPV_D_2D          : I32EnumAttrCase<"Dim2D", 1> {
def SPV_EM_RoundingModeRTE                  : I32EnumAttrCase<"RoundingModeRTE", 4462> {
   ];
 }
 def SPV_EM_RoundingModeRTZ                  : I32EnumAttrCase<"RoundingModeRTZ", 4463> {
   list<Availability> availability = [
     Extension<[SPV_KHR_float_controls]>,
     Capability<[SPV_C_RoundingModeRTZ]>
   ];
 }
+def SPV_EM_EarlyAndLateFragmentTestsAMD     : I32EnumAttrCase<"EarlyAndLateFragmentTestsAMD", 5017> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests]>,
+    Capability<[SPV_C_Shader]>
+  ];
+}
 def SPV_EM_StencilRefReplacingEXT           : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> {
   list<Availability> availability = [
     Extension<[SPV_EXT_shader_stencil_export]>,
     Capability<[SPV_C_StencilExportEXT]>
   ];
 }
+def SPV_EM_StencilRefUnchangedFrontAMD      : I32EnumAttrCase<"StencilRefUnchangedFrontAMD", 5079> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
+def SPV_EM_StencilRefGreaterFrontAMD        : I32EnumAttrCase<"StencilRefGreaterFrontAMD", 5080> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
+def SPV_EM_StencilRefLessFrontAMD           : I32EnumAttrCase<"StencilRefLessFrontAMD", 5081> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
+def SPV_EM_StencilRefUnchangedBackAMD       : I32EnumAttrCase<"StencilRefUnchangedBackAMD", 5082> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
+def SPV_EM_StencilRefGreaterBackAMD         : I32EnumAttrCase<"StencilRefGreaterBackAMD", 5083> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
+def SPV_EM_StencilRefLessBackAMD            : I32EnumAttrCase<"StencilRefLessBackAMD", 5084> {
+  list<Availability> availability = [
+    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+    Capability<[SPV_C_StencilExportEXT]>
+  ];
+}
 def SPV_EM_OutputLinesNV                    : I32EnumAttrCase<"OutputLinesNV", 5269> {
   list<Availability> availability = [
     Extension<[SPV_NV_mesh_shader]>,
     Capability<[SPV_C_MeshShadingNV]>
   ];
 }
 def SPV_EM_OutputPrimitivesNV               : I32EnumAttrCase<"OutputPrimitivesNV", 5270> {
   list<Availability> availability = [
list<Availability> availability = [
     Capability<[SPV_C_FPGAKernelAttributesINTEL]>
   ];
 }
 def SPV_EM_SchedulerTargetFmaxMhzINTEL      : I32EnumAttrCase<"SchedulerTargetFmaxMhzINTEL", 5903> {
   list<Availability> availability = [
     Capability<[SPV_C_FPGAKernelAttributesINTEL]>
   ];
 }
+def SPV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
+  list<Availability> availability = [
+    Capability<[SPV_C_VectorComputeINTEL]>
+  ];
+}
 
 def SPV_ExecutionModeAttr :
     SPV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", [
       SPV_EM_Invocations, SPV_EM_SpacingEqual, SPV_EM_SpacingFractionalEven,
       SPV_EM_SpacingFractionalOdd, SPV_EM_VertexOrderCw, SPV_EM_VertexOrderCcw,
       SPV_EM_PixelCenterInteger, SPV_EM_OriginUpperLeft, SPV_EM_OriginLowerLeft,
       SPV_EM_EarlyFragmentTests, SPV_EM_PointMode, SPV_EM_Xfb, SPV_EM_DepthReplacing,
       SPV_EM_DepthGreater, SPV_EM_DepthLess, SPV_EM_DepthUnchanged, SPV_EM_LocalSize,
       SPV_EM_LocalSizeHint, SPV_EM_InputPoints, SPV_EM_InputLines,
       SPV_EM_InputLinesAdjacency, SPV_EM_Triangles, SPV_EM_InputTrianglesAdjacency,
       SPV_EM_Quads, SPV_EM_Isolines, SPV_EM_OutputVertices, SPV_EM_OutputPoints,
       SPV_EM_OutputLineStrip, SPV_EM_OutputTriangleStrip, SPV_EM_VecTypeHint,
       SPV_EM_ContractionOff, SPV_EM_Initializer, SPV_EM_Finalizer,
       SPV_EM_SubgroupSize, SPV_EM_SubgroupsPerWorkgroup,
       SPV_EM_SubgroupsPerWorkgroupId, SPV_EM_LocalSizeId, SPV_EM_LocalSizeHintId,
       SPV_EM_SubgroupUniformControlFlowKHR, SPV_EM_PostDepthCoverage,
       SPV_EM_DenormPreserve, SPV_EM_DenormFlushToZero,
       SPV_EM_SignedZeroInfNanPreserve, SPV_EM_RoundingModeRTE,
-      SPV_EM_RoundingModeRTZ, SPV_EM_StencilRefReplacingEXT, SPV_EM_OutputLinesNV,
-      SPV_EM_OutputPrimitivesNV, SPV_EM_DerivativeGroupQuadsNV,
-      SPV_EM_DerivativeGroupLinearNV, SPV_EM_OutputTrianglesNV,
-      SPV_EM_PixelInterlockOrderedEXT, SPV_EM_PixelInterlockUnorderedEXT,
-      SPV_EM_SampleInterlockOrderedEXT, SPV_EM_SampleInterlockUnorderedEXT,
-      SPV_EM_ShadingRateInterlockOrderedEXT, SPV_EM_ShadingRateInterlockUnorderedEXT,
-      SPV_EM_SharedLocalMemorySizeINTEL, SPV_EM_RoundingModeRTPINTEL,
-      SPV_EM_RoundingModeRTNINTEL, SPV_EM_FloatingPointModeALTINTEL,
-      SPV_EM_FloatingPointModeIEEEINTEL, SPV_EM_MaxWorkgroupSizeINTEL,
-      SPV_EM_MaxWorkDimINTEL, SPV_EM_NoGlobalOffsetINTEL,
-      SPV_EM_NumSIMDWorkitemsINTEL, SPV_EM_SchedulerTargetFmaxMhzINTEL
+      SPV_EM_RoundingModeRTZ, SPV_EM_EarlyAndLateFragmentTestsAMD,
+      SPV_EM_StencilRefReplacingEXT, SPV_EM_StencilRefUnchangedFrontAMD,
+      SPV_EM_StencilRefGreaterFrontAMD, SPV_EM_StencilRefLessFrontAMD,
+      SPV_EM_StencilRefUnchangedBackAMD, SPV_EM_StencilRefGreaterBackAMD,
+      SPV_EM_StencilRefLessBackAMD, SPV_EM_OutputLinesNV, SPV_EM_OutputPrimitivesNV,
+      SPV_EM_DerivativeGroupQuadsNV, SPV_EM_DerivativeGroupLinearNV,
+      SPV_EM_OutputTrianglesNV, SPV_EM_PixelInterlockOrderedEXT,
+      SPV_EM_PixelInterlockUnorderedEXT, SPV_EM_SampleInterlockOrderedEXT,
+      SPV_EM_SampleInterlockUnorderedEXT, SPV_EM_ShadingRateInterlockOrderedEXT,
+      SPV_EM_ShadingRateInterlockUnorderedEXT, SPV_EM_SharedLocalMemorySizeINTEL,
+      SPV_EM_RoundingModeRTPINTEL, SPV_EM_RoundingModeRTNINTEL,
+      SPV_EM_FloatingPointModeALTINTEL, SPV_EM_FloatingPointModeIEEEINTEL,
+      SPV_EM_MaxWorkgroupSizeINTEL, SPV_EM_MaxWorkDimINTEL,
+      SPV_EM_NoGlobalOffsetINTEL, SPV_EM_NumSIMDWorkitemsINTEL,
+      SPV_EM_SchedulerTargetFmaxMhzINTEL, SPV_EM_NamedBarrierCountINTEL
     ]>;
 
 def SPV_EM_Vertex                 : I32EnumAttrCase<"Vertex", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_EM_TessellationControl    : I32EnumAttrCase<"TessellationControl", 1> {
def SPV_IO_SignExtend         : I32BitEnumAttrCaseBit<"SignExtend", 12> {
   ];
 }
 def SPV_IO_Offsets            : I32BitEnumAttrCaseBit<"Offsets", 16>;
 def SPV_IO_ZeroExtend         : I32BitEnumAttrCaseBit<"ZeroExtend", 13> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_4>
   ];
 }
+def SPV_IO_Nontemporal        : I32BitEnumAttrCaseBit<"Nontemporal", 14> {
+  list<Availability> availability = [
+    MinVersion<SPV_V_1_6>
+  ];
+}
 
 def SPV_ImageOperandsAttr :
     SPV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", [
       SPV_IO_None, SPV_IO_Bias, SPV_IO_Lod, SPV_IO_Grad, SPV_IO_ConstOffset,
       SPV_IO_Offset, SPV_IO_ConstOffsets, SPV_IO_Sample, SPV_IO_MinLod,
       SPV_IO_MakeTexelAvailable, SPV_IO_MakeTexelVisible, SPV_IO_NonPrivateTexel,
-      SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend
+      SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend,
+      SPV_IO_Nontemporal
     ]>;
 
 def SPV_LT_Export      : I32EnumAttrCase<"Export", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Linkage]>
   ];
 }
 def SPV_LT_Import      : I32EnumAttrCase<"Import", 1> {
def SPV_MA_MakePointerVisible   : I32BitEnumAttrCaseBit<"MakePointerVisible", 4> {
   ];
 }
 def SPV_MA_NonPrivatePointer    : I32BitEnumAttrCaseBit<"NonPrivatePointer", 5> {
   list<Availability> availability = [
     MinVersion<SPV_V_1_5>,
     Capability<[SPV_C_VulkanMemoryModel]>
   ];
 }
+def SPV_MA_AliasScopeINTELMask  : I32BitEnumAttrCaseBit<"AliasScopeINTELMask", 16> {
+  list<Availability> availability = [
+    Extension<[SPV_INTEL_memory_access_aliasing]>,
+    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+  ];
+}
+def SPV_MA_NoAliasINTELMask     : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> {
+  list<Availability> availability = [
+    Extension<[SPV_INTEL_memory_access_aliasing]>,
+    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+  ];
+}
 
 def SPV_MemoryAccessAttr :
     SPV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", [
       SPV_MA_None, SPV_MA_Volatile, SPV_MA_Aligned, SPV_MA_Nontemporal,
       SPV_MA_MakePointerAvailable, SPV_MA_MakePointerVisible,
-      SPV_MA_NonPrivatePointer
+      SPV_MA_NonPrivatePointer, SPV_MA_AliasScopeINTELMask, SPV_MA_NoAliasINTELMask
     ]>;
 
 def SPV_MM_Simple  : I32EnumAttrCase<"Simple", 0> {
   list<Availability> availability = [
     Capability<[SPV_C_Shader]>
   ];
 }
 def SPV_MM_GLSL450 : I32EnumAttrCase<"GLSL450", 1> {
Op<SPIRV_Dialect, mnemonic, !listconcat(traits, [
          DeclareOpInterfaceMethods<QueryMinVersionInterface>,
          DeclareOpInterfaceMethods<QueryMaxVersionInterface>,
          DeclareOpInterfaceMethods<QueryExtensionInterface>,
          DeclareOpInterfaceMethods<QueryCapabilityInterface>
        ])> {
   // Availability specification for this op itself.
   list<Availability> availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[]>
   ];
 
   // For each SPIR-V op, the following static functions need to be defined
   // in SPVOps.cpp:
   //
   // * ParseResult <op-c++-class-name>::parse(OpAsmParser &parser,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td

let description = [{
 
     ```mlir
     %0 = spv.BitFieldInsert %base, %insert, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
   ];
 
   let arguments = (ins
     SPV_ScalarOrVectorOf<SPV_Integer>:$base,
     SPV_ScalarOrVectorOf<SPV_Integer>:$insert,
     SPV_Integer:$offset,
     SPV_Integer:$count
   );
let description = [{
 
     ```mlir
     %0 = spv.BitFieldSExtract %base, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
   ];
 }
 
 // -----
 
 def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract",
                                                    [UnsignedOp]> {
   let summary = "Extract a bit field from an object, without sign extension.";
let description = [{
 
     ```mlir
     %0 = spv.BitFieldUExtract %base, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
   ];
 }
 
 // -----
 
 def SPV_BitReverseOp : SPV_BitUnaryOp<"BitReverse", []> {
   let summary = "Reverse the bits in an object.";
 
let description = [{
     ```mlir
     %2 = spv.BitReverse %0 : i32
     %3 = spv.BitReverse %1 : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
   ];
 }
 
 // -----
 
 def SPV_BitwiseAndOp : SPV_BitBinaryOp<"BitwiseAnd",
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = [{

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td

def SPV_ReturnOp : SPV_Op<"Return", [InFunctionScope, NoSideEffect,
   let results = (outs);
 
   let assemblyFormat = "attr-dict";
 }
 
 // -----
 
 def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> {
-  let summary = "Declares that this block is not reachable in the CFG.";
+  let summary = "Behavior is undefined if this instruction is executed.";
 
   let description = [{
     This instruction must be the last instruction in a block.
 
     <!-- End of AutoGen section -->
 
     ```
     unreachable-op ::= `spv.Unreachable`

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td

let description = [{
     %0 = spv.CooperativeMatrixLengthNV : !spv.coopmatrix<Subgroup, i32, 8, 16>
     ```
   }];
 
   let assemblyFormat = "attr-dict `:` $type";
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_NV_cooperative_matrix]>,
     Capability<[SPV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
     TypeAttr:$type
   );
 
let description = [{
     ```
     %0 = spv.CooperativeMatrixLoadNV %ptr, %stride, %colMajor
          : !spv.ptr<i32, StorageBuffer> as !spv.coopmatrix<i32, Workgroup, 16, 8>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_NV_cooperative_matrix]>,
     Capability<[SPV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$pointer,
     SPV_Integer:$stride,
     SPV_Bool:$columnmajor,
def SPV_CooperativeMatrixMulAddNVOp : SPV_Op<"CooperativeMatrixMulAddNV",
   }];
 
   let assemblyFormat = [{
     operands attr-dict`:` type($a) `,` type($b) `->` type($c)
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_NV_cooperative_matrix]>,
     Capability<[SPV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
     SPV_AnyCooperativeMatrix:$a,
     SPV_AnyCooperativeMatrix:$b,
     SPV_AnyCooperativeMatrix:$c
let description = [{
     ```
       spv.CooperativeMatrixStoreNV %arg0, %arg2, %arg1, %arg3 :
         !spv.ptr<i32, StorageBuffer>, !spv.coopmatrix<Workgroup, i32, 16, 8>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_NV_cooperative_matrix]>,
     Capability<[SPV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$pointer,
     SPV_AnyCooperativeMatrix:$object,
     SPV_Integer:$stride,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

let description = [{
     %0 = spv.GroupBroadcast "Subgroup" %scalar_value, %scalar_localid : f32, i32
     %1 = spv.GroupBroadcast "Workgroup" %vector_value, %vector_localid :
       vector<4xf32>, vector<3xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Groups]>
   ];
 
   let arguments = (ins
     SPV_ScopeAttr:$execution_scope,
     SPV_Type:$value,
     SPV_ScalarOrVectorOf<SPV_Integer>:$localid
let description = [{
 
     ```mlir
     %0 = spv.SubgroupBallotKHR %predicate : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_KHR_shader_ballot]>,
     Capability<[SPV_C_SubgroupBallotKHR]>
   ];
 
   let arguments = (ins
     SPV_Bool:$predicate
   );
 
let description = [{
 
     ```
     %0 = spv.SubgroupBlockReadINTEL "StorageBuffer" %ptr : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_INTEL_subgroups]>,
     Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$ptr
   );
 
let description = [{
 
     ```
     spv.SubgroupBlockWriteINTEL "StorageBuffer" %ptr, %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_INTEL_subgroups]>,
     Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$ptr,
     SPV_Type:$value
   );
 
   let results = (outs);
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_GROUP_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td

let description = [{
     ```mlir
     %0 = spv.ImageDrefGather %1 : !spv.sampled_image<!spv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown>>, %2 : vector<4xf32>, %3 : f32 -> vector<4xi32>
     %0 = spv.ImageDrefGather %1 : !spv.sampled_image<!spv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown>>, %2 : vector<4xf32>, %3 : f32 ["NonPrivateTexel"] : f32, f32 -> vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Shader]>
   ];
 
   let arguments = (ins
     SPV_AnySampledImage:$sampledimage,
     SPV_ScalarOrVectorOf<SPV_Float>:$coordinate,
     SPV_Float:$dref,
let description = [{
     %4 = spv.ImageQuerySize %1 : !spv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown> -> vector<2xi32>
     %5 = spv.ImageQuerySize %2 : !spv.image<i32, Dim2D, NoDepth, Arrayed, SingleSampled, NoSampler, Unknown> -> vector<3xi32>
     ```
 
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_ImageQuery, SPV_C_Kernel]>
   ];
 
   let arguments = (ins
     SPV_AnyImage:$image
   );
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td

let description = [{
     ```
     %4 = spv.Ordered %0, %1 : f32
     %5 = spv.Ordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Kernel]>
   ];
 }
 
 // -----
 
 def SPV_SGreaterThanOp : SPV_LogicalBinaryOp<"SGreaterThan",
let description = [{
     ```
     %4 = spv.Unordered %0, %1 : f32
     %5 = spv.Unordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Kernel]>
   ];
 }
 
 // -----
 
 def SPV_ULessThanEqualOp : SPV_LogicalBinaryOp<"ULessThanEqual",

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td

let description = [{
     %0 = spv.MatrixTimesMatrix %matrix_1, %matrix_2 :
         !spv.matrix<4 x vector<3xf32>>, !spv.matrix<3 x vector<4xf32>> ->
         !spv.matrix<4 x vector<4xf32>>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Matrix]>
   ];
 
   let arguments = (ins
     SPV_AnyMatrix:$leftmatrix,
     SPV_AnyMatrix:$rightmatrix
   );
let description = [{
     %0 = spv.MatrixTimesScalar %matrix, %scalar :
     !spv.matrix<3 x vector<3xf32>>, f32 -> !spv.matrix<3 x vector<3xf32>>
 
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Matrix]>
   ];
 
   let arguments = (ins
     SPV_AnyMatrix:$matrix,
     SPV_Float:$scalar
   );
let description = [{
     %0 = spv.Transpose %matrix: !spv.matrix<2 x vector<3xf32>> ->
     !spv.matrix<3 x vector<2xf32>>
 
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Matrix]>
   ];
 
   let arguments = (ins
     SPV_AnyMatrix:$matrix
   );
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td

 #ifndef MLIR_DIALECT_SPIRV_IR_MEMORY_OPS
 #define MLIR_DIALECT_SPIRV_IR_MEMORY_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 // -----
 
 def SPV_AccessChainOp : SPV_Op<"AccessChain", [NoSideEffect]> {
-  let summary = [{
-    Create a pointer into a composite object that can be used with OpLoad
-    and OpStore.
-  }];
+  let summary = "Create a pointer into a composite object.";
 
   let description = [{
     Result Type must be an OpTypePointer. Its Type operand must be the type
     reached by walking the Base’s type hierarchy down to the last provided
     index in Indexes, and its Storage Class operand must be the same as the
     Storage Class of Base.
 
     Base must be a pointer, pointing to the base of a composite object.
func @inbounds_ptr_access_chain(%arg0: !spv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spv.InBoundsPtrAccessChain %arg0[%arg1] : !spv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Addresses]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$base_ptr,
     SPV_Integer:$element,
     Variadic<SPV_Integer>:$indices
func @ptr_access_chain(%arg0: !spv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spv.PtrAccessChain %arg0[%arg1] : !spv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_Addresses, SPV_C_PhysicalStorageBufferAddresses, SPV_C_VariablePointers, SPV_C_VariablePointersStorageBuffer]>
   ];
 
   let arguments = (ins
     SPV_AnyPtr:$base_ptr,
     SPV_Integer:$element,
     Variadic<SPV_Integer>:$indices

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td

let description = [{
 
     ```
     spv.AssumeTrueKHR %arg
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[SPV_KHR_expect_assume]>,
     Capability<[SPV_C_ExpectAssumeKHR]>
   ];
 
   let arguments = (ins
     SPV_Bool:$condition
   );
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

let description = [{
 
     ```mlir
     %0 = spv.GroupNonUniformBallot "SubGroup" %predicate : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformBallot]>
   ];
 
   let arguments = (ins
     SPV_ScopeAttr:$execution_scope,
     SPV_Bool:$predicate
   );
let description = [{
     %0 = spv.GroupNonUniformBroadcast "Subgroup" %scalar_value, %id : f32, i32
     %1 = spv.GroupNonUniformBroadcast "Workgroup" %vector_value, %id :
       vector<4xf32>, i32
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformBallot]>
   ];
 
   let arguments = (ins
     SPV_ScopeAttr:$execution_scope,
     SPV_Type:$value,
     SPV_Integer:$id
let description = [{
 
     ```mlir
     %0 = spv.GroupNonUniformElect : i1
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniform]>
   ];
 
   let arguments = (ins
     SPV_ScopeAttr:$execution_scope
   );
 
let description = [{
     %vector = ... : vector<4xf32>
     %0 = spv.GroupNonUniformFAdd "Workgroup" "Reduce" %scalar : f32
     %1 = spv.GroupNonUniformFAdd "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformFMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMax", SPV_Float, []> {
let description = [{
     %vector = ... : vector<4xf32>
     %0 = spv.GroupNonUniformFMax "Workgroup" "Reduce" %scalar : f32
     %1 = spv.GroupNonUniformFMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformFMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMin", SPV_Float, []> {
let description = [{
     %vector = ... : vector<4xf32>
     %0 = spv.GroupNonUniformFMin "Workgroup" "Reduce" %scalar : f32
     %1 = spv.GroupNonUniformFMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformFMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMul", SPV_Float, []> {
let description = [{
     %vector = ... : vector<4xf32>
     %0 = spv.GroupNonUniformFMul "Workgroup" "Reduce" %scalar : f32
     %1 = spv.GroupNonUniformFMul "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformIAddOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformIAdd", SPV_Integer, []> {
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformIAdd "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformIAdd "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformIMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformIMul", SPV_Integer, []> {
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformIMul "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformIMul "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformSMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformSMax",
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformSMax "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformSMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformSMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformSMin",
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformSMin "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformSMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformUMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformUMax",
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformUMax "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformUMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 def SPV_GroupNonUniformUMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformUMin",
let description = [{
     %vector = ... : vector<4xi32>
     %0 = spv.GroupNonUniformUMin "Workgroup" "Reduce" %scalar : i32
     %1 = spv.GroupNonUniformUMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
     MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_5>,
+    MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_NON_UNIFORM_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td

 }
 
 // -----
 
 def SPV_ConstantOp : SPV_Op<"Constant",
     [ConstantLike,
      DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
      NoSideEffect]> {
-  let summary = "The op that declares a SPIR-V normal constant";
+  let summary = [{
+    Declare a new integer-type or floating-point-type scalar constant.
+  }];
 
   let description = [{
     This op declares a SPIR-V normal constant. SPIR-V has multiple constant
     instructions covering different constant types:
 
     * `OpConstantTrue` and `OpConstantFalse` for boolean constants
     * `OpConstant` for scalar constants
     * `OpConstantComposite` for composite constants
def SPV_ReferenceOfOp : SPV_Op<"mlir.referenceof", [NoSideEffect]> {
   let autogenSerialization = 0;
 
   let assemblyFormat = "$spec_const attr-dict `:` type($reference)";
 }
 
 // -----
 
 def SPV_SpecConstantOp : SPV_Op<"SpecConstant", [InModuleScope, Symbol]> {
-  let summary = "The op that declares a SPIR-V specialization constant";
+  let summary = [{
+    Declare a new integer-type or floating-point-type scalar specialization
+    constant.
+  }];
 
   let description = [{
     This op declares a SPIR-V scalar specialization constant. SPIR-V has
     multiple constant instructions covering different scalar types:
 
     * `OpSpecConstantTrue` and `OpSpecConstantFalse` for boolean constants
     * `OpSpecConstant` for scalar constants
 

mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp

case spirv::Version::V_1_##v:                                                \
     break
 
     MIN_VERSION_CASE(0);
     MIN_VERSION_CASE(1);
     MIN_VERSION_CASE(2);
     MIN_VERSION_CASE(3);
     MIN_VERSION_CASE(4);
     MIN_VERSION_CASE(5);
+    MIN_VERSION_CASE(6);
 #undef MIN_VERSION_CASE
   }
 
   // See "2.3. Physical Layout of a SPIR-V Module and Instruction" in the SPIR-V
   // spec for the definition of the binary module header.
   //
   // The first five words of a SPIR-V module must be:
   // +-------------------------------------------------------------------------+

mlir/test/Dialect/SPIRV/IR/availability.mlir

 // RUN: mlir-opt -mlir-disable-threading -test-spirv-op-availability %s | FileCheck %s
 
 // CHECK-LABEL: iadd
 func.func @iadd(%arg: i32) -> i32 {
   // CHECK: min version: v1.0
-  // CHECK: max version: v1.5
+  // CHECK: max version: v1.6
   // CHECK: extensions: [ ]
   // CHECK: capabilities: [ ]
   %0 = spv.IAdd %arg, %arg: i32
   return %0: i32
 }
 
 // CHECK: atomic_compare_exchange_weak
 func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
   // CHECK: min version: v1.0
   // CHECK: max version: v1.3
   // CHECK: extensions: [ ]
   // CHECK: capabilities: [ [Kernel] ]
   %0 = spv.AtomicCompareExchangeWeak "Workgroup" "Release" "Acquire" %ptr, %value, %comparator: !spv.ptr<i32, Workgroup>
   return %0: i32
 }
 
 // CHECK-LABEL: subgroup_ballot
 func.func @subgroup_ballot(%predicate: i1) -> vector<4xi32> {
   // CHECK: min version: v1.3
-  // CHECK: max version: v1.5
+  // CHECK: max version: v1.6
   // CHECK: extensions: [ ]
   // CHECK: capabilities: [ [GroupNonUniformBallot] ]
   %0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: module_logical_glsl450
 func.func @module_logical_glsl450() {
   // CHECK: spv.module min version: v1.0
-  // CHECK: spv.module max version: v1.5
+  // CHECK: spv.module max version: v1.6
   // CHECK: spv.module extensions: [ ]
   // CHECK: spv.module capabilities: [ [Shader] ]
   spv.module Logical GLSL450 { }
   return
 }
 
 // CHECK-LABEL: module_physical_storage_buffer64_vulkan
 func.func @module_physical_storage_buffer64_vulkan() {
   // CHECK: spv.module min version: v1.0
-  // CHECK: spv.module max version: v1.5
+  // CHECK: spv.module max version: v1.6
   // CHECK: spv.module extensions: [ [SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer] [SPV_KHR_vulkan_memory_model] ]
   // CHECK: spv.module capabilities: [ [PhysicalStorageBufferAddresses] [VulkanMemoryModel] ]
   spv.module PhysicalStorageBuffer64 Vulkan { }
   return
 }

mlir/utils/spirv/gen_spirv_dialect.py

 #
 # ./gen_spirv_dialect.py --base-td-path /path/to/SPIRVBase.td \
 #                        --new-enum MemoryModel
 #
 # The 'operand_kinds' dict of spirv.core.grammar.json contains all supported
 # SPIR-V enum classes.
 
 import itertools
+import math
 import re
 import requests
 import textwrap
 import yaml
 
 SPIRV_HTML_SPEC_URL = 'https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html'
 SPIRV_JSON_SPEC_URL = 'https://raw.githubusercontent.com/KhronosGroup/SPIRV-Headers/master/include/spirv/unified1/spirv.core.grammar.json'
 
def get_availability_spec(enum_case, capability_mapping, for_op, for_cap):
 
   Returns:
     - A `let availability = [...];` string if with availability spec or
       empty string if without availability spec
   """
   assert not (for_op and for_cap), 'cannot set both for_op and for_cap'
 
   DEFAULT_MIN_VERSION = 'MinVersion<SPV_V_1_0>'
-  DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_5>'
+  DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_6>'
   DEFAULT_CAP = 'Capability<[]>'
   DEFAULT_EXT = 'Extension<[]>'
 
   min_version = enum_case.get('version', '')
   if min_version == 'None':
     min_version = ''
   elif min_version:
     min_version = 'MinVersion<SPV_V_{}>'.format(min_version.replace('.', '_'))
def gen_operand_kind_enum_attr(operand_kind, capability_mapping):
   def get_case_symbol(kind_name, case_name):
     if kind_name == 'Dim':
       if case_name == '1D' or case_name == '2D' or case_name == '3D':
         return 'Dim{}'.format(case_name)
     return case_name
 
   kind_name = operand_kind['kind']
   is_bit_enum = operand_kind['category'] == 'BitEnum'
-  kind_category = 'Bit' if is_bit_enum else 'I32'
   kind_acronym = ''.join([c for c in kind_name if c >= 'A' and c <= 'Z'])
 
   name_to_case_dict = {}
   for case in operand_kind['enumerants']:
     name_to_case_dict[case['enumerant']] = case
 
   if kind_name == 'Capability':
     # Special treatment for capability cases: we need to sort them topologically
     # because a capability can refer to another via the 'implies' field.
     kind_cases = toposort_capabilities(operand_kind['enumerants'],
                                        capability_mapping)
   else:
     kind_cases = [(case['enumerant'], case['value'])
                   for case in operand_kind['enumerants']]
     kind_cases, _ = uniquify_enum_cases(kind_cases)
   max_len = max([len(symbol) for (symbol, _) in kind_cases])
 
   # Generate the definition for each enum case
-  fmt_str = 'def SPV_{acronym}_{case} {colon:>{offset}} '\
-            '{category}EnumAttrCase<"{symbol}", {value}>{avail}'
+  case_category = 'I32Bit' if is_bit_enum else 'I32'
+  fmt_str = 'def SPV_{acronym}_{case_name} {colon:>{offset}} '\
+            '{category}EnumAttrCase{suffix}<"{symbol}"{case_value_part}>{avail}'
   case_defs = []
-  for case in kind_cases:
-    avail = get_availability_spec(name_to_case_dict[case[0]],
+  for case_pair in kind_cases:
+    name = case_pair[0]
+    if is_bit_enum:
+      value = int(case_pair[1], base=16)
+    else:
+      value = int(case_pair[1])
+    avail = get_availability_spec(name_to_case_dict[name],
                                   capability_mapping,
                                   False, kind_name == 'Capability')
+    if is_bit_enum:
+      if value == 0:
+        suffix = 'None'
+        value = ''
+      else:
+        suffix = "Bit"
+        value = ', {}'.format(int(math.log2(value)))
+    else:
+        suffix = ''
+        value = ', {}'.format(value)
+
     case_def = fmt_str.format(
-        category=kind_category,
+        category=case_category,
+        suffix=suffix,
         acronym=kind_acronym,
-        case=case[0],
-        symbol=get_case_symbol(kind_name, case[0]),
-        value=case[1],
+        case_name=name,
+        symbol=get_case_symbol(kind_name, name),
+        case_value_part=value,
         avail=' {{\n  {}\n}}'.format(avail) if avail else ';',
         colon=':',
-        offset=(max_len + 1 - len(case[0])))
+        offset=(max_len + 1 - len(name)))
     case_defs.append(case_def)
   case_defs = '\n'.join(case_defs)
 
   # Generate the list of enum case names
   fmt_str = 'SPV_{acronym}_{symbol}';
   case_names = [fmt_str.format(acronym=kind_acronym,symbol=case[0])
                 for case in kind_cases]
 
   # Split them into sublists and concatenate into multiple lines
   case_names = split_list_into_sublists(case_names)
   case_names = ['{:6}'.format('') + ', '.join(sublist)
                 for sublist in case_names]
   case_names = ',\n'.join(case_names)
 
   # Generate the enum attribute definition
+  kind_category = 'Bit' if is_bit_enum else 'I32'
   enum_attr = '''def SPV_{name}Attr :
     SPV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", [
 {cases}
     ]>;'''.format(
           name=kind_name, category=kind_category, cases=case_names)
   return kind_name, case_defs + '\n\n' + enum_attr
 
 

mlir/utils/spirv/refresh_inst.sh

+#!/bin/bash
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+# Script for refreshing all defined SPIR-V ops using SPIR-V spec from the
+# Internet.
+#
+# Run as:
+# ./refresh_inst.sh
+
+current_file="$(readlink -f "$0")"
+current_dir="$(dirname "$current_file")"
+
+spirv_ir_include_dir="${current_dir}/../../include/mlir/Dialect/SPIRV/IR/"
+
+for file in "${spirv_ir_include_dir}"/*; do
+  file_name="$(basename $file)"
+  if [[ $file_name == "SPIRVOps.td" ||
+        $file_name == "SPIRVCLOps.td" ||
+        $file_name == "SPIRVGLOps.td" ]]; then
+    continue
+  fi
+  if [[ $file_name =~ SPIRV.*Ops.td ]]; then
+    echo "--- refreshing $file_name ---"
+    "${current_dir}/define_inst.sh" ${file_name} Op
+  fi
+done
+