[SDAG] Add test for DAGCombiner multiple result commutative CSE

[ibookstein]

Summary

This commit adds a test for DAGCombiner commutative CSE on
nodes with multiple results (UMUL_LOHI). In this commit it
asserts the lack of CSE, a later commit will demonstrate
the CSE in the changed assertions.

Signed-off-by: Itay Bookstein <[e-mail]>

[barannikov88]

Checked locally, there are indeed UMUL_LOHI nodes which haven't been CSEd, so LGTM.
I'm wondering how you came up with this...

[ibookstein]

Something very similar to the use-case demonstrated in the test: the computation of the high part of a 64x64->128 squaring emitted four 32-bit multiplications rather than three, on a 32-bit arch.

llvm/test/CodeGen/X86/dagcombine-cse.ll

entry:
   %tmp35 = insertelement <2 x double> undef, double %tmp3454, i32 0    ; <<2 x double>> [#uses=1]
   %tmp36 = insertelement <2 x double> %tmp35, double 0.000000e+00, i32 1    ; <<2 x double>> [#uses=1]
   %tmp42 = bitcast <2 x double> %tmp36 to <8 x i16>    ; <<8 x i16>> [#uses=1]
   %tmp43 = shufflevector <8 x i16> %tmp42, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 1, i32 2, i32 4, i32 5, i32 6, i32 7 >    ; <<8 x i16>> [#uses=1]
   %tmp47 = bitcast <8 x i16> %tmp43 to <4 x i32>    ; <<4 x i32>> [#uses=1]
   %tmp48 = extractelement <4 x i32> %tmp47, i32 0    ; <i32> [#uses=1]
   ret i32 %tmp48
 }
+
+; Test CSE for SDAG nodes with multiple results (UMUL_LOHI).
+; Pre-committed before fix, so this does not demonstrate CSE yet.
+define i96 @square_high(i96 %x) nounwind {
+; X86-LABEL: square_high:
+; X86:       ## %bb.0: ## %entry
+; X86-NEXT:    pushl %ebp
+; X86-NEXT:    pushl %ebx
+; X86-NEXT:    pushl %edi
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    subl $12, %esp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    mull {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %edx, %ecx
+; X86-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    mull %ebp
+; X86-NEXT:    movl %eax, %edi
+; X86-NEXT:    addl %ecx, %eax
+; X86-NEXT:    movl %edx, %eax
+; X86-NEXT:    movl %edx, %esi
+; X86-NEXT:    adcl $0, %eax
+; X86-NEXT:    setb %bl
+; X86-NEXT:    xorl %eax, %eax
+; X86-NEXT:    mull %ebp
+; X86-NEXT:    addl %ecx, %edi
+; X86-NEXT:    adcl %eax, %esi
+; X86-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
+; X86-NEXT:    movzbl %bl, %ecx
+; X86-NEXT:    adcl %edx, %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    movl %esi, %eax
+; X86-NEXT:    mull %esi
+; X86-NEXT:    movl %esi, %ebx
+; X86-NEXT:    movl %edx, (%esp) ## 4-byte Spill
+; X86-NEXT:    movl %ebp, %esi
+; X86-NEXT:    movl %ebp, %eax
+; X86-NEXT:    mull %ebx
+; X86-NEXT:    movl %edx, %ebp
+; X86-NEXT:    movl %eax, %ebx
+; X86-NEXT:    addl (%esp), %ebx ## 4-byte Folded Reload
+; X86-NEXT:    adcl $0, %ebp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    mull %esi
+; X86-NEXT:    movl %edx, %esi
+; X86-NEXT:    addl %ebx, %eax
+; X86-NEXT:    adcl %ebp, %esi
+; X86-NEXT:    setb %bl
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    mull %eax
+; X86-NEXT:    movl %eax, %ebp
+; X86-NEXT:    addl %esi, %ebp
+; X86-NEXT:    movzbl %bl, %esi
+; X86-NEXT:    adcl %edx, %esi
+; X86-NEXT:    addl {{[-0-9]+}}(%e{{[sb]}}p), %ebp ## 4-byte Folded Reload
+; X86-NEXT:    adcl %edi, %esi
+; X86-NEXT:    adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
+; X86-NEXT:    adcl $0, %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT:    mull %edi
+; X86-NEXT:    movl %edx, (%esp) ## 4-byte Spill
+; X86-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    mull %edi
+; X86-NEXT:    movl %edx, %edi
+; X86-NEXT:    movl %eax, %ebx
+; X86-NEXT:    addl (%esp), %ebx ## 4-byte Folded Reload
+; X86-NEXT:    adcl $0, %edi
+; X86-NEXT:    addl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
+; X86-NEXT:    adcl %esi, %ebx
+; X86-NEXT:    adcl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Folded Reload
+; X86-NEXT:    adcl $0, %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    mull %eax
+; X86-NEXT:    addl %eax, %edi
+; X86-NEXT:    adcl %edx, %ecx
+; X86-NEXT:    movl %ebx, %eax
+; X86-NEXT:    movl %edi, %edx
+; X86-NEXT:    addl $12, %esp
+; X86-NEXT:    popl %esi
+; X86-NEXT:    popl %edi
+; X86-NEXT:    popl %ebx
+; X86-NEXT:    popl %ebp
+; X86-NEXT:    retl
+;
+; X64-LABEL: square_high:
+; X64:       ## %bb.0: ## %entry
+; X64-NEXT:    movl %esi, %ecx
+; X64-NEXT:    movq %rcx, %rax
+; X64-NEXT:    mulq %rdi
+; X64-NEXT:    movq %rdx, %r8
+; X64-NEXT:    movq %rax, %rsi
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    mulq %rdi
+; X64-NEXT:    addq %rdx, %rsi
+; X64-NEXT:    adcq $0, %r8
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    mulq %rcx
+; X64-NEXT:    addq %rsi, %rax
+; X64-NEXT:    adcq %r8, %rdx
+; X64-NEXT:    imulq %rcx, %rcx
+; X64-NEXT:    addq %rcx, %rdx
+; X64-NEXT:    shrdq $32, %rdx, %rax
+; X64-NEXT:    shrq $32, %rdx
+; X64-NEXT:    retq
+entry:
+  %conv = zext i96 %x to i192
+  %mul = mul nuw i192 %conv, %conv
+  %shr = lshr i192 %mul, 96
+  %conv2 = trunc i192 %shr to i96
+  ret i96 %conv2
+}