[DAG] PromoteIntRes_BUILD_VECTOR - extend constant boolean vectors according to target BooleanContents

[RKSimon]

Summary

PromoteIntRes_BUILD_VECTOR currently always ANY_EXTENDs build vector operands, but if this is a constant boolean vector we're losing the useful ability to keep the vector matching the BooleanContents mode used by the target.

This patch extends constant boolean vectors according to target BooleanContents, allowing a number of additional all-bits folds (notable XOR -> NOT conversions) to occur.

[RKSimon]

llvm/test/CodeGen/PowerPC/vec-select.ll

56

@nemanjai Please can you confirm if you intended to avoid the XXSEL pattern because <i1 -1, i1 -1, i1 -1, i1 -1> would extend to <i32 1, i32 1, i32 1, i32 1> or some other reason?

[RKSimon]

rebase after rGd172842b5100926cc882617a1874afc09f5fbaaf

[RKSimon]

llvm/test/CodeGen/PowerPC/vec-select.ll

56

@shchenz I'm not sure if @nemanjai is around, do you happen to know any background to this please?

[shchenz]

llvm/test/CodeGen/PowerPC/vec-select.ll

56

To me, this looks like improvement for 4 x i1 type. We cannot guarantee the higher 31 bits even before this patch.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

5315

Please fix this comment to make it clear this is a heuristic; there isn't any semantic requirement that the high bits match getBooleanContents() here.

[RKSimon]

Adjust comment to make it clear that the extension isn't necessary, just useful for further folds.

[RKSimon]

any more comments?

[efriedma]

LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 
 
 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   assert(NOutVT.isVector() && "This type must be promoted to a vector type");
   unsigned NumElems = N->getNumOperands();
   EVT NOutVTElem = NOutVT.getVectorElementType();
-
+  TargetLoweringBase::BooleanContent NOutBoolType = TLI.getBooleanContents(NOutVT);
+  unsigned NOutExtOpc = TargetLowering::getExtendForContent(NOutBoolType);
   SDLoc dl(N);
 
   SmallVector<SDValue, 8> Ops;
   Ops.reserve(NumElems);
   for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Op;
+    SDValue Op = N->getOperand(i);
+    EVT OpVT = Op.getValueType();
     // BUILD_VECTOR integer operand types are allowed to be larger than the
     // result's element type. This may still be true after the promotion. For
     // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
     // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
-    if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
-      Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
-    else
-      Op = N->getOperand(i);
+    if (OpVT.bitsLT(NOutVTElem)) {
+      unsigned ExtOpc = ISD::ANY_EXTEND;
+      // Attempt to extend constant bool vectors to match target's BooleanContent.
+      // While not necessary, this improves chances of the constant correctly
+      // folding with compare results (e.g. for NOT patterns).
+      if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant)
+        ExtOpc = NOutExtOpc;
+      Op = DAG.getNode(ExtOpc, dl, NOutVTElem, Op);
+    }
     Ops.push_back(Op);
   }
 
   return DAG.getBuildVector(NOutVT, dl, Ops);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_ScalarOp(SDNode *N) {
 

llvm/test/CodeGen/AArch64/arm64-vshuffle.ll

%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
                                    i1 7>,
                          <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
                                    i1 7>,
                          <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
                                     i32 12, i32 14, i32 0>
   ret <8 x i1> %Shuff
 }
 
-; CHECK-LABEL: lCPI1_0:
-; CHECK:          .byte   0                       ; 0x0
-; CHECK:          .space  1
-; CHECK:          .byte   0                       ; 0x0
-; CHECK:          .space  1
-; CHECK:          .byte   1                       ; 0x1
-; CHECK:          .byte   0                       ; 0x0
-; CHECK:          .byte   0                       ; 0x0
-; CHECK:          .byte   0                       ; 0x0
 define <8 x i1>@test2() {
-; CHECK-LABEL: test2
-; CHECK: adrp    x[[REG2:[0-9]+]], lCPI1_0@PAGE
-; CHECK: ldr     d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
+; CHECK-LABEL: test2:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    movi d0, #0x0000ff00000000
+; CHECK-NEXT:    ret
 bb:
   %Shuff = shufflevector <8 x i1> zeroinitializer,
      <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
      <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
                 i32 0>
   ret <8 x i1> %Shuff
 }
 
 define <16 x i1> @test3(i1* %ptr, i32 %v) {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    movi.4s v0, #1
+; CHECK-NEXT:    movi.2d v0, #0x0000ff000000ff
 ; CHECK-NEXT:    ret
 bb:
   %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
      <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
                  i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
                  i32 14, i32 0>
   ret <16 x i1> %Shuff
 }
 ; CHECK-LABEL: lCPI3_0:
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
-; CHECK:         .byte   1                       ; 0x1
+; CHECK:         .byte   255                     ; 0xff
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0

llvm/test/CodeGen/ARM/select_xform.ll

 }
 
 define  <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {
 ; CHECK-LABEL: t21:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov d16, r2, r3
 ; CHECK-NEXT:    vmov d17, r0, r1
 ; CHECK-NEXT:    vceq.i32 d16, d17, d16
-; CHECK-NEXT:    vmov.i32 d17, #0x1
-; CHECK-NEXT:    veor d16, d16, d17
+; CHECK-NEXT:    vmvn d16, d16
 ; CHECK-NEXT:    vshl.i32 d16, d16, #31
 ; CHECK-NEXT:    vshr.s32 d16, d16, #31
 ; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    bx lr
   %tst = icmp eq <2 x i32> %lhs, %rhs
   %ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>
   %btst = sext <2 x i1> %ntst to <2 x i32>
   ret <2 x i32> %btst
 }

llvm/test/CodeGen/PowerPC/pr25080.ll

 ; LE-NEXT:    mtvsrd 32, 3
 ; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; LE-NEXT:    vmrghh 4, 1, 4
 ; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
 ; LE-NEXT:    vmrghh 3, 3, 6
 ; LE-NEXT:    lxvd2x 2, 0, 3
 ; LE-NEXT:    vmrghh 5, 0, 5
 ; LE-NEXT:    xxmrglw 0, 36, 34
-; LE-NEXT:    vspltish 4, 15
 ; LE-NEXT:    xxmrglw 1, 37, 35
 ; LE-NEXT:    xxswapd 35, 2
 ; LE-NEXT:    xxmrgld 34, 1, 0
 ; LE-NEXT:    xxlor 34, 34, 35
-; LE-NEXT:    vslh 2, 2, 4
-; LE-NEXT:    vsrah 2, 2, 4
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: pr25080:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; BE-NEXT:    xxlxor 36, 36, 36
 ; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; BE-NEXT:    lxvw4x 0, 0, 3

 ; BE-NEXT:    mtvsrwz 32, 3
 ; BE-NEXT:    addis 3, 2, .LCPI0_2@toc@ha
 ; BE-NEXT:    vperm 4, 6, 4, 1
 ; BE-NEXT:    addi 3, 3, .LCPI0_2@toc@l
 ; BE-NEXT:    vperm 5, 5, 7, 1
 ; BE-NEXT:    vperm 3, 0, 3, 1
 ; BE-NEXT:    xxmrghw 0, 36, 34
 ; BE-NEXT:    xxmrghw 1, 35, 37
-; BE-NEXT:    vspltish 3, 15
 ; BE-NEXT:    xxmrghd 34, 1, 0
 ; BE-NEXT:    lxvw4x 0, 0, 3
 ; BE-NEXT:    xxlor 34, 34, 0
-; BE-NEXT:    vslh 2, 2, 3
-; BE-NEXT:    vsrah 2, 2, 3
 ; BE-NEXT:    blr
 entry:
   %0 = trunc <8 x i32> %a to <8 x i23>
   %1 = icmp eq <8 x i23> %0, zeroinitializer
   %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
   %3 = sext <8 x i1> %2 to <8 x i16>
   ret <8 x i16> %3
 }

llvm/test/CodeGen/PowerPC/vec-select.ll

 entry:
   %neg.i = xor <2 x i64> %c, <i64 -1, i64 -1>
   %and.i = and <2 x i64> %a, %neg.i
   %and1.i = and <2 x i64> %c, %b
   %or.i = or <2 x i64> %and.i, %and1.i
   ret <2 x i64> %or.i
 }
 
-; Not valid to emit XXSEL for this illegal type.
+; vXi1 constants are sign-extended to preserve XXSEL pattern.
 define dso_local <4 x i1> @test5(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {
 ; CHECK-LABEL: test5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vspltisw v5, 1
-; CHECK-NEXT:    xxland vs0, vs36, vs35
-; CHECK-NEXT:    xxlxor vs1, vs36, vs37
-; CHECK-NEXT:    xxland vs1, vs34, vs1
-; CHECK-NEXT:    xxlor vs34, vs1, vs0
+; CHECK-NEXT:    xxsel vs34, vs34, vs35, vs36
 ; CHECK-NEXT:    blr
 entry:
   %neg.i = xor <4 x i1> %c, <i1 -1, i1 -1, i1 -1, i1 -1>
   %and.i = and <4 x i1> %a, %neg.i
   %and1.i = and <4 x i1> %c, %b
   %or.i = or <4 x i1> %and.i, %and1.i
   ret <4 x i1> %or.i
 }

llvm/test/CodeGen/X86/bitcast-setcc-128.ll

 ; AVX1-NEXT:    orl $-65536, %ecx # imm = 0xFFFF0000
 ; AVX1-NEXT:    movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
 ; AVX1-NEXT:    orq %rcx, %rax
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v16i8_widened_with_ones:
 ; AVX2:       # %bb.0: # %entry
 ; AVX2-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vinserti128 $1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT:    vpsllw $7, %ymm0, %ymm0
+; AVX2-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vpmovmskb %ymm0, %ecx
 ; AVX2-NEXT:    movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
 ; AVX2-NEXT:    orq %rcx, %rax
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512F-LABEL: v16i8_widened_with_ones:
 ; AVX512F:       # %bb.0: # %entry

llvm/test/CodeGen/X86/promote-cmp.ll

 ; SSE2-NEXT:    shufps {{.*#+}} xmm10 = xmm10[0,2],xmm8[0,2]
 ; SSE2-NEXT:    pcmpeqd %xmm9, %xmm6
 ; SSE2-NEXT:    pcmpeqd %xmm7, %xmm4
 ; SSE2-NEXT:    shufps {{.*#+}} xmm4 = xmm4[1,3],xmm6[1,3]
 ; SSE2-NEXT:    andps %xmm10, %xmm4
 ; SSE2-NEXT:    shufps {{.*#+}} xmm5 = xmm5[1,3],xmm8[1,3]
 ; SSE2-NEXT:    orps %xmm4, %xmm5
 ; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
-; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[2,1,3,3]
-; SSE2-NEXT:    psllq $63, %xmm6
-; SSE2-NEXT:    psrad $31, %xmm6
-; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
-; SSE2-NEXT:    pand %xmm6, %xmm1
-; SSE2-NEXT:    pandn %xmm3, %xmm6
-; SSE2-NEXT:    por %xmm6, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm5[0,1,1,3]
-; SSE2-NEXT:    pxor %xmm4, %xmm3
-; SSE2-NEXT:    psllq $63, %xmm3
-; SSE2-NEXT:    psrad $31, %xmm3
-; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE2-NEXT:    pand %xmm3, %xmm0
-; SSE2-NEXT:    pandn %xmm2, %xmm3
-; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pxor %xmm5, %xmm4
+; SSE2-NEXT:    pxor %xmm6, %xmm6
+; SSE2-NEXT:    pcmpgtd %xmm4, %xmm6
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
+; SSE2-NEXT:    pand %xmm4, %xmm0
+; SSE2-NEXT:    pandn %xmm2, %xmm4
+; SSE2-NEXT:    por %xmm4, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm5[2,1,3,3]
+; SSE2-NEXT:    psllq $63, %xmm2
+; SSE2-NEXT:    psrad $31, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE2-NEXT:    pand %xmm2, %xmm1
+; SSE2-NEXT:    pandn %xmm3, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm1
 ; SSE2-NEXT:    retq
 ;
 ; SSE4-LABEL: PR45808:
 ; SSE4:       # %bb.0:
 ; SSE4-NEXT:    movdqa %xmm0, %xmm4
 ; SSE4-NEXT:    movdqa %xmm1, %xmm0
 ; SSE4-NEXT:    pcmpgtq %xmm3, %xmm0
 ; SSE4-NEXT:    movdqa %xmm4, %xmm5
 ; SSE4-NEXT:    pcmpgtq %xmm2, %xmm5
 ; SSE4-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3]
 ; SSE4-NEXT:    pcmpeqd %xmm6, %xmm6
 ; SSE4-NEXT:    pxor %xmm5, %xmm6
 ; SSE4-NEXT:    psllq $63, %xmm0
 ; SSE4-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
-; SSE4-NEXT:    pmovzxdq {{.*#+}} xmm0 = xmm6[0],zero,xmm6[1],zero
-; SSE4-NEXT:    psllq $63, %xmm0
+; SSE4-NEXT:    pmovsxdq %xmm6, %xmm0
 ; SSE4-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
 ; SSE4-NEXT:    movapd %xmm2, %xmm0
 ; SSE4-NEXT:    movapd %xmm3, %xmm1
 ; SSE4-NEXT:    retq
 ;
 ; AVX1-LABEL: PR45808:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2