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Differential D129544

[RISCV][test] Add test of binop followed by extractelement.
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Authored by jacquesguan on Jul 12 2022, 1:12 AM.

Details

Reviewers
spatel
reames
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rG9049c46b9d0e: [RISCV][test] Add test of binop followed by extractelement.

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Unit TestsFailed

TimeTest
60,040 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test

Event Timeline

jacquesguan created this revision.Jul 12 2022, 1:12 AM
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jacquesguan requested review of this revision.Jul 12 2022, 1:12 AM
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jacquesguan added a child revision: D129545: [RISCV] Scalarize binop followed by extractelement..Jul 12 2022, 1:14 AM
frasercrmck added a comment.Jul 12 2022, 1:40 AM

I've only briefly looked at shouldScalarizeBinop but it sounds like it should theoretically work for scalable vectors (barring an initial check against BUILD_VECTOR) - should we add some scalable-vector tests here too while we're at it? I don't know if you're planning on that change in the future but having consistency sounds desirable to me. Or at least we could make it clear this patch adds fixed-vector tests.

jacquesguan updated this revision to Diff 443869.Jul 12 2022, 2:02 AM

Add scalable vector cases.

jacquesguan added a comment.Jul 12 2022, 2:04 AM
In D129544#3644527, @frasercrmck wrote:

I've only briefly looked at shouldScalarizeBinop but it sounds like it should theoretically work for scalable vectors (barring an initial check against BUILD_VECTOR) - should we add some scalable-vector tests here too while we're at it? I don't know if you're planning on that change in the future but having consistency sounds desirable to me. Or at least we could make it clear this patch adds fixed-vector tests.

Thanks for advice, I added scalable cases. And yes, it could work on scalable vectors too, I am doing the next patch which changes the DAGCombiner to enable these combinations for scalable vectors.

Harbormaster completed remote builds in B174820: Diff 443869.Jul 12 2022, 3:40 AM
reames accepted this revision.Jul 12 2022, 9:56 AM

LGTM w/required changes before commit.

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
485

Naming wise, "ext" makes me think "extend" not "extractelement".

I'd suggest extractelt_<type>_<op>_splat.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
653

Meta comment: "1" and "0" are special edge cases for mul and div. Please use a constant which is not an edge case if you're not testing that behavior.

662

Example of previous comment causing less than helpful test output.

This revision is now accepted and ready to land.Jul 12 2022, 9:56 AM
jacquesguan updated this revision to Diff 444156.Jul 12 2022, 11:24 PM

Address comment.

jacquesguan marked 3 inline comments as done.Jul 12 2022, 11:25 PM
jacquesguan added inline comments.
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
485

Done.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
653

Done.

662

Done.

This revision was landed with ongoing or failed builds.Jul 12 2022, 11:54 PM
Closed by commit rG9049c46b9d0e: [RISCV][test] Add test of binop followed by extractelement. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan marked 3 inline comments as done.
jacquesguan added a commit: rG9049c46b9d0e: [RISCV][test] Add test of binop followed by extractelement..
Harbormaster completed remote builds in B175042: Diff 444156.Jul 13 2022, 12:16 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
70 lines
70 lines
85 lines
85 lines
189 lines

Diff 444156

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

Show First 20 Lines • Show All 475 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x double> %v, i32 %idx %r = extractelement <vscale x 8 x double> %v, i32 %idx
ret double %r ret double %r
} }
define float @extractelt_fadd_nxv4f32_splat(<vscale x 4 x float> %x) {
reamesUnsubmitted
Done
ReplyInline Actions

Naming wise, "ext" makes me think "extend" not "extractelement".

I'd suggest extractelt_<type>_<op>_splat.

reames: Naming wise, "ext" makes me think "extend" not "extractelement". I'd suggest…
jacquesguanAuthorUnsubmitted
Done
ReplyInline Actions

Done.

jacquesguan: Done.
; CHECK-LABEL: extractelt_fadd_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI45_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI45_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfadd.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fadd <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 2
ret float %ext
}
define float @extractelt_fsub_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fsub_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI46_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfrsub.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fsub <vscale x 4 x float> %splat, %x
%ext = extractelement <vscale x 4 x float> %bo, i32 1
ret float %ext
}
define float @extractelt_fmul_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fmul_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmul.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fmul <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 3
ret float %ext
}
define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fdiv_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfdiv.vf v8, v8, ft0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fdiv <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 0
ret float %ext
}

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <vscale x 8 x double>, <vscale x 8 x double>* %x %a = load <vscale x 8 x double>, <vscale x 8 x double>* %x
%b = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %a) %b = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %a)
store double %b, double* %p store double %b, double* %p
ret void ret void
} }
declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>)
define float @extractelt_fadd_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fadd_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfadd.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fadd <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 2
ret float %ext
}
define float @extractelt_fsub_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fsub_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfrsub.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fsub <vscale x 4 x float> %splat, %x
%ext = extractelement <vscale x 4 x float> %bo, i32 1
ret float %ext
}
define float @extractelt_fmul_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fmul_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI49_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmul.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fmul <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 3
ret float %ext
}
define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
; CHECK-LABEL: extractelt_fdiv_nxv4f32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI50_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfdiv.vf v8, v8, ft0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fdiv <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 0
ret float %ext
}

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

Show First 20 Lines • Show All 735 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i64> %v, i32 %idx %r = extractelement <vscale x 8 x i64> %v, i32 %idx
ret i64 %r ret i64 %r
} }
define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_add_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 3
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = add <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_sub_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v8, 3
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sub <vscale x 4 x i32> %splat, %x
%ext = extractelement <vscale x 4 x i32> %bo, i32 1
ret i32 %ext
}
define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_mul_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = mul <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 3
ret i32 %ext
}
define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_sdiv_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1366
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v10, v8, 31
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext
}
define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_udiv_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1366
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v10, v8, 31
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext
}

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

Show First 20 Lines • Show All 699 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i64> %v, i32 %idx %r = extractelement <vscale x 8 x i64> %v, i32 %idx
ret i64 %r ret i64 %r
} }
define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_add_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 3
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = add <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_sub_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v8, 3
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sub <vscale x 4 x i32> %splat, %x
%ext = extractelement <vscale x 4 x i32> %bo, i32 1
ret i32 %ext
}
define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_mul_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = mul <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 3
ret i32 %ext
}
define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_sdiv_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addiw a0, a0, 1366
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v10, v8, 31
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext
}
define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; CHECK-LABEL: extractelt_udiv_nxv4i32_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addiw a0, a0, 1366
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: vsrl.vi v10, v8, 31
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext
}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

Show First 20 Lines • Show All 605 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = extractelement <2 x double> %a, i64 1 %b = extractelement <2 x double> %a, i64 1
store double %b, double* %p store double %b, double* %p
ret void ret void
} }
define i32 @extractelt_add_v4i32(<4 x i32> %x) {
; CHECK-LABEL: extractelt_add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 13
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%bo = add <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
; CHECK-LABEL: extractelt_sub_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vrsub.vi v8, v8, 13
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%bo = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %x
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; CHECK-LABEL: extractelt_mul_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 13
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%bo = mul <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
reamesUnsubmitted
Done
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Meta comment: "1" and "0" are special edge cases for mul and div. Please use a constant which is not an edge case if you're not testing that behavior.

reames: Meta comment: "1" and "0" are special edge cases for mul and div. Please use a constant which…
jacquesguanAuthorUnsubmitted
Done
ReplyInline Actions

Done.

jacquesguan: Done.
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV32-LABEL: extractelt_sdiv_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: li a0, -1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
reamesUnsubmitted
Done
ReplyInline Actions

Example of previous comment causing less than helpful test output.

reames: Example of previous comment causing less than helpful test output.
jacquesguanAuthorUnsubmitted
Done
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Done.

jacquesguan: Done.
; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-NEXT: vslideup.vi v10, v9, 3
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-NEXT: lui a0, %hi(.LCPI38_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI38_0)
; RV32-NEXT: vle32.v v9, (a0)
; RV32-NEXT: lui a0, %hi(.LCPI38_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI38_1)
; RV32-NEXT: vle32.v v11, (a0)
; RV32-NEXT: vand.vv v10, v8, v10
; RV32-NEXT: vmulh.vv v8, v8, v9
; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: vsra.vv v9, v8, v11
; RV32-NEXT: vsrl.vi v8, v8, 31
; RV32-NEXT: vadd.vv v8, v9, v8
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32-NEXT: vslidedown.vi v8, v8, 2
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_sdiv_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: li a0, -1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV64-NEXT: vslideup.vi v10, v9, 3
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI38_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI38_0)
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: lui a0, %hi(.LCPI38_1)
; RV64-NEXT: addi a0, a0, %lo(.LCPI38_1)
; RV64-NEXT: vle32.v v11, (a0)
; RV64-NEXT: vand.vv v10, v8, v10
; RV64-NEXT: vmulh.vv v8, v8, v9
; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vsra.vv v8, v8, v11
; RV64-NEXT: vsrl.vi v9, v8, 31
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%bo = sdiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
}
define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; CHECK-LABEL: extractelt_udiv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v10, v9, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI39_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI39_0)
; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vmulhu.vv v8, v8, v9
; CHECK-NEXT: vsrl.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
}
define float @extractelt_fadd_v4f32(<4 x float> %x) {
; CHECK-LABEL: extractelt_fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI40_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfadd.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%bo = fadd <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
}
define float @extractelt_fsub_v4f32(<4 x float> %x) {
; CHECK-LABEL: extractelt_fsub_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI41_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI41_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfrsub.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%bo = fsub <4 x float> <float 11.0, float 12.0, float 13.0, float 14.0>, %x
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
}
define float @extractelt_fmul_v4f32(<4 x float> %x) {
; CHECK-LABEL: extractelt_fmul_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI42_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmul.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%bo = fmul <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
}
define float @extractelt_fdiv_v4f32(<4 x float> %x) {
; CHECK-LABEL: extractelt_fdiv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI43_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI43_0)(a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfdiv.vf v8, v8, ft0
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%bo = fdiv <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
}