[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.

[kito-cheng]

Summary

RISC-V expand register tuple spilling into series of register spilling after
register allocation phase by the pseudo instruction expansion, however part of
register tuple might be still undefined during spilling, machine verifier will
complain the spill instruction is using an undefined physical register.

Optimal solution should be doing liveness analysis and do not emit spill
and reload for those undefined parts, but accurate liveness info at that point
is not so easy to get.

So the suboptimal solution is still spill and reload those undefined parts, but
adding implicit-use of super register to spill function, then machine
verifier will only report report using undefined physical register if
the when whole super register is undefined, and this behavior are also
documented in MachineVerifier::checkLiveness[1].

Example for demo what happend:

v10m2 = xxx
# v12m2 not define yet
PseudoVSPILL2_M2 v10m2_v12m2
...

After expansion:

v10m2 = xxx
# v12m2 not define yet
# Expand PseudoVSPILL2_M2 v10m2_v12m2 to 2 vs2r
VS2R_V v10m2
VS2R_V v12m2 # Use undef reg!

What this patch did:

v10m2 = xxx
# v12m2 not define yet
# Expand PseudoVSPILL2_M2 v10m2_v12m2 to 2 vs2r
VS2R_V v10m2 implicit v10m2_v12m2
# Use undef reg (v12m2), but v10m2_v12m2 ins't totally undef, so
# that's OK.
VS2R_V v12m2 implicit v10m2_v12m2

[1] https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/MachineVerifier.cpp#L2016-L2019

[craig.topper]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

318

prevent -> prevents
complain -> complaining

325

can this be .addReg(SrcReg, RegState::Implicit)

llvm/test/CodeGen/RISCV/undef-subreg-range.mir

1 ↗

(On Diff #436391)

Move to rvv directory since it uses RVV instructions?

[kito-cheng]

Changes:

• Address @craig.topper's commet:
  • Use addReg rather than add(MachineOperand::CreateReg(...)).
  • Tweak comment in the code.
  • Move test case to rvv directory.

[frasercrmck]

The fix LGTM.

As for the test, I'm wondering: maybe it's good to have a "real-world" test case for this, but couldn't we test it far more simply? As it stands I'm finding it hard to find the actual bug in the test case.

Just to see how small the test case could be, I tried and was able to reproduce the issue with this test:

---
name:            foo
tracksRegLiveness: true
stack:
  - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 8,
      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true }
body:   |
  bb.0:
    liveins: $v8m2, $x10, $x11
    PseudoVSPILL2_M2 killed $v8m2_v10m2, killed $x10, killed $x11 :: (store unknown-size into %stack.0, align 8)
    PseudoRET
...

Perhaps that's a little too simplistic, but it does show off the issue rather cleanly.

llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir

7

Regardless of my comment below, we probably don't need these ModuleIDs or source_filenames?

[kito-cheng]

Chagnes:

• Refine testcase.

[kito-cheng]

@frasercrmck thanks your suggestion! that made testcase easier to understand what happened, my habit is generating a reduced C testcase and then use that to generating ll or mir test, I guess that habit is come from my GCC development experiences, I guess I should having some new habit about that for LLVM development :P

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir

13

Are all these flags needed? Does generating the test with -simplify-mir remove them?

[kito-cheng]

Changes:

• Remove unnecessary flags in the testcase.

[kito-cheng]

llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir

13

I don't use -simplify-mir to generate the testcase, but most flags are unnecessary, I just remove those manually this time, and that's new flag to me, I'll use that next time, thanks!

[craig.topper]

LGTM

[foad]

We do this (adding implicit super register operands) in AMDGPU too, but eventually they start getting in the way of other optimizations. I'd really like it if we could agree on another way to fix the physical subreg liveness problem. See: https://discourse.llvm.org/t/physical-subregister-liveness/5994

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

if (LMUL == 2) {
     Opcode = RISCV::VS4R_V;
     SubRegIdx = RISCV::sub_vrm4_0;
     static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
                   "Unexpected subreg numbering");
   } else
     assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
 
   for (unsigned I = 0; I < NF; ++I) {
+    // Adding implicit-use of super register to describe we are using part of
+    // super register, that prevents machine verifier complaining when part of
+    // subreg is undef, see comment in MachineVerifier::checkLiveness for more
+    // detail.
     BuildMI(MBB, MBBI, DL, TII->get(Opcode))
         .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
         .addReg(Base)
-        .addMemOperand(*(MBBI->memoperands_begin()));
+        .addMemOperand(*(MBBI->memoperands_begin()))
+        .addReg(SrcReg, RegState::Implicit);
     if (I != NF - 1)
       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
           .addReg(Base)
           .addReg(VL);
   }
   MBBI->eraseFromParent();
   return true;
 }

llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -O2 -mtriple riscv64 -riscv-enable-subreg-liveness \
+# RUN:     -verify-machineinstrs -run-pass=riscv-expand-pseudo -o - 2>&1 \
+# RUN:     | FileCheck %s
+--- |
+  define void @foo() #0 {
+  entry:
+    ret void
+  }
+...
+---
+name:            foo
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHCatchret:   false
+hasEHScopes:     false
+hasEHFunclets:   false
+failsVerification: false
+tracksDebugUserValues: true
+registers:       []
+liveins:         []
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       16
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true }
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  varArgsFrameIndex: 0
+  varArgsSaveSize: 0
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $x10, $x11
+    ; CHECK-LABEL: name: foo
+    ; CHECK: liveins: $v8m2, $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: VS2R_V $v8m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK-NEXT: $x10 = ADD $x10, $x11
+    ; CHECK-NEXT: VS2R_V $v10m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK-NEXT: PseudoRET
+    PseudoVSPILL2_M2 killed $v8m2_v10m2, killed $x10, killed $x11 :: (store unknown-size into %stack.0, align 8)
+    PseudoRET
+
+...