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Differential D127492

[X86][SLP] Basic test coverage for llvm.powi
ClosedPublic

Authored by n-omer on Jun 10 2022, 5:55 AM.

Details

Reviewers
RKSimon
rob.lougher
andreadb
craig.topper
efriedma
spatel
ABataev
Commits
rG245604a96fb0: [X86][SLP] Basic test coverage for llvm.powi
Summary

This patch introduces basic test coverage for llvm.powi.* intrinsics.

Diff Detail

Unit TestsFailed

TimeTest
80 msx64 debian > LLVM.Analysis/CostModel/X86::powi.ll
1,570 msx64 debian > LLVM.CodeGen/Thumb::frame-access.ll
110 msx64 debian > LLVM.Transforms/SLPVectorizer/X86::powi.ll

Event Timeline

n-omer created this revision.Jun 10 2022, 5:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 10 2022, 5:55 AM
Herald added subscribers: jsji, vporpo, StephenFan. · View Herald Transcript
n-omer requested review of this revision.Jun 10 2022, 5:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 10 2022, 5:55 AM
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RKSimon added a reviewer: ABataev.Jun 10 2022, 6:02 AM
RKSimon added inline comments.
llvm/test/Analysis/CostModel/X86/powi.ll
8

Probably worth adding a couple of different methods here with different i32 power factors: non-constant, negative, odd, even. big (above the limit for powi -> mul expansion):
@powi_var
@powi_6
@powi_3
@powi_n3
@powi_16

llvm/test/Transforms/SLPVectorizer/X86/powi.ll
8

again - you're going to need tests with different powi factors - not just the factor = 6 case from https://github.com/llvm/llvm-project/issues/53887 - its probably satisfactory to have these tests use different factors (just make sure you rename them to state the factor)?

probably worth adding at least one 'negative test' with different powi factors to make sure it doesn't try to vectorize / crash / whatever

Harbormaster completed remote builds in B169051: Diff 435884.Jun 10 2022, 7:02 AM
craig.topper retitled this revision from []X86][SLP] Basic test coverage for llvm.powi to [X86][SLP] Basic test coverage for llvm.powi.Jun 10 2022, 12:56 PM
n-omer updated this revision to Diff 436312.Jun 13 2022, 2:41 AM

Address review comments.

Herald added a subscriber: nlopes. · View Herald TranscriptJun 13 2022, 2:41 AM
nlopes added a comment.Jun 13 2022, 2:47 AM

If possible, please replace all uses of undef with poison. Thank you!

Harbormaster completed remote builds in B169388: Diff 436312.Jun 13 2022, 3:35 AM
n-omer updated this revision to Diff 436716.Jun 14 2022, 2:37 AM
n-omer marked 2 inline comments as done.

Replace undef with poison.

Harbormaster completed remote builds in B169672: Diff 436716.Jun 14 2022, 3:33 AM
n-omer updated this revision to Diff 436751.Jun 14 2022, 5:42 AM

Update RUN lines to fix failing builds and add new variable argument test to SLP.

RKSimon accepted this revision.Jun 14 2022, 5:58 AM

LGTM

This revision is now accepted and ready to land.Jun 14 2022, 5:58 AM
Harbormaster completed remote builds in B169697: Diff 436751.Jun 14 2022, 6:43 AM
This revision was landed with ongoing or failed builds.Jun 15 2022, 3:14 AM
Closed by commit rG245604a96fb0: [X86][SLP] Basic test coverage for llvm.powi (authored by n-omer, committed by jmorse). · Explain Why
This revision was automatically updated to reflect the committed changes.
jmorse added a commit: rG245604a96fb0: [X86][SLP] Basic test coverage for llvm.powi.
jmorse mentioned this in D125953: [DebugInfo][InstrRef] Handle joins PHI+Def values in LiveDebugValues.Jul 25 2022, 10:43 AM

Revision Contents

PathSize
llvm/
test/
Analysis/
CostModel/
X86/
357 lines
Transforms/
SLPVectorizer/
X86/
546 lines

Diff 436312

llvm/test/Analysis/CostModel/X86/powi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -enable-no-nans-fp-math -passes="print<cost-model>" 2>&1 -disable-output -mtriple=x86_64-linux-gnu -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -enable-no-nans-fp-math -passes="print<cost-model>" 2>&1 -disable-output -mtriple=x86_64-linux-gnu -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
; RUN: opt < %s -enable-no-nans-fp-math -passes="print<cost-model>" 2>&1 -disable-output -mtriple=x86_64-linux-gnu -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -enable-no-nans-fp-math -passes="print<cost-model>" 2>&1 -disable-output -mtriple=x86_64-linux-gnu -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
define i32 @powi_var(i32 %arg) {
; SSE-LABEL: 'powi_var'
RKSimonUnsubmitted
Done
ReplyInline Actions

Probably worth adding a couple of different methods here with different i32 power factors: non-constant, negative, odd, even. big (above the limit for powi -> mul expansion):
@powi_var
@powi_6
@powi_3
@powi_n3
@powi_16

RKSimon: Probably worth adding a couple of different methods here with different i32 power factors: non…
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 %arg)
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX1-LABEL: 'powi_var'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 %arg)
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX2-LABEL: 'powi_var'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 %arg)
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'powi_var'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 %arg)
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F32 = call float @llvm.powi.f32(float undef, i32 %arg)
%V2F32 = call <2 x float> @llvm.powi.v2f32(<2 x float> undef, i32 %arg)
%V4F32 = call <4 x float> @llvm.powi.v4f32(<4 x float> undef, i32 %arg)
%V8F32 = call <8 x float> @llvm.powi.v8f32(<8 x float> undef, i32 %arg)
%V16F32 = call <16 x float> @llvm.powi.v16f32(<16 x float> undef, i32 %arg)
%F64 = call double @llvm.powi.f64(double undef, i32 %arg)
%V2F64 = call <2 x double> @llvm.powi.v2f64(<2 x double> undef, i32 %arg)
%V4F64 = call <4 x double> @llvm.powi.v4f64(<4 x double> undef, i32 %arg)
%V8F64 = call <8 x double> @llvm.powi.v8f64(<8 x double> undef, i32 %arg)
%V16F64 = call <16 x double> @llvm.powi.v16f64(<16 x double> undef, i32 %arg)
ret i32 undef
}
define i32 @powi_3() {
; SSE-LABEL: 'powi_3'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 3)
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX1-LABEL: 'powi_3'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX2-LABEL: 'powi_3'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'powi_3'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F32 = call float @llvm.powi.f32(float undef, i32 3)
%V2F32 = call <2 x float> @llvm.powi.v2f32(<2 x float> undef, i32 3)
%V4F32 = call <4 x float> @llvm.powi.v4f32(<4 x float> undef, i32 3)
%V8F32 = call <8 x float> @llvm.powi.v8f32(<8 x float> undef, i32 3)
%V16F32 = call <16 x float> @llvm.powi.v16f32(<16 x float> undef, i32 3)
%F64 = call double @llvm.powi.f64(double undef, i32 3)
%V2F64 = call <2 x double> @llvm.powi.v2f64(<2 x double> undef, i32 3)
%V4F64 = call <4 x double> @llvm.powi.v4f64(<4 x double> undef, i32 3)
%V8F64 = call <8 x double> @llvm.powi.v8f64(<8 x double> undef, i32 3)
%V16F64 = call <16 x double> @llvm.powi.v16f64(<16 x double> undef, i32 3)
ret i32 undef
}
define i32 @powi_n3() {
; SSE-LABEL: 'powi_n3'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 -3)
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX1-LABEL: 'powi_n3'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 -3)
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX2-LABEL: 'powi_n3'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 -3)
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'powi_n3'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 -3)
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F32 = call float @llvm.powi.f32(float undef, i32 -3)
%V2F32 = call <2 x float> @llvm.powi.v2f32(<2 x float> undef, i32 -3)
%V4F32 = call <4 x float> @llvm.powi.v4f32(<4 x float> undef, i32 -3)
%V8F32 = call <8 x float> @llvm.powi.v8f32(<8 x float> undef, i32 -3)
%V16F32 = call <16 x float> @llvm.powi.v16f32(<16 x float> undef, i32 -3)
%F64 = call double @llvm.powi.f64(double undef, i32 -3)
%V2F64 = call <2 x double> @llvm.powi.v2f64(<2 x double> undef, i32 -3)
%V4F64 = call <4 x double> @llvm.powi.v4f64(<4 x double> undef, i32 -3)
%V8F64 = call <8 x double> @llvm.powi.v8f64(<8 x double> undef, i32 -3)
%V16F64 = call <16 x double> @llvm.powi.v16f64(<16 x double> undef, i32 -3)
ret i32 undef
}
define i32 @powi_6() {
; SSE-LABEL: 'powi_6'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX1-LABEL: 'powi_6'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX2-LABEL: 'powi_6'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'powi_6'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F32 = call float @llvm.powi.f32(float undef, i32 6)
%V2F32 = call <2 x float> @llvm.powi.v2f32(<2 x float> undef, i32 6)
%V4F32 = call <4 x float> @llvm.powi.v4f32(<4 x float> undef, i32 6)
%V8F32 = call <8 x float> @llvm.powi.v8f32(<8 x float> undef, i32 6)
%V16F32 = call <16 x float> @llvm.powi.v16f32(<16 x float> undef, i32 6)
%F64 = call double @llvm.powi.f64(double undef, i32 6)
%V2F64 = call <2 x double> @llvm.powi.v2f64(<2 x double> undef, i32 6)
%V4F64 = call <4 x double> @llvm.powi.v4f64(<4 x double> undef, i32 6)
%V8F64 = call <8 x double> @llvm.powi.v8f64(<8 x double> undef, i32 6)
%V16F64 = call <16 x double> @llvm.powi.v16f64(<16 x double> undef, i32 6)
ret i32 undef
}
define i32 @powi_16() {
; SSE-LABEL: 'powi_16'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 16)
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX1-LABEL: 'powi_16'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 16)
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX2-LABEL: 'powi_16'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 16)
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'powi_16'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.powi.f32.i32(float undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = call double @llvm.powi.f64.i32(double undef, i32 6)
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V16F64 = call <16 x double> @llvm.powi.v16f64.i32(<16 x double> undef, i32 16)
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F32 = call float @llvm.powi.f32(float undef, i32 16)
%V2F32 = call <2 x float> @llvm.powi.v2f32(<2 x float> undef, i32 16)
%V4F32 = call <4 x float> @llvm.powi.v4f32(<4 x float> undef, i32 16)
%V8F32 = call <8 x float> @llvm.powi.v8f32(<8 x float> undef, i32 16)
%V16F32 = call <16 x float> @llvm.powi.v16f32(<16 x float> undef, i32 16)
%F64 = call double @llvm.powi.f64(double undef, i32 6)
%V2F64 = call <2 x double> @llvm.powi.v2f64(<2 x double> undef, i32 16)
%V4F64 = call <4 x double> @llvm.powi.v4f64(<4 x double> undef, i32 16)
%V8F64 = call <8 x double> @llvm.powi.v8f64(<8 x double> undef, i32 16)
%V16F64 = call <16 x double> @llvm.powi.v16f64(<16 x double> undef, i32 16)
ret i32 undef
}
declare float @llvm.powi.f32(float, i32)
declare <2 x float> @llvm.powi.v2f32(<2 x float>, i32)
declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32)
declare <8 x float> @llvm.powi.v8f32(<8 x float>, i32)
declare <16 x float> @llvm.powi.v16f32(<16 x float>, i32)
declare double @llvm.powi.f64(double, i32)
declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32)
declare <4 x double> @llvm.powi.v4f64(<4 x double>, i32)
declare <8 x double> @llvm.powi.v8f64(<8 x double>, i32)
declare <16 x double> @llvm.powi.v16f64(<16 x double>, i32)

llvm/test/Transforms/SLPVectorizer/X86/powi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-linux-gnu -mcpu=x86-64 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-linux-gnu -mcpu=x86-64-v2 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
; RUN: opt < %s -mtriple=x86_64-linux-gnu -mcpu=x86-64-v3 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-linux-gnu -mcpu=x86-64-v4 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
define <2 x double> @buildvector_powi_2f64_6(<2 x double> %a) {
; CHECK-LABEL: @buildvector_powi_2f64_6(
RKSimonUnsubmitted
Done
ReplyInline Actions

again - you're going to need tests with different powi factors - not just the factor = 6 case from https://github.com/llvm/llvm-project/issues/53887 - its probably satisfactory to have these tests use different factors (just make sure you rename them to state the factor)?

probably worth adding at least one 'negative test' with different powi factors to make sure it doesn't try to vectorize / crash / whatever

RKSimon: again - you're going to need tests with different powi factors - not just the factor = 6 case…
; CHECK-NEXT: [[A0:%.*]] = extractelement <2 x double> [[A:%.*]], i32 0
; CHECK-NEXT: [[A1:%.*]] = extractelement <2 x double> [[A]], i32 1
; CHECK-NEXT: [[C0:%.*]] = call double @llvm.powi.f64.i32(double [[A0]], i32 6)
; CHECK-NEXT: [[C1:%.*]] = call double @llvm.powi.f64.i32(double [[A1]], i32 6)
; CHECK-NEXT: [[R0:%.*]] = insertelement <2 x double> undef, double [[C0]], i32 0
; CHECK-NEXT: [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[C1]], i32 1
; CHECK-NEXT: ret <2 x double> [[R1]]
;
%a0 = extractelement <2 x double> %a, i32 0
%a1 = extractelement <2 x double> %a, i32 1
%c0 = call double @llvm.powi.f64(double %a0 , i32 6)
%c1 = call double @llvm.powi.f64(double %a1 , i32 6)
%r0 = insertelement <2 x double> undef, double %c0, i32 0
%r1 = insertelement <2 x double> %r0, double %c1, i32 1
ret <2 x double> %r1
}
define <4 x float> @buildvector_powi_4f32_3(<4 x float> %a) {
; SSE-LABEL: @buildvector_powi_4f32_3(
; SSE-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A0]], i32 0
; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[A1]], i32 1
; SSE-NEXT: [[TMP3:%.*]] = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> [[TMP2]], i32 3)
; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x float> poison, float [[A2]], i32 0
; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x float> [[TMP4]], float [[A3]], i32 1
; SSE-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> [[TMP5]], i32 3)
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; SSE-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; SSE-NEXT: [[R31:%.*]] = shufflevector <4 x float> [[TMP7]], <4 x float> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; SSE-NEXT: ret <4 x float> [[R31]]
;
; AVX1-LABEL: @buildvector_powi_4f32_3(
; AVX1-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
; AVX1-NEXT: [[C0:%.*]] = call float @llvm.powi.f32.i32(float [[A0]], i32 3)
; AVX1-NEXT: [[C1:%.*]] = call float @llvm.powi.f32.i32(float [[A1]], i32 3)
; AVX1-NEXT: [[C2:%.*]] = call float @llvm.powi.f32.i32(float [[A2]], i32 3)
; AVX1-NEXT: [[C3:%.*]] = call float @llvm.powi.f32.i32(float [[A3]], i32 3)
; AVX1-NEXT: [[R0:%.*]] = insertelement <4 x float> undef, float [[C0]], i32 0
; AVX1-NEXT: [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[C1]], i32 1
; AVX1-NEXT: [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[C2]], i32 2
; AVX1-NEXT: [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[C3]], i32 3
; AVX1-NEXT: ret <4 x float> [[R3]]
;
; AVX2-LABEL: @buildvector_powi_4f32_3(
; AVX2-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
; AVX2-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
; AVX2-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
; AVX2-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
; AVX2-NEXT: [[C0:%.*]] = call float @llvm.powi.f32.i32(float [[A0]], i32 3)
; AVX2-NEXT: [[C1:%.*]] = call float @llvm.powi.f32.i32(float [[A1]], i32 3)
; AVX2-NEXT: [[C2:%.*]] = call float @llvm.powi.f32.i32(float [[A2]], i32 3)
; AVX2-NEXT: [[C3:%.*]] = call float @llvm.powi.f32.i32(float [[A3]], i32 3)
; AVX2-NEXT: [[R0:%.*]] = insertelement <4 x float> undef, float [[C0]], i32 0
; AVX2-NEXT: [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[C1]], i32 1
; AVX2-NEXT: [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[C2]], i32 2
; AVX2-NEXT: [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[C3]], i32 3
; AVX2-NEXT: ret <4 x float> [[R3]]
;
; AVX512-LABEL: @buildvector_powi_4f32_3(
; AVX512-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
; AVX512-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
; AVX512-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
; AVX512-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
; AVX512-NEXT: [[C0:%.*]] = call float @llvm.powi.f32.i32(float [[A0]], i32 3)
; AVX512-NEXT: [[C1:%.*]] = call float @llvm.powi.f32.i32(float [[A1]], i32 3)
; AVX512-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A2]], i32 0
; AVX512-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[A3]], i32 1
; AVX512-NEXT: [[TMP3:%.*]] = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> [[TMP2]], i32 3)
; AVX512-NEXT: [[R0:%.*]] = insertelement <4 x float> undef, float [[C0]], i32 0
; AVX512-NEXT: [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[C1]], i32 1
; AVX512-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; AVX512-NEXT: [[R31:%.*]] = shufflevector <4 x float> [[R1]], <4 x float> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; AVX512-NEXT: ret <4 x float> [[R31]]
;
%a0 = extractelement <4 x float> %a, i32 0
%a1 = extractelement <4 x float> %a, i32 1
%a2 = extractelement <4 x float> %a, i32 2
%a3 = extractelement <4 x float> %a, i32 3
%c0 = call float @llvm.powi.f32(float %a0 , i32 3)
%c1 = call float @llvm.powi.f32(float %a1 , i32 3)
%c2 = call float @llvm.powi.f32(float %a2 , i32 3)
%c3 = call float @llvm.powi.f32(float %a3 , i32 3)
%r0 = insertelement <4 x float> undef, float %c0, i32 0
%r1 = insertelement <4 x float> %r0, float %c1, i32 1
%r2 = insertelement <4 x float> %r1, float %c2, i32 2
%r3 = insertelement <4 x float> %r2, float %c3, i32 3
ret <4 x float> %r3
}
;
; 256-bit Vectors
;
define <4 x double> @buildvector_powi_4f64_16(<4 x double> %a) {
; SSE-LABEL: @buildvector_powi_4f64_16(
; SSE-NEXT: [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3
; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A0]], i32 0
; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[A1]], i32 1
; SSE-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[TMP2]], i32 16)
; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[A2]], i32 0
; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[A3]], i32 1
; SSE-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[TMP5]], i32 16)
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; SSE-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; SSE-NEXT: [[R31:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; SSE-NEXT: ret <4 x double> [[R31]]
;
; AVX1-LABEL: @buildvector_powi_4f64_16(
; AVX1-NEXT: [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3
; AVX1-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A0]], i32 0
; AVX1-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[A1]], i32 1
; AVX1-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[TMP2]], i32 16)
; AVX1-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[A2]], i32 0
; AVX1-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[A3]], i32 1
; AVX1-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[TMP5]], i32 16)
; AVX1-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; AVX1-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; AVX1-NEXT: [[R31:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; AVX1-NEXT: ret <4 x double> [[R31]]
;
; AVX2-LABEL: @buildvector_powi_4f64_16(
; AVX2-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[A:%.*]], i32 16)
; AVX2-NEXT: ret <4 x double> [[TMP1]]
;
; AVX512-LABEL: @buildvector_powi_4f64_16(
; AVX512-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[A:%.*]], i32 16)
; AVX512-NEXT: ret <4 x double> [[TMP1]]
;
%a0 = extractelement <4 x double> %a, i32 0
%a1 = extractelement <4 x double> %a, i32 1
%a2 = extractelement <4 x double> %a, i32 2
%a3 = extractelement <4 x double> %a, i32 3
%c0 = call double @llvm.powi.f64(double %a0 , i32 16)
%c1 = call double @llvm.powi.f64(double %a1 , i32 16)
%c2 = call double @llvm.powi.f64(double %a2 , i32 16)
%c3 = call double @llvm.powi.f64(double %a3 , i32 16)
%r0 = insertelement <4 x double> undef, double %c0, i32 0
%r1 = insertelement <4 x double> %r0, double %c1, i32 1
%r2 = insertelement <4 x double> %r1, double %c2, i32 2
%r3 = insertelement <4 x double> %r2, double %c3, i32 3
ret <4 x double> %r3
}
define <8 x float> @buildvector_powi_8f32_4(<8 x float> %a) {
; SSE-LABEL: @buildvector_powi_8f32_4(
; SSE-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
; SSE-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
; SSE-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
; SSE-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
; SSE-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
; SSE-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A0]], i32 0
; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A1]], i32 1
; SSE-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A2]], i32 2
; SSE-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A3]], i32 3
; SSE-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP4]], i32 4)
; SSE-NEXT: [[TMP6:%.*]] = insertelement <4 x float> poison, float [[A4]], i32 0
; SSE-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[A5]], i32 1
; SSE-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[A6]], i32 2
; SSE-NEXT: [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[A7]], i32 3
; SSE-NEXT: [[TMP10:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP9]], i32 4)
; SSE-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[TMP12:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[TMP11]], <8 x float> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; SSE-NEXT: ret <8 x float> [[R71]]
;
; AVX1-LABEL: @buildvector_powi_8f32_4(
; AVX1-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
; AVX1-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
; AVX1-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
; AVX1-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
; AVX1-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
; AVX1-NEXT: [[C0:%.*]] = call float @llvm.powi.f32.i32(float [[A0]], i32 4)
; AVX1-NEXT: [[C1:%.*]] = call float @llvm.powi.f32.i32(float [[A1]], i32 4)
; AVX1-NEXT: [[C2:%.*]] = call float @llvm.powi.f32.i32(float [[A2]], i32 4)
; AVX1-NEXT: [[C3:%.*]] = call float @llvm.powi.f32.i32(float [[A3]], i32 4)
; AVX1-NEXT: [[C4:%.*]] = call float @llvm.powi.f32.i32(float [[A4]], i32 4)
; AVX1-NEXT: [[C5:%.*]] = call float @llvm.powi.f32.i32(float [[A5]], i32 4)
; AVX1-NEXT: [[C6:%.*]] = call float @llvm.powi.f32.i32(float [[A6]], i32 4)
; AVX1-NEXT: [[C7:%.*]] = call float @llvm.powi.f32.i32(float [[A7]], i32 4)
; AVX1-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[C0]], i32 0
; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[C1]], i32 1
; AVX1-NEXT: [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[C2]], i32 2
; AVX1-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[C3]], i32 3
; AVX1-NEXT: [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[C4]], i32 4
; AVX1-NEXT: [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[C5]], i32 5
; AVX1-NEXT: [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[C6]], i32 6
; AVX1-NEXT: [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[C7]], i32 7
; AVX1-NEXT: ret <8 x float> [[R7]]
;
; AVX2-LABEL: @buildvector_powi_8f32_4(
; AVX2-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> [[A:%.*]], i32 4)
; AVX2-NEXT: ret <8 x float> [[TMP1]]
;
; AVX512-LABEL: @buildvector_powi_8f32_4(
; AVX512-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> [[A:%.*]], i32 4)
; AVX512-NEXT: ret <8 x float> [[TMP1]]
;
%a0 = extractelement <8 x float> %a, i32 0
%a1 = extractelement <8 x float> %a, i32 1
%a2 = extractelement <8 x float> %a, i32 2
%a3 = extractelement <8 x float> %a, i32 3
%a4 = extractelement <8 x float> %a, i32 4
%a5 = extractelement <8 x float> %a, i32 5
%a6 = extractelement <8 x float> %a, i32 6
%a7 = extractelement <8 x float> %a, i32 7
%c0 = call float @llvm.powi.f32(float %a0 , i32 4)
%c1 = call float @llvm.powi.f32(float %a1 , i32 4)
%c2 = call float @llvm.powi.f32(float %a2 , i32 4)
%c3 = call float @llvm.powi.f32(float %a3 , i32 4)
%c4 = call float @llvm.powi.f32(float %a4 , i32 4)
%c5 = call float @llvm.powi.f32(float %a5 , i32 4)
%c6 = call float @llvm.powi.f32(float %a6 , i32 4)
%c7 = call float @llvm.powi.f32(float %a7 , i32 4)
%r0 = insertelement <8 x float> undef, float %c0, i32 0
%r1 = insertelement <8 x float> %r0, float %c1, i32 1
%r2 = insertelement <8 x float> %r1, float %c2, i32 2
%r3 = insertelement <8 x float> %r2, float %c3, i32 3
%r4 = insertelement <8 x float> %r3, float %c4, i32 4
%r5 = insertelement <8 x float> %r4, float %c5, i32 5
%r6 = insertelement <8 x float> %r5, float %c6, i32 6
%r7 = insertelement <8 x float> %r6, float %c7, i32 7
ret <8 x float> %r7
}
;
; 512-bit Vectors
;
define <8 x double> @buildvector_powi_8f64_5(<8 x double> %a) {
; SSE-LABEL: @buildvector_powi_8f64_5(
; SSE-NEXT: [[A0:%.*]] = extractelement <8 x double> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <8 x double> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <8 x double> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <8 x double> [[A]], i32 3
; SSE-NEXT: [[A4:%.*]] = extractelement <8 x double> [[A]], i32 4
; SSE-NEXT: [[A5:%.*]] = extractelement <8 x double> [[A]], i32 5
; SSE-NEXT: [[A6:%.*]] = extractelement <8 x double> [[A]], i32 6
; SSE-NEXT: [[A7:%.*]] = extractelement <8 x double> [[A]], i32 7
; SSE-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0]], i32 0
; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1]], i32 1
; SSE-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2]], i32 2
; SSE-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3]], i32 3
; SSE-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[TMP4]], i32 5)
; SSE-NEXT: [[TMP6:%.*]] = insertelement <4 x double> poison, double [[A4]], i32 0
; SSE-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[A5]], i32 1
; SSE-NEXT: [[TMP8:%.*]] = insertelement <4 x double> [[TMP7]], double [[A6]], i32 2
; SSE-NEXT: [[TMP9:%.*]] = insertelement <4 x double> [[TMP8]], double [[A7]], i32 3
; SSE-NEXT: [[TMP10:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[TMP9]], i32 5)
; SSE-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x double> [[TMP11]], <8 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; SSE-NEXT: ret <8 x double> [[R71]]
;
; AVX1-LABEL: @buildvector_powi_8f64_5(
; AVX1-NEXT: [[A0:%.*]] = extractelement <8 x double> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <8 x double> [[A]], i32 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <8 x double> [[A]], i32 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <8 x double> [[A]], i32 3
; AVX1-NEXT: [[A4:%.*]] = extractelement <8 x double> [[A]], i32 4
; AVX1-NEXT: [[A5:%.*]] = extractelement <8 x double> [[A]], i32 5
; AVX1-NEXT: [[A6:%.*]] = extractelement <8 x double> [[A]], i32 6
; AVX1-NEXT: [[A7:%.*]] = extractelement <8 x double> [[A]], i32 7
; AVX1-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0]], i32 0
; AVX1-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1]], i32 1
; AVX1-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2]], i32 2
; AVX1-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3]], i32 3
; AVX1-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[TMP4]], i32 5)
; AVX1-NEXT: [[TMP6:%.*]] = insertelement <4 x double> poison, double [[A4]], i32 0
; AVX1-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[A5]], i32 1
; AVX1-NEXT: [[TMP8:%.*]] = insertelement <4 x double> [[TMP7]], double [[A6]], i32 2
; AVX1-NEXT: [[TMP9:%.*]] = insertelement <4 x double> [[TMP8]], double [[A7]], i32 3
; AVX1-NEXT: [[TMP10:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[TMP9]], i32 5)
; AVX1-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; AVX1-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; AVX1-NEXT: [[R71:%.*]] = shufflevector <8 x double> [[TMP11]], <8 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; AVX1-NEXT: ret <8 x double> [[R71]]
;
; AVX2-LABEL: @buildvector_powi_8f64_5(
; AVX2-NEXT: [[TMP1:%.*]] = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> [[A:%.*]], i32 5)
; AVX2-NEXT: ret <8 x double> [[TMP1]]
;
; AVX512-LABEL: @buildvector_powi_8f64_5(
; AVX512-NEXT: [[TMP1:%.*]] = call <8 x double> @llvm.powi.v8f64.i32(<8 x double> [[A:%.*]], i32 5)
; AVX512-NEXT: ret <8 x double> [[TMP1]]
;
%a0 = extractelement <8 x double> %a, i32 0
%a1 = extractelement <8 x double> %a, i32 1
%a2 = extractelement <8 x double> %a, i32 2
%a3 = extractelement <8 x double> %a, i32 3
%a4 = extractelement <8 x double> %a, i32 4
%a5 = extractelement <8 x double> %a, i32 5
%a6 = extractelement <8 x double> %a, i32 6
%a7 = extractelement <8 x double> %a, i32 7
%c0 = call double @llvm.powi.f64(double %a0 , i32 5)
%c1 = call double @llvm.powi.f64(double %a1 , i32 5)
%c2 = call double @llvm.powi.f64(double %a2 , i32 5)
%c3 = call double @llvm.powi.f64(double %a3 , i32 5)
%c4 = call double @llvm.powi.f64(double %a4 , i32 5)
%c5 = call double @llvm.powi.f64(double %a5 , i32 5)
%c6 = call double @llvm.powi.f64(double %a6 , i32 5)
%c7 = call double @llvm.powi.f64(double %a7 , i32 5)
%r0 = insertelement <8 x double> undef, double %c0, i32 0
%r1 = insertelement <8 x double> %r0, double %c1, i32 1
%r2 = insertelement <8 x double> %r1, double %c2, i32 2
%r3 = insertelement <8 x double> %r2, double %c3, i32 3
%r4 = insertelement <8 x double> %r3, double %c4, i32 4
%r5 = insertelement <8 x double> %r4, double %c5, i32 5
%r6 = insertelement <8 x double> %r5, double %c6, i32 6
%r7 = insertelement <8 x double> %r6, double %c7, i32 7
ret <8 x double> %r7
}
define <8 x double> @buildvector_powi_8f64_varied(<8 x double> %a) {
; CHECK-LABEL: @buildvector_powi_8f64_varied(
; CHECK-NEXT: [[A0:%.*]] = extractelement <8 x double> [[A:%.*]], i32 0
; CHECK-NEXT: [[A1:%.*]] = extractelement <8 x double> [[A]], i32 1
; CHECK-NEXT: [[A2:%.*]] = extractelement <8 x double> [[A]], i32 2
; CHECK-NEXT: [[A3:%.*]] = extractelement <8 x double> [[A]], i32 3
; CHECK-NEXT: [[A4:%.*]] = extractelement <8 x double> [[A]], i32 4
; CHECK-NEXT: [[A5:%.*]] = extractelement <8 x double> [[A]], i32 5
; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x double> [[A]], i32 6
; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x double> [[A]], i32 7
; CHECK-NEXT: [[C0:%.*]] = call double @llvm.powi.f64.i32(double [[A0]], i32 1)
; CHECK-NEXT: [[C1:%.*]] = call double @llvm.powi.f64.i32(double [[A1]], i32 2)
; CHECK-NEXT: [[C2:%.*]] = call double @llvm.powi.f64.i32(double [[A2]], i32 3)
; CHECK-NEXT: [[C3:%.*]] = call double @llvm.powi.f64.i32(double [[A3]], i32 4)
; CHECK-NEXT: [[C4:%.*]] = call double @llvm.powi.f64.i32(double [[A4]], i32 5)
; CHECK-NEXT: [[C5:%.*]] = call double @llvm.powi.f64.i32(double [[A5]], i32 6)
; CHECK-NEXT: [[C6:%.*]] = call double @llvm.powi.f64.i32(double [[A6]], i32 7)
; CHECK-NEXT: [[C7:%.*]] = call double @llvm.powi.f64.i32(double [[A7]], i32 -8)
; CHECK-NEXT: [[R0:%.*]] = insertelement <8 x double> undef, double [[C0]], i32 0
; CHECK-NEXT: [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[C1]], i32 1
; CHECK-NEXT: [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[C2]], i32 2
; CHECK-NEXT: [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[C3]], i32 3
; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[C4]], i32 4
; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[C5]], i32 5
; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[C6]], i32 6
; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[C7]], i32 7
; CHECK-NEXT: ret <8 x double> [[R7]]
;
%a0 = extractelement <8 x double> %a, i32 0
%a1 = extractelement <8 x double> %a, i32 1
%a2 = extractelement <8 x double> %a, i32 2
%a3 = extractelement <8 x double> %a, i32 3
%a4 = extractelement <8 x double> %a, i32 4
%a5 = extractelement <8 x double> %a, i32 5
%a6 = extractelement <8 x double> %a, i32 6
%a7 = extractelement <8 x double> %a, i32 7
%c0 = call double @llvm.powi.f64(double %a0 , i32 1)
%c1 = call double @llvm.powi.f64(double %a1 , i32 2)
%c2 = call double @llvm.powi.f64(double %a2 , i32 3)
%c3 = call double @llvm.powi.f64(double %a3 , i32 4)
%c4 = call double @llvm.powi.f64(double %a4 , i32 5)
%c5 = call double @llvm.powi.f64(double %a5 , i32 6)
%c6 = call double @llvm.powi.f64(double %a6 , i32 7)
%c7 = call double @llvm.powi.f64(double %a7 , i32 -8)
%r0 = insertelement <8 x double> undef, double %c0, i32 0
%r1 = insertelement <8 x double> %r0, double %c1, i32 1
%r2 = insertelement <8 x double> %r1, double %c2, i32 2
%r3 = insertelement <8 x double> %r2, double %c3, i32 3
%r4 = insertelement <8 x double> %r3, double %c4, i32 4
%r5 = insertelement <8 x double> %r4, double %c5, i32 5
%r6 = insertelement <8 x double> %r5, double %c6, i32 6
%r7 = insertelement <8 x double> %r6, double %c7, i32 7
ret <8 x double> %r7
}
define <16 x float> @buildvector_powi_16f32_n13(<16 x float> %a) {
; SSE-LABEL: @buildvector_powi_16f32_n13(
; SSE-NEXT: [[A0:%.*]] = extractelement <16 x float> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <16 x float> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <16 x float> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <16 x float> [[A]], i32 3
; SSE-NEXT: [[A4:%.*]] = extractelement <16 x float> [[A]], i32 4
; SSE-NEXT: [[A5:%.*]] = extractelement <16 x float> [[A]], i32 5
; SSE-NEXT: [[A6:%.*]] = extractelement <16 x float> [[A]], i32 6
; SSE-NEXT: [[A7:%.*]] = extractelement <16 x float> [[A]], i32 7
; SSE-NEXT: [[A8:%.*]] = extractelement <16 x float> [[A]], i32 8
; SSE-NEXT: [[A9:%.*]] = extractelement <16 x float> [[A]], i32 9
; SSE-NEXT: [[A10:%.*]] = extractelement <16 x float> [[A]], i32 10
; SSE-NEXT: [[A11:%.*]] = extractelement <16 x float> [[A]], i32 11
; SSE-NEXT: [[A12:%.*]] = extractelement <16 x float> [[A]], i32 12
; SSE-NEXT: [[A13:%.*]] = extractelement <16 x float> [[A]], i32 13
; SSE-NEXT: [[A14:%.*]] = extractelement <16 x float> [[A]], i32 14
; SSE-NEXT: [[A15:%.*]] = extractelement <16 x float> [[A]], i32 15
; SSE-NEXT: [[TMP1:%.*]] = insertelement <8 x float> poison, float [[A0]], i32 0
; SSE-NEXT: [[TMP2:%.*]] = insertelement <8 x float> [[TMP1]], float [[A1]], i32 1
; SSE-NEXT: [[TMP3:%.*]] = insertelement <8 x float> [[TMP2]], float [[A2]], i32 2
; SSE-NEXT: [[TMP4:%.*]] = insertelement <8 x float> [[TMP3]], float [[A3]], i32 3
; SSE-NEXT: [[TMP5:%.*]] = insertelement <8 x float> [[TMP4]], float [[A4]], i32 4
; SSE-NEXT: [[TMP6:%.*]] = insertelement <8 x float> [[TMP5]], float [[A5]], i32 5
; SSE-NEXT: [[TMP7:%.*]] = insertelement <8 x float> [[TMP6]], float [[A6]], i32 6
; SSE-NEXT: [[TMP8:%.*]] = insertelement <8 x float> [[TMP7]], float [[A7]], i32 7
; SSE-NEXT: [[TMP9:%.*]] = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> [[TMP8]], i32 -13)
; SSE-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[A8]], i32 0
; SSE-NEXT: [[TMP11:%.*]] = insertelement <8 x float> [[TMP10]], float [[A9]], i32 1
; SSE-NEXT: [[TMP12:%.*]] = insertelement <8 x float> [[TMP11]], float [[A10]], i32 2
; SSE-NEXT: [[TMP13:%.*]] = insertelement <8 x float> [[TMP12]], float [[A11]], i32 3
; SSE-NEXT: [[TMP14:%.*]] = insertelement <8 x float> [[TMP13]], float [[A12]], i32 4
; SSE-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[A13]], i32 5
; SSE-NEXT: [[TMP16:%.*]] = insertelement <8 x float> [[TMP15]], float [[A14]], i32 6
; SSE-NEXT: [[TMP17:%.*]] = insertelement <8 x float> [[TMP16]], float [[A15]], i32 7
; SSE-NEXT: [[TMP18:%.*]] = call <8 x float> @llvm.powi.v8f32.i32(<8 x float> [[TMP17]], i32 -13)
; SSE-NEXT: [[TMP19:%.*]] = shufflevector <8 x float> [[TMP9]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[TMP20:%.*]] = shufflevector <8 x float> [[TMP18]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; SSE-NEXT: [[R151:%.*]] = shufflevector <16 x float> [[TMP19]], <16 x float> [[TMP20]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; SSE-NEXT: ret <16 x float> [[R151]]
;
; AVX1-LABEL: @buildvector_powi_16f32_n13(
; AVX1-NEXT: [[A0:%.*]] = extractelement <16 x float> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <16 x float> [[A]], i32 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <16 x float> [[A]], i32 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <16 x float> [[A]], i32 3
; AVX1-NEXT: [[A4:%.*]] = extractelement <16 x float> [[A]], i32 4
; AVX1-NEXT: [[A5:%.*]] = extractelement <16 x float> [[A]], i32 5
; AVX1-NEXT: [[A6:%.*]] = extractelement <16 x float> [[A]], i32 6
; AVX1-NEXT: [[A7:%.*]] = extractelement <16 x float> [[A]], i32 7
; AVX1-NEXT: [[A8:%.*]] = extractelement <16 x float> [[A]], i32 8
; AVX1-NEXT: [[A9:%.*]] = extractelement <16 x float> [[A]], i32 9
; AVX1-NEXT: [[A10:%.*]] = extractelement <16 x float> [[A]], i32 10
; AVX1-NEXT: [[A11:%.*]] = extractelement <16 x float> [[A]], i32 11
; AVX1-NEXT: [[A12:%.*]] = extractelement <16 x float> [[A]], i32 12
; AVX1-NEXT: [[A13:%.*]] = extractelement <16 x float> [[A]], i32 13
; AVX1-NEXT: [[A14:%.*]] = extractelement <16 x float> [[A]], i32 14
; AVX1-NEXT: [[A15:%.*]] = extractelement <16 x float> [[A]], i32 15
; AVX1-NEXT: [[C0:%.*]] = call float @llvm.powi.f32.i32(float [[A0]], i32 -13)
; AVX1-NEXT: [[C1:%.*]] = call float @llvm.powi.f32.i32(float [[A1]], i32 -13)
; AVX1-NEXT: [[C2:%.*]] = call float @llvm.powi.f32.i32(float [[A2]], i32 -13)
; AVX1-NEXT: [[C3:%.*]] = call float @llvm.powi.f32.i32(float [[A3]], i32 -13)
; AVX1-NEXT: [[C4:%.*]] = call float @llvm.powi.f32.i32(float [[A4]], i32 -13)
; AVX1-NEXT: [[C5:%.*]] = call float @llvm.powi.f32.i32(float [[A5]], i32 -13)
; AVX1-NEXT: [[C6:%.*]] = call float @llvm.powi.f32.i32(float [[A6]], i32 -13)
; AVX1-NEXT: [[C7:%.*]] = call float @llvm.powi.f32.i32(float [[A7]], i32 -13)
; AVX1-NEXT: [[C8:%.*]] = call float @llvm.powi.f32.i32(float [[A8]], i32 -13)
; AVX1-NEXT: [[C9:%.*]] = call float @llvm.powi.f32.i32(float [[A9]], i32 -13)
; AVX1-NEXT: [[C10:%.*]] = call float @llvm.powi.f32.i32(float [[A10]], i32 -13)
; AVX1-NEXT: [[C11:%.*]] = call float @llvm.powi.f32.i32(float [[A11]], i32 -13)
; AVX1-NEXT: [[C12:%.*]] = call float @llvm.powi.f32.i32(float [[A12]], i32 -13)
; AVX1-NEXT: [[C13:%.*]] = call float @llvm.powi.f32.i32(float [[A13]], i32 -13)
; AVX1-NEXT: [[C14:%.*]] = call float @llvm.powi.f32.i32(float [[A14]], i32 -13)
; AVX1-NEXT: [[C15:%.*]] = call float @llvm.powi.f32.i32(float [[A15]], i32 -13)
; AVX1-NEXT: [[R0:%.*]] = insertelement <16 x float> undef, float [[C0]], i32 0
; AVX1-NEXT: [[R1:%.*]] = insertelement <16 x float> [[R0]], float [[C1]], i32 1
; AVX1-NEXT: [[R2:%.*]] = insertelement <16 x float> [[R1]], float [[C2]], i32 2
; AVX1-NEXT: [[R3:%.*]] = insertelement <16 x float> [[R2]], float [[C3]], i32 3
; AVX1-NEXT: [[R4:%.*]] = insertelement <16 x float> [[R3]], float [[C4]], i32 4
; AVX1-NEXT: [[R5:%.*]] = insertelement <16 x float> [[R4]], float [[C5]], i32 5
; AVX1-NEXT: [[R6:%.*]] = insertelement <16 x float> [[R5]], float [[C6]], i32 6
; AVX1-NEXT: [[R7:%.*]] = insertelement <16 x float> [[R6]], float [[C7]], i32 7
; AVX1-NEXT: [[R8:%.*]] = insertelement <16 x float> [[R7]], float [[C8]], i32 8
; AVX1-NEXT: [[R9:%.*]] = insertelement <16 x float> [[R8]], float [[C9]], i32 9
; AVX1-NEXT: [[R10:%.*]] = insertelement <16 x float> [[R9]], float [[C10]], i32 10
; AVX1-NEXT: [[R11:%.*]] = insertelement <16 x float> [[R10]], float [[C11]], i32 11
; AVX1-NEXT: [[R12:%.*]] = insertelement <16 x float> [[R11]], float [[C12]], i32 12
; AVX1-NEXT: [[R13:%.*]] = insertelement <16 x float> [[R12]], float [[C13]], i32 13
; AVX1-NEXT: [[R14:%.*]] = insertelement <16 x float> [[R13]], float [[C14]], i32 14
; AVX1-NEXT: [[R15:%.*]] = insertelement <16 x float> [[R14]], float [[C15]], i32 15
; AVX1-NEXT: ret <16 x float> [[R15]]
;
; AVX2-LABEL: @buildvector_powi_16f32_n13(
; AVX2-NEXT: [[TMP1:%.*]] = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> [[A:%.*]], i32 -13)
; AVX2-NEXT: ret <16 x float> [[TMP1]]
;
; AVX512-LABEL: @buildvector_powi_16f32_n13(
; AVX512-NEXT: [[TMP1:%.*]] = call <16 x float> @llvm.powi.v16f32.i32(<16 x float> [[A:%.*]], i32 -13)
; AVX512-NEXT: ret <16 x float> [[TMP1]]
;
%a0 = extractelement <16 x float> %a, i32 0
%a1 = extractelement <16 x float> %a, i32 1
%a2 = extractelement <16 x float> %a, i32 2
%a3 = extractelement <16 x float> %a, i32 3
%a4 = extractelement <16 x float> %a, i32 4
%a5 = extractelement <16 x float> %a, i32 5
%a6 = extractelement <16 x float> %a, i32 6
%a7 = extractelement <16 x float> %a, i32 7
%a8 = extractelement <16 x float> %a, i32 8
%a9 = extractelement <16 x float> %a, i32 9
%a10 = extractelement <16 x float> %a, i32 10
%a11 = extractelement <16 x float> %a, i32 11
%a12 = extractelement <16 x float> %a, i32 12
%a13 = extractelement <16 x float> %a, i32 13
%a14 = extractelement <16 x float> %a, i32 14
%a15 = extractelement <16 x float> %a, i32 15
%c0 = call float @llvm.powi.f32(float %a0 , i32 -13)
%c1 = call float @llvm.powi.f32(float %a1 , i32 -13)
%c2 = call float @llvm.powi.f32(float %a2 , i32 -13)
%c3 = call float @llvm.powi.f32(float %a3 , i32 -13)
%c4 = call float @llvm.powi.f32(float %a4 , i32 -13)
%c5 = call float @llvm.powi.f32(float %a5 , i32 -13)
%c6 = call float @llvm.powi.f32(float %a6 , i32 -13)
%c7 = call float @llvm.powi.f32(float %a7 , i32 -13)
%c8 = call float @llvm.powi.f32(float %a8 , i32 -13)
%c9 = call float @llvm.powi.f32(float %a9 , i32 -13)
%c10 = call float @llvm.powi.f32(float %a10 , i32 -13)
%c11 = call float @llvm.powi.f32(float %a11 , i32 -13)
%c12 = call float @llvm.powi.f32(float %a12 , i32 -13)
%c13 = call float @llvm.powi.f32(float %a13 , i32 -13)
%c14 = call float @llvm.powi.f32(float %a14 , i32 -13)
%c15 = call float @llvm.powi.f32(float %a15 , i32 -13)
%r0 = insertelement <16 x float> undef, float %c0 , i32 0
%r1 = insertelement <16 x float> %r0 , float %c1 , i32 1
%r2 = insertelement <16 x float> %r1 , float %c2 , i32 2
%r3 = insertelement <16 x float> %r2 , float %c3 , i32 3
%r4 = insertelement <16 x float> %r3 , float %c4 , i32 4
%r5 = insertelement <16 x float> %r4 , float %c5 , i32 5
%r6 = insertelement <16 x float> %r5 , float %c6 , i32 6
%r7 = insertelement <16 x float> %r6 , float %c7 , i32 7
%r8 = insertelement <16 x float> %r7 , float %c8 , i32 8
%r9 = insertelement <16 x float> %r8 , float %c9 , i32 9
%r10 = insertelement <16 x float> %r9 , float %c10, i32 10
%r11 = insertelement <16 x float> %r10, float %c11, i32 11
%r12 = insertelement <16 x float> %r11, float %c12, i32 12
%r13 = insertelement <16 x float> %r12, float %c13, i32 13
%r14 = insertelement <16 x float> %r13, float %c14, i32 14
%r15 = insertelement <16 x float> %r14, float %c15, i32 15
ret <16 x float> %r15
}
declare float @llvm.powi.f32(float, i32)
declare double @llvm.powi.f64(double, i32)